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arm64: dts: qcom: fix indentation

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Correct indentation to use only tabs.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230416101134.95686-1-krzysztof.kozlowski@linaro.org
This commit is contained in:
Krzysztof Kozlowski 2023-04-16 12:11:31 +02:00 committed by Bjorn Andersson
parent 033553c04b
commit f34fbb71ce
8 changed files with 80 additions and 80 deletions
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8
arch/arm64/boot/dts/qcom/msm8996.dtsi
View file

@ -53,8 +53,8 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
compatible = "cache";
cache-level = <2>;
};
};
@ -83,8 +83,8 @@ CPU2: cpu@100 {
#cooling-cells = <2>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
compatible = "cache";
cache-level = <2>;
};
};

4
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View file

@ -60,8 +60,8 @@ L2_0: l2-cache {
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
compatible = "cache";
cache-level = <3>;
};
};
};

2
arch/arm64/boot/dts/qcom/sdm670.dtsi
View file

@ -42,7 +42,7 @@ L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
compatible = "cache";
};
};
};

4
arch/arm64/boot/dts/qcom/sdm845.dtsi
View file

@ -110,8 +110,8 @@ L2_0: l2-cache {
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
compatible = "cache";
cache-level = <3>;
};
};
};

34
arch/arm64/boot/dts/qcom/sm6375.dtsi
View file

@ -48,10 +48,10 @@ CPU0: cpu@0 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
compatible = "cache";
};
};
};
@ -68,8 +68,8 @@ CPU1: cpu@100 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
@ -85,8 +85,8 @@ CPU2: cpu@200 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
@ -102,8 +102,8 @@ CPU3: cpu@300 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
@ -119,8 +119,8 @@ CPU4: cpu@400 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
@ -136,8 +136,8 @@ CPU5: cpu@500 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
@ -153,8 +153,8 @@ CPU6: cpu@600 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
@ -170,8 +170,8 @@ CPU7: cpu@700 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
next-level-cache = <&L3_0>;
};
};

4
arch/arm64/boot/dts/qcom/sm8150.dtsi
View file

@ -65,8 +65,8 @@ L2_0: l2-cache {
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
compatible = "cache";
cache-level = <3>;
};
};
};

52
arch/arm64/boot/dts/qcom/sm8350.dtsi
View file

@ -58,12 +58,12 @@ CPU0: cpu@0 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
compatible = "cache";
cache-level = <3>;
};
};
};
@ -80,9 +80,9 @@ CPU1: cpu@100 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@ -98,9 +98,9 @@ CPU2: cpu@200 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@ -116,9 +116,9 @@ CPU3: cpu@300 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@ -134,9 +134,9 @@ CPU4: cpu@400 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@ -152,9 +152,9 @@ CPU5: cpu@500 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@ -170,9 +170,9 @@ CPU6: cpu@600 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@ -188,9 +188,9 @@ CPU7: cpu@700 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};

52
arch/arm64/boot/dts/qcom/sm8450.dtsi
View file

@ -57,12 +57,12 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
compatible = "cache";
cache-level = <3>;
};
};
};
@ -79,9 +79,9 @@ CPU1: cpu@100 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@ -97,9 +97,9 @@ CPU2: cpu@200 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@ -115,9 +115,9 @@ CPU3: cpu@300 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@ -133,9 +133,9 @@ CPU4: cpu@400 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 1>;
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@ -151,9 +151,9 @@ CPU5: cpu@500 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 1>;
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@ -169,9 +169,9 @@ CPU6: cpu@600 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 1>;
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
@ -187,9 +187,9 @@ CPU7: cpu@700 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 2>;
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};