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https://github.com/torvalds/linux
synced 2024-09-06 18:01:05 +00:00
powerpc/fsl_msi: add MSIIR1 support for MPIC v4.3
The original MPIC MSI bank contains 8 registers, MPIC v4.3 MSI bank contains 16 registers, and this patch adds NR_MSI_REG_MAX and NR_MSI_IRQS_MAX to describe the maximum capability of MSI bank. MPIC v4.3 provides MSIIR1 to index these 16 MSI registers. MSIIR1 uses different bits definition than MSIIR. This patch adds ibs_shift and srs_shift to indicate the bits definition of the MSIIR and MSIIR1, so the same code can handle the MSIIR and MSIIR1 simultaneously. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> [scottwood@freescale.com: reinstated static on all_avail] Signed-off-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
parent
6d854acd24
commit
f31dd9443a
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@ -28,6 +28,18 @@
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#include "fsl_msi.h"
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#include "fsl_msi.h"
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#include "fsl_pci.h"
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#include "fsl_pci.h"
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#define MSIIR_OFFSET_MASK 0xfffff
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#define MSIIR_IBS_SHIFT 0
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#define MSIIR_SRS_SHIFT 5
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#define MSIIR1_IBS_SHIFT 4
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#define MSIIR1_SRS_SHIFT 0
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#define MSI_SRS_MASK 0xf
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#define MSI_IBS_MASK 0x1f
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#define msi_hwirq(msi, msir_index, intr_index) \
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((msir_index) << (msi)->srs_shift | \
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((intr_index) << (msi)->ibs_shift))
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static LIST_HEAD(msi_head);
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static LIST_HEAD(msi_head);
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struct fsl_msi_feature {
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struct fsl_msi_feature {
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@ -80,18 +92,19 @@ static const struct irq_domain_ops fsl_msi_host_ops = {
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static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
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static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
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{
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{
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int rc;
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int rc, hwirq;
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rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS,
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rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS_MAX,
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msi_data->irqhost->of_node);
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msi_data->irqhost->of_node);
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if (rc)
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if (rc)
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return rc;
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return rc;
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rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap);
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/*
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if (rc < 0) {
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* Reserve all the hwirqs
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msi_bitmap_free(&msi_data->bitmap);
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* The available hwirqs will be released in fsl_msi_setup_hwirq()
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return rc;
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*/
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}
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for (hwirq = 0; hwirq < NR_MSI_IRQS_MAX; hwirq++)
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msi_bitmap_reserve_hwirq(&msi_data->bitmap, hwirq);
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return 0;
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return 0;
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}
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}
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@ -144,8 +157,9 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
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msg->data = hwirq;
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msg->data = hwirq;
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pr_debug("%s: allocated srs: %d, ibs: %d\n",
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pr_debug("%s: allocated srs: %d, ibs: %d\n", __func__,
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__func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
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(hwirq >> msi_data->srs_shift) & MSI_SRS_MASK,
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(hwirq >> msi_data->ibs_shift) & MSI_IBS_MASK);
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}
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}
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static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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@ -255,7 +269,7 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
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msir_index = cascade_data->index;
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msir_index = cascade_data->index;
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if (msir_index >= NR_MSI_REG)
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if (msir_index >= NR_MSI_REG_MAX)
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cascade_irq = NO_IRQ;
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cascade_irq = NO_IRQ;
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irqd_set_chained_irq_inprogress(idata);
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irqd_set_chained_irq_inprogress(idata);
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@ -285,8 +299,8 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
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intr_index = ffs(msir_value) - 1;
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intr_index = ffs(msir_value) - 1;
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cascade_irq = irq_linear_revmap(msi_data->irqhost,
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cascade_irq = irq_linear_revmap(msi_data->irqhost,
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msir_index * IRQS_PER_MSI_REG +
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msi_hwirq(msi_data, msir_index,
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intr_index + have_shift);
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intr_index + have_shift));
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if (cascade_irq != NO_IRQ)
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if (cascade_irq != NO_IRQ)
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generic_handle_irq(cascade_irq);
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generic_handle_irq(cascade_irq);
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have_shift += intr_index + 1;
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have_shift += intr_index + 1;
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@ -316,7 +330,7 @@ static int fsl_of_msi_remove(struct platform_device *ofdev)
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if (msi->list.prev != NULL)
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if (msi->list.prev != NULL)
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list_del(&msi->list);
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list_del(&msi->list);
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for (i = 0; i < NR_MSI_REG; i++) {
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for (i = 0; i < NR_MSI_REG_MAX; i++) {
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virq = msi->msi_virqs[i];
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virq = msi->msi_virqs[i];
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if (virq != NO_IRQ) {
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if (virq != NO_IRQ) {
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cascade_data = irq_get_handler_data(virq);
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cascade_data = irq_get_handler_data(virq);
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@ -339,7 +353,7 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
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int offset, int irq_index)
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int offset, int irq_index)
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{
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{
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struct fsl_msi_cascade_data *cascade_data = NULL;
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struct fsl_msi_cascade_data *cascade_data = NULL;
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int virt_msir;
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int virt_msir, i;
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virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
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virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
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if (virt_msir == NO_IRQ) {
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if (virt_msir == NO_IRQ) {
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@ -360,6 +374,11 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
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irq_set_handler_data(virt_msir, cascade_data);
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irq_set_handler_data(virt_msir, cascade_data);
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irq_set_chained_handler(virt_msir, fsl_msi_cascade);
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irq_set_chained_handler(virt_msir, fsl_msi_cascade);
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/* Release the hwirqs corresponding to this MSI register */
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for (i = 0; i < IRQS_PER_MSI_REG; i++)
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msi_bitmap_free_hwirqs(&msi->bitmap,
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msi_hwirq(msi, offset, i), 1);
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return 0;
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return 0;
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}
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}
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@ -368,13 +387,12 @@ static int fsl_of_msi_probe(struct platform_device *dev)
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{
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{
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const struct of_device_id *match;
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const struct of_device_id *match;
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struct fsl_msi *msi;
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struct fsl_msi *msi;
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struct resource res;
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struct resource res, msiir;
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int err, i, j, irq_index, count;
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int err, i, j, irq_index, count;
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const u32 *p;
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const u32 *p;
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const struct fsl_msi_feature *features;
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const struct fsl_msi_feature *features;
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int len;
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int len;
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u32 offset;
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u32 offset;
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static const u32 all_avail[] = { 0, NR_MSI_IRQS };
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match = of_match_device(fsl_of_msi_ids, &dev->dev);
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match = of_match_device(fsl_of_msi_ids, &dev->dev);
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if (!match)
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if (!match)
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@ -391,7 +409,7 @@ static int fsl_of_msi_probe(struct platform_device *dev)
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platform_set_drvdata(dev, msi);
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platform_set_drvdata(dev, msi);
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msi->irqhost = irq_domain_add_linear(dev->dev.of_node,
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msi->irqhost = irq_domain_add_linear(dev->dev.of_node,
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NR_MSI_IRQS, &fsl_msi_host_ops, msi);
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NR_MSI_IRQS_MAX, &fsl_msi_host_ops, msi);
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if (msi->irqhost == NULL) {
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if (msi->irqhost == NULL) {
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dev_err(&dev->dev, "No memory for MSI irqhost\n");
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dev_err(&dev->dev, "No memory for MSI irqhost\n");
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}
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}
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msi->msiir_offset =
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msi->msiir_offset =
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features->msiir_offset + (res.start & 0xfffff);
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features->msiir_offset + (res.start & 0xfffff);
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/*
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* First read the MSIIR/MSIIR1 offset from dts
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* On failure use the hardcode MSIIR offset
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*/
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if (of_address_to_resource(dev->dev.of_node, 1, &msiir))
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msi->msiir_offset = features->msiir_offset +
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(res.start & MSIIR_OFFSET_MASK);
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else
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msi->msiir_offset = msiir.start & MSIIR_OFFSET_MASK;
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}
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}
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msi->feature = features->fsl_pic_ip;
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msi->feature = features->fsl_pic_ip;
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}
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}
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p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
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p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
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if (p && len % (2 * sizeof(u32)) != 0) {
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dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
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__func__);
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err = -EINVAL;
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goto error_out;
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}
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if (!p) {
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if (of_device_is_compatible(dev->dev.of_node, "fsl,mpic-msi-v4.3")) {
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p = all_avail;
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msi->srs_shift = MSIIR1_SRS_SHIFT;
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len = sizeof(all_avail);
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msi->ibs_shift = MSIIR1_IBS_SHIFT;
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}
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if (p)
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dev_warn(&dev->dev, "%s: dose not support msi-available-ranges property\n",
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__func__);
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for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) {
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for (irq_index = 0; irq_index < NR_MSI_REG_MSIIR1;
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if (p[i * 2] % IRQS_PER_MSI_REG ||
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irq_index++) {
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p[i * 2 + 1] % IRQS_PER_MSI_REG) {
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err = fsl_msi_setup_hwirq(msi, dev,
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printk(KERN_WARNING "%s: %s: msi available range of %u at %u is not IRQ-aligned\n",
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irq_index, irq_index);
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__func__, dev->dev.of_node->full_name,
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if (err)
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p[i * 2 + 1], p[i * 2]);
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goto error_out;
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}
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} else {
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static const u32 all_avail[] =
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{ 0, NR_MSI_REG_MSIIR * IRQS_PER_MSI_REG };
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msi->srs_shift = MSIIR_SRS_SHIFT;
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msi->ibs_shift = MSIIR_IBS_SHIFT;
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if (p && len % (2 * sizeof(u32)) != 0) {
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dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
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__func__);
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err = -EINVAL;
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err = -EINVAL;
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goto error_out;
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goto error_out;
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}
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}
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offset = p[i * 2] / IRQS_PER_MSI_REG;
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if (!p) {
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count = p[i * 2 + 1] / IRQS_PER_MSI_REG;
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p = all_avail;
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len = sizeof(all_avail);
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}
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for (j = 0; j < count; j++, irq_index++) {
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for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) {
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err = fsl_msi_setup_hwirq(msi, dev, offset + j, irq_index);
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if (p[i * 2] % IRQS_PER_MSI_REG ||
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if (err)
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p[i * 2 + 1] % IRQS_PER_MSI_REG) {
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pr_warn("%s: %s: msi available range of %u at %u is not IRQ-aligned\n",
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__func__, dev->dev.of_node->full_name,
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p[i * 2 + 1], p[i * 2]);
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err = -EINVAL;
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goto error_out;
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goto error_out;
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}
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offset = p[i * 2] / IRQS_PER_MSI_REG;
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count = p[i * 2 + 1] / IRQS_PER_MSI_REG;
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for (j = 0; j < count; j++, irq_index++) {
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err = fsl_msi_setup_hwirq(msi, dev, offset + j,
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irq_index);
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if (err)
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goto error_out;
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}
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}
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}
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}
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}
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@ -507,6 +559,10 @@ static const struct of_device_id fsl_of_msi_ids[] = {
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.compatible = "fsl,mpic-msi",
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.compatible = "fsl,mpic-msi",
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.data = &mpic_msi_feature,
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.data = &mpic_msi_feature,
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},
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},
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{
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.compatible = "fsl,mpic-msi-v4.3",
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.data = &mpic_msi_feature,
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},
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{
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{
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.compatible = "fsl,ipic-msi",
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.compatible = "fsl,ipic-msi",
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.data = &ipic_msi_feature,
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.data = &ipic_msi_feature,
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@ -16,9 +16,11 @@
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#include <linux/of.h>
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#include <linux/of.h>
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#include <asm/msi_bitmap.h>
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#include <asm/msi_bitmap.h>
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#define NR_MSI_REG 8
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#define NR_MSI_REG_MSIIR 8 /* MSIIR can index 8 MSI registers */
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#define NR_MSI_REG_MSIIR1 16 /* MSIIR1 can index 16 MSI registers */
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#define NR_MSI_REG_MAX NR_MSI_REG_MSIIR1
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#define IRQS_PER_MSI_REG 32
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#define IRQS_PER_MSI_REG 32
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#define NR_MSI_IRQS (NR_MSI_REG * IRQS_PER_MSI_REG)
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#define NR_MSI_IRQS_MAX (NR_MSI_REG_MAX * IRQS_PER_MSI_REG)
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#define FSL_PIC_IP_MASK 0x0000000F
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#define FSL_PIC_IP_MASK 0x0000000F
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#define FSL_PIC_IP_MPIC 0x00000001
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#define FSL_PIC_IP_MPIC 0x00000001
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@ -31,9 +33,11 @@ struct fsl_msi {
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unsigned long cascade_irq;
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unsigned long cascade_irq;
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u32 msiir_offset; /* Offset of MSIIR, relative to start of CCSR */
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u32 msiir_offset; /* Offset of MSIIR, relative to start of CCSR */
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u32 ibs_shift; /* Shift of interrupt bit select */
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u32 srs_shift; /* Shift of the shared interrupt register select */
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void __iomem *msi_regs;
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void __iomem *msi_regs;
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u32 feature;
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u32 feature;
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int msi_virqs[NR_MSI_REG];
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int msi_virqs[NR_MSI_REG_MAX];
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struct msi_bitmap bitmap;
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struct msi_bitmap bitmap;
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