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ACPICA: MADT: Add RISC-V INTC interrupt controller
ACPICA commit bd6d1ae1e13abe78e149c8b61b4bc7bc7feab015 The ECR to add RISC-V INTC interrupt controller is approved by the UEFI forum and will be available in the next revision of the ACPI specification. Link: https://github.com/acpica/acpica/commit/bd6d1ae1 Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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@ -891,7 +891,8 @@ enum acpi_madt_type {
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ACPI_MADT_TYPE_MSI_PIC = 21,
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ACPI_MADT_TYPE_BIO_PIC = 22,
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ACPI_MADT_TYPE_LPC_PIC = 23,
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ACPI_MADT_TYPE_RESERVED = 24, /* 24 to 0x7F are reserved */
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ACPI_MADT_TYPE_RINTC = 24,
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ACPI_MADT_TYPE_RESERVED = 25, /* 25 to 0x7F are reserved */
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ACPI_MADT_TYPE_OEM_RESERVED = 0x80 /* 0x80 to 0xFF are reserved for OEM use */
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};
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@ -1251,6 +1252,24 @@ enum acpi_madt_lpc_pic_version {
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ACPI_MADT_LPC_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
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};
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/* 24: RISC-V INTC */
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struct acpi_madt_rintc {
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struct acpi_subtable_header header;
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u8 version;
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u8 reserved;
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u32 flags;
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u64 hart_id;
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u32 uid; /* ACPI processor UID */
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};
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/* Values for RISC-V INTC Version field above */
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enum acpi_madt_rintc_version {
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ACPI_MADT_RINTC_VERSION_NONE = 0,
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ACPI_MADT_RINTC_VERSION_V1 = 1,
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ACPI_MADT_RINTC_VERSION_RESERVED = 2 /* 2 and greater are reserved */
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};
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/* 80: OEM data */
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struct acpi_madt_oem_data {
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