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powerpc/32s: Move _tlbie() and _tlbia() in a new file
_tlbie() and _tlbia() are used only on 603 cores while the other functions are used only on cores having a hash table. Move them into a new file named nohash_low.S Add mmu_hash_lock var is used by both, it needs to go in a common file. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/9a265b1b17a64153463d361280cb4b43eb1266a4.1603348103.git.christophe.leroy@csgroup.eu
This commit is contained in:
Christophe Leroy
Michael Ellerman
parent
b91280f3f3
commit
f265512582
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@ -6,4 +6,4 @@ ifdef CONFIG_KASAN
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CFLAGS_mmu.o += -DDISABLE_BRANCH_PROFILING
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endif
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obj-y += mmu.o hash_low.o mmu_context.o tlb.o
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obj-y += mmu.o hash_low.o mmu_context.o tlb.o nohash_low.o
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@ -26,13 +26,6 @@
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#include <asm/feature-fixups.h>
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#include <asm/code-patching-asm.h>
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#ifdef CONFIG_SMP
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.section .bss
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.align 2
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mmu_hash_lock:
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.space 4
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#endif /* CONFIG_SMP */
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/*
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* Load a PTE into the hash table, if possible.
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* The address is in r4, and r3 contains an access flag:
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@ -618,74 +611,3 @@ _GLOBAL(flush_hash_pages)
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.previous
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EXPORT_SYMBOL(flush_hash_pages)
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_ASM_NOKPROBE_SYMBOL(flush_hash_pages)
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/*
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* Flush an entry from the TLB
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*/
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#ifdef CONFIG_SMP
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_GLOBAL(_tlbie)
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lwz r8,TASK_CPU(r2)
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oris r8,r8,11
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mfmsr r10
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rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
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rlwinm r0,r0,0,28,26 /* clear DR */
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mtmsr r0
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isync
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lis r9,mmu_hash_lock@h
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ori r9,r9,mmu_hash_lock@l
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tophys(r9,r9)
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10: lwarx r7,0,r9
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cmpwi 0,r7,0
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bne- 10b
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stwcx. r8,0,r9
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bne- 10b
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eieio
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tlbie r3
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sync
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TLBSYNC
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li r0,0
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stw r0,0(r9) /* clear mmu_hash_lock */
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mtmsr r10
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isync
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blr
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_ASM_NOKPROBE_SYMBOL(_tlbie)
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#endif /* CONFIG_SMP */
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/*
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* Flush the entire TLB. 603/603e only
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*/
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_GLOBAL(_tlbia)
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#if defined(CONFIG_SMP)
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lwz r8,TASK_CPU(r2)
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oris r8,r8,10
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mfmsr r10
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rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
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rlwinm r0,r0,0,28,26 /* clear DR */
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mtmsr r0
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isync
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lis r9,mmu_hash_lock@h
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ori r9,r9,mmu_hash_lock@l
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tophys(r9,r9)
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10: lwarx r7,0,r9
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cmpwi 0,r7,0
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bne- 10b
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stwcx. r8,0,r9
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bne- 10b
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#endif /* CONFIG_SMP */
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li r5, 32
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lis r4, KERNELBASE@h
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mtctr r5
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sync
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0: tlbie r4
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addi r4, r4, 0x1000
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bdnz 0b
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sync
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#ifdef CONFIG_SMP
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TLBSYNC
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li r0,0
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stw r0,0(r9) /* clear mmu_hash_lock */
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mtmsr r10
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isync
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#endif /* CONFIG_SMP */
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blr
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_ASM_NOKPROBE_SYMBOL(_tlbia)
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@ -46,6 +46,10 @@ static struct batrange { /* stores address ranges mapped by BATs */
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phys_addr_t phys;
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} bat_addrs[8];
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#ifdef CONFIG_SMP
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unsigned long mmu_hash_lock;
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#endif
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/*
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* Return PA for this VA if it is mapped by a BAT, or 0
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*/
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80
arch/powerpc/mm/book3s32/nohash_low.S
Normal file
80
arch/powerpc/mm/book3s32/nohash_low.S
Normal file
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@ -0,0 +1,80 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* This file contains low-level assembler routines for managing
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* the PowerPC 603 tlb invalidation.
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*/
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#include <asm/page.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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/*
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* Flush an entry from the TLB
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*/
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#ifdef CONFIG_SMP
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_GLOBAL(_tlbie)
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lwz r8,TASK_CPU(r2)
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oris r8,r8,11
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mfmsr r10
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rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
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rlwinm r0,r0,0,28,26 /* clear DR */
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mtmsr r0
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isync
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lis r9,mmu_hash_lock@h
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ori r9,r9,mmu_hash_lock@l
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tophys(r9,r9)
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10: lwarx r7,0,r9
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cmpwi 0,r7,0
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bne- 10b
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stwcx. r8,0,r9
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bne- 10b
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eieio
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tlbie r3
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sync
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TLBSYNC
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li r0,0
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stw r0,0(r9) /* clear mmu_hash_lock */
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mtmsr r10
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isync
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blr
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_ASM_NOKPROBE_SYMBOL(_tlbie)
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#endif /* CONFIG_SMP */
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/*
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* Flush the entire TLB. 603/603e only
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*/
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_GLOBAL(_tlbia)
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#if defined(CONFIG_SMP)
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lwz r8,TASK_CPU(r2)
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oris r8,r8,10
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mfmsr r10
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rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
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rlwinm r0,r0,0,28,26 /* clear DR */
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mtmsr r0
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isync
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lis r9,mmu_hash_lock@h
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ori r9,r9,mmu_hash_lock@l
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tophys(r9,r9)
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10: lwarx r7,0,r9
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cmpwi 0,r7,0
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bne- 10b
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stwcx. r8,0,r9
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bne- 10b
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#endif /* CONFIG_SMP */
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li r5, 32
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lis r4, KERNELBASE@h
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mtctr r5
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sync
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0: tlbie r4
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addi r4, r4, 0x1000
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bdnz 0b
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sync
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#ifdef CONFIG_SMP
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TLBSYNC
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li r0,0
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stw r0,0(r9) /* clear mmu_hash_lock */
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mtmsr r10
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isync
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#endif /* CONFIG_SMP */
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blr
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_ASM_NOKPROBE_SYMBOL(_tlbia)
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