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A set of interrupt chip driver fixes:
- Ensure the atomicity of affinity updates in the GIC driver. - Don't try to sleep in atomic context when waiting for the GICv4.1 to respond. Use polling instead. - Typo fixes in Kconfig and warnings. -----BEGIN PGP SIGNATURE----- iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAl8B8sETHHRnbHhAbGlu dXRyb25peC5kZQAKCRCmGPVMDXSYoQ2AEAC/W+PkCmAqhTrsr2iHn3JOdXEVW21T Ybivz2Bbf07kOy3bgvuLuo6/tRPh/R8fwjmrhgUZfWUcLQ1c3VSDyPPtmHVrTK8i 0oZLT1Bc2npCdAX2V8UruRyihhbQk52xb6K2OeDqVhpiuwv0PbcBpsT7No1gg5i2 FaH1F160nJG4HrWusmJKLcqvT+4t/ZWCoYKQeBzhxzZLuFvMU/e+PhUhKbr2MXdx jBOWv+3DeEd88soxTNsrhsJPdx2i9j1WdSy2kJRhm4DTRWvWxkZ/96ugzWJqIHxV XZsaKvAyQe9Ft62n44gkEH8RoKyZfCNSQkj3csi14W8WfDkpjCrJZeEh6gHFXewk GbUJOC9IuwEkhkKRBDD/C0+9v0YxpW1uG/cC2+vIBxZvGqUm9X96UfuhC5F86tcJ gEUEX0CvMWeBF0TejuOgi72FXlCFpcTGzTLSD0y8RS1I66i226AzkOAsXoZL8OdT PLdLor7qWMFLrq+ehTkaojCV946j5ClwMK5a95By22QufID04iSsisT5MZqhladO BdVtHPbApnrB0AXMzMHd69PoAGNeknVdZwYTNE9lNsV8W1WPJxfpnINNX7EYQL77 SOJOEbWa8h7aToy9GJpwODhYByyqeIqHMbvIeWAo3wx9GD5Kt0aqWryZa/b4PehR W+0VyqdqSkTGIA== =ZZ0g -----END PGP SIGNATURE----- Merge tag 'irq-urgent-2020-07-05' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq fixes from Thomas Gleixner: "A set of interrupt chip driver fixes: - Ensure the atomicity of affinity updates in the GIC driver - Don't try to sleep in atomic context when waiting for the GICv4.1 to respond. Use polling instead. - Typo fixes in Kconfig and warnings" * tag 'irq-urgent-2020-07-05' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/gic: Atomically update affinity irqchip/riscv-intc: Fix a typo in a pr_warn() irqchip/gic-v4.1: Use readx_poll_timeout_atomic() to fix sleep in atomic irqchip/loongson-pci-msi: Fix a typo in Kconfig
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commit
f23dbe1893
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@ -563,7 +563,7 @@ config LOONGSON_PCH_PIC
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Support for the Loongson PCH PIC Controller.
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config LOONGSON_PCH_MSI
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bool "Loongson PCH PIC Controller"
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bool "Loongson PCH MSI Controller"
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depends on MACH_LOONGSON64 || COMPILE_TEST
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depends on PCI
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default MACH_LOONGSON64
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@ -3797,10 +3797,10 @@ static void its_wait_vpt_parse_complete(void)
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if (!gic_rdists->has_vpend_valid_dirty)
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return;
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WARN_ON_ONCE(readq_relaxed_poll_timeout(vlpi_base + GICR_VPENDBASER,
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val,
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!(val & GICR_VPENDBASER_Dirty),
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10, 500));
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WARN_ON_ONCE(readq_relaxed_poll_timeout_atomic(vlpi_base + GICR_VPENDBASER,
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val,
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!(val & GICR_VPENDBASER_Dirty),
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10, 500));
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}
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static void its_vpe_schedule(struct its_vpe *vpe)
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@ -329,10 +329,8 @@ static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
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static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
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bool force)
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{
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void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
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unsigned int cpu, shift = (gic_irq(d) % 4) * 8;
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u32 val, mask, bit;
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unsigned long flags;
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void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d);
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unsigned int cpu;
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if (!force)
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cpu = cpumask_any_and(mask_val, cpu_online_mask);
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@ -342,13 +340,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
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if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
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return -EINVAL;
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gic_lock_irqsave(flags);
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mask = 0xff << shift;
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bit = gic_cpu_map[cpu] << shift;
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val = readl_relaxed(reg) & ~mask;
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writel_relaxed(val | bit, reg);
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gic_unlock_irqrestore(flags);
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writeb_relaxed(gic_cpu_map[cpu], reg);
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irq_data_update_effective_affinity(d, cpumask_of(cpu));
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return IRQ_SET_MASK_OK_DONE;
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@ -99,7 +99,7 @@ static int __init riscv_intc_init(struct device_node *node,
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hartid = riscv_of_parent_hartid(node);
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if (hartid < 0) {
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pr_warn("unable to fine hart id for %pOF\n", node);
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pr_warn("unable to find hart id for %pOF\n", node);
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return 0;
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}
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