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remoteproc: mediatek: Fix side effect of mt8195 sram power on
The definition of L1TCM_SRAM_PDN bits on mt8195 is different to mt8192.
L1TCM_SRAM_PDN bits[3:0] control the power of mt8195 L1TCM SRAM.
L1TCM_SRAM_PDN bits[7:4] control the access path to EMI for SCP.
These bits have to be powered on to allow EMI access for SCP.
Bits[7:4] also affect audio DSP because audio DSP and SCP are
placed on the same hardware bus. If SCP cannot access EMI, audio DSP is
blocked too.
L1TCM_SRAM_PDN bits[31:8] are not used.
This fix removes modification of bits[7:4] when power on/off mt8195 SCP
L1TCM. It's because the modification introduces a short period of time
blocking audio DSP to access EMI. This was not a problem until we have
to load both SCP module and audio DSP module. audio DSP needs to access
EMI because it has source/data on DRAM. Audio DSP will have unexpected
behavior when it accesses EMI and the SCP driver blocks the EMI path at
the same time.
Fixes: 79111df414
("remoteproc: mediatek: Support mt8195 scp")
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Link: https://lore.kernel.org/r/20220321060340.10975-1-tinghan.shen@mediatek.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
This commit is contained in:
parent
ce522ba9ef
commit
f20e232d74
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@ -54,6 +54,8 @@
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#define MT8192_CORE0_WDT_IRQ 0x10030
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#define MT8192_CORE0_WDT_CFG 0x10034
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#define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4)
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#define SCP_FW_VER_LEN 32
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#define SCP_SHARE_BUFFER_SIZE 288
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@ -365,22 +365,22 @@ static int mt8183_scp_before_load(struct mtk_scp *scp)
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return 0;
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}
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static void mt8192_power_on_sram(void __iomem *addr)
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static void scp_sram_power_on(void __iomem *addr, u32 reserved_mask)
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{
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int i;
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for (i = 31; i >= 0; i--)
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writel(GENMASK(i, 0), addr);
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writel(GENMASK(i, 0) & ~reserved_mask, addr);
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writel(0, addr);
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}
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static void mt8192_power_off_sram(void __iomem *addr)
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static void scp_sram_power_off(void __iomem *addr, u32 reserved_mask)
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{
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int i;
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writel(0, addr);
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for (i = 0; i < 32; i++)
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writel(GENMASK(i, 0), addr);
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writel(GENMASK(i, 0) & ~reserved_mask, addr);
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}
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static int mt8186_scp_before_load(struct mtk_scp *scp)
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@ -393,7 +393,7 @@ static int mt8186_scp_before_load(struct mtk_scp *scp)
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writel(0x0, scp->reg_base + MT8183_SCP_CLK_DIV_SEL);
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/* Turn on the power of SCP's SRAM before using it. Enable 1 block per time*/
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mt8192_power_on_sram(scp->reg_base + MT8183_SCP_SRAM_PDN);
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scp_sram_power_on(scp->reg_base + MT8183_SCP_SRAM_PDN, 0);
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/* Initialize TCM before loading FW. */
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writel(0x0, scp->reg_base + MT8183_SCP_L1_SRAM_PD);
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@ -412,11 +412,32 @@ static int mt8192_scp_before_load(struct mtk_scp *scp)
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writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET);
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/* enable SRAM clock */
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mt8192_power_on_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_0);
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mt8192_power_on_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_1);
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mt8192_power_on_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_2);
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mt8192_power_on_sram(scp->reg_base + MT8192_L1TCM_SRAM_PDN);
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mt8192_power_on_sram(scp->reg_base + MT8192_CPU0_SRAM_PD);
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scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
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scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
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scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
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scp_sram_power_on(scp->reg_base + MT8192_L1TCM_SRAM_PDN, 0);
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scp_sram_power_on(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
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/* enable MPU for all memory regions */
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writel(0xff, scp->reg_base + MT8192_CORE0_MEM_ATT_PREDEF);
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return 0;
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}
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static int mt8195_scp_before_load(struct mtk_scp *scp)
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{
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/* clear SPM interrupt, SCP2SPM_IPC_CLR */
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writel(0xff, scp->reg_base + MT8192_SCP2SPM_IPC_CLR);
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writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET);
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/* enable SRAM clock */
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scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
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scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
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scp_sram_power_on(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
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scp_sram_power_on(scp->reg_base + MT8192_L1TCM_SRAM_PDN,
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MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS);
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scp_sram_power_on(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
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/* enable MPU for all memory regions */
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writel(0xff, scp->reg_base + MT8192_CORE0_MEM_ATT_PREDEF);
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@ -572,11 +593,25 @@ static void mt8183_scp_stop(struct mtk_scp *scp)
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static void mt8192_scp_stop(struct mtk_scp *scp)
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{
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/* Disable SRAM clock */
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mt8192_power_off_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_0);
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mt8192_power_off_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_1);
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mt8192_power_off_sram(scp->reg_base + MT8192_L2TCM_SRAM_PD_2);
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mt8192_power_off_sram(scp->reg_base + MT8192_L1TCM_SRAM_PDN);
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mt8192_power_off_sram(scp->reg_base + MT8192_CPU0_SRAM_PD);
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scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
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scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
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scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
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scp_sram_power_off(scp->reg_base + MT8192_L1TCM_SRAM_PDN, 0);
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scp_sram_power_off(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
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/* Disable SCP watchdog */
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writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG);
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}
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static void mt8195_scp_stop(struct mtk_scp *scp)
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{
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/* Disable SRAM clock */
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scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_0, 0);
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scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_1, 0);
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scp_sram_power_off(scp->reg_base + MT8192_L2TCM_SRAM_PD_2, 0);
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scp_sram_power_off(scp->reg_base + MT8192_L1TCM_SRAM_PDN,
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MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS);
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scp_sram_power_off(scp->reg_base + MT8192_CPU0_SRAM_PD, 0);
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/* Disable SCP watchdog */
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writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG);
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@ -922,11 +957,11 @@ static const struct mtk_scp_of_data mt8192_of_data = {
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static const struct mtk_scp_of_data mt8195_of_data = {
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.scp_clk_get = mt8195_scp_clk_get,
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.scp_before_load = mt8192_scp_before_load,
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.scp_before_load = mt8195_scp_before_load,
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.scp_irq_handler = mt8192_scp_irq_handler,
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.scp_reset_assert = mt8192_scp_reset_assert,
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.scp_reset_deassert = mt8192_scp_reset_deassert,
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.scp_stop = mt8192_scp_stop,
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.scp_stop = mt8195_scp_stop,
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.scp_da_to_va = mt8192_scp_da_to_va,
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.host_to_scp_reg = MT8192_GIPC_IN_SET,
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.host_to_scp_int_bit = MT8192_HOST_IPC_INT_BIT,
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