mirror of
https://github.com/torvalds/linux
synced 2024-09-20 11:07:02 +00:00
Merge branches 'clk-basic', 'clk-mtk', 'clk-devm-enable' and 'clk-ti-dt' into clk-next
- Remove allwinner workaround logic/compatible in fixed factor code - MediaTek clk driver cleanups - Add reset support to more MediaTek clk drivers - devm helpers for clk_get() + clk_prepare() and clk_enable() * clk-basic: clk: fixed-factor: Introduce *clk_hw_register_fixed_factor_parent_hw() clk: mux: Introduce devm_clk_hw_register_mux_parent_hws() clk: divider: Introduce devm_clk_hw_register_divider_parent_hw() dt-bindings: clock: fixed-factor: Drop Allwinner A10 compatible clk: fixed: Remove Allwinner A10 special-case logic * clk-mtk: clk: mediatek: reset: Add infra_ao reset support for MT8186 dt-bindings: arm: mediatek: Add #reset-cells property for MT8186 dt-bindings: reset: mediatek: Add infra_ao reset index for MT8186 clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195 dt-bindings: reset: mediatek: Add infra_ao reset index for MT8192/MT8195 dt-bindings: arm: mediatek: Add #reset-cells property for MT8192/MT8195 clk: mediatek: reset: Add reset support for simple probe clk: mediatek: reset: Add new register reset function with device clk: mediatek: reset: Change return type for clock reset register function clk: mediatek: reset: Support inuput argument index mode clk: mediatek: reset: Support nonsequence base offsets of reset registers clk: mediatek: reset: Revise structure to control reset register clk: mediatek: reset: Merge and revise reset register function clk: mediatek: reset: Extract common drivers to update function clk: mediatek: reset: Refine and reorder functions in reset.c clk: mediatek: reset: Fix written reset bit offset clk: mediatek: reset: Add reset.h clk: mediatek: Delete MT8192 msdc gate dt-bindings: ARM: Mediatek: Remove msdc binding of MT8192 clock * clk-devm-enable: clk: Remove never used devm_clk_*unregister() clk: Fix pointer casting to prevent oops in devm_clk_release() clk: meson: axg-audio: Don't duplicate devm_clk_get_enabled() clk: Provide new devm_clk helpers for prepared and enabled clocks clk: generalize devm_clk_get() a bit clk: Improve documentation for devm_clk_get() and its optional variant * clk-ti-dt: clk: ti: Stop using legacy clkctrl names for omap4 and 5
This commit is contained in:
Stephen Boyd
commit
f04ed3d9f8
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@ -39,6 +39,9 @@ properties:
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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required:
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- compatible
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- reg
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@ -24,7 +24,6 @@ properties:
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- mediatek,mt8192-imp_iic_wrap_w
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- mediatek,mt8192-imp_iic_wrap_n
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- mediatek,mt8192-msdc_top
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- mediatek,mt8192-msdc
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- mediatek,mt8192-mfgcfg
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- mediatek,mt8192-imgsys
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- mediatek,mt8192-imgsys2
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@ -107,13 +106,6 @@ examples:
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#clock-cells = <1>;
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};
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- |
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msdc: clock-controller@11f60000 {
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compatible = "mediatek,mt8192-msdc";
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reg = <0x11f60000 0x1000>;
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#clock-cells = <1>;
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};
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- |
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mfgcfg: clock-controller@13fbf000 {
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compatible = "mediatek,mt8192-mfgcfg";
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@ -29,6 +29,9 @@ properties:
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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required:
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- compatible
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- reg
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@ -37,6 +37,9 @@ properties:
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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required:
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- compatible
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- reg
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@ -13,7 +13,6 @@ maintainers:
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properties:
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compatible:
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enum:
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- allwinner,sun4i-a10-pll3-2x-clk
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- fixed-factor-clock
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"#clock-cells":
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@ -4,42 +4,101 @@
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#include <linux/export.h>
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#include <linux/gfp.h>
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struct devm_clk_state {
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struct clk *clk;
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void (*exit)(struct clk *clk);
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};
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static void devm_clk_release(struct device *dev, void *res)
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{
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clk_put(*(struct clk **)res);
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struct devm_clk_state *state = res;
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if (state->exit)
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state->exit(state->clk);
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clk_put(state->clk);
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}
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static struct clk *__devm_clk_get(struct device *dev, const char *id,
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struct clk *(*get)(struct device *dev, const char *id),
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int (*init)(struct clk *clk),
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void (*exit)(struct clk *clk))
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{
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struct devm_clk_state *state;
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struct clk *clk;
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int ret;
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state = devres_alloc(devm_clk_release, sizeof(*state), GFP_KERNEL);
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if (!state)
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return ERR_PTR(-ENOMEM);
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clk = get(dev, id);
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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goto err_clk_get;
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}
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if (init) {
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ret = init(clk);
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if (ret)
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goto err_clk_init;
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}
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state->clk = clk;
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state->exit = exit;
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devres_add(dev, state);
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return clk;
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err_clk_init:
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clk_put(clk);
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err_clk_get:
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devres_free(state);
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return ERR_PTR(ret);
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}
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struct clk *devm_clk_get(struct device *dev, const char *id)
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{
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struct clk **ptr, *clk;
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ptr = devres_alloc(devm_clk_release, sizeof(*ptr), GFP_KERNEL);
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if (!ptr)
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return ERR_PTR(-ENOMEM);
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clk = clk_get(dev, id);
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if (!IS_ERR(clk)) {
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*ptr = clk;
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devres_add(dev, ptr);
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} else {
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devres_free(ptr);
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}
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return clk;
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return __devm_clk_get(dev, id, clk_get, NULL, NULL);
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}
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EXPORT_SYMBOL(devm_clk_get);
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struct clk *devm_clk_get_prepared(struct device *dev, const char *id)
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{
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return __devm_clk_get(dev, id, clk_get, clk_prepare, clk_unprepare);
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}
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EXPORT_SYMBOL_GPL(devm_clk_get_prepared);
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struct clk *devm_clk_get_enabled(struct device *dev, const char *id)
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{
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return __devm_clk_get(dev, id, clk_get,
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clk_prepare_enable, clk_disable_unprepare);
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}
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EXPORT_SYMBOL_GPL(devm_clk_get_enabled);
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struct clk *devm_clk_get_optional(struct device *dev, const char *id)
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{
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struct clk *clk = devm_clk_get(dev, id);
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if (clk == ERR_PTR(-ENOENT))
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return NULL;
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return clk;
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return __devm_clk_get(dev, id, clk_get_optional, NULL, NULL);
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}
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EXPORT_SYMBOL(devm_clk_get_optional);
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struct clk *devm_clk_get_optional_prepared(struct device *dev, const char *id)
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{
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return __devm_clk_get(dev, id, clk_get_optional,
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clk_prepare, clk_unprepare);
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}
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EXPORT_SYMBOL_GPL(devm_clk_get_optional_prepared);
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struct clk *devm_clk_get_optional_enabled(struct device *dev, const char *id)
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{
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return __devm_clk_get(dev, id, clk_get_optional,
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clk_prepare_enable, clk_disable_unprepare);
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}
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EXPORT_SYMBOL_GPL(devm_clk_get_optional_enabled);
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struct clk_bulk_devres {
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struct clk_bulk_data *clks;
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int num_clks;
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@ -78,7 +78,8 @@ static void devm_clk_hw_register_fixed_factor_release(struct device *dev, void *
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static struct clk_hw *
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__clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
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const char *name, const char *parent_name, int index,
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const char *name, const char *parent_name,
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const struct clk_hw *parent_hw, int index,
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unsigned long flags, unsigned int mult, unsigned int div,
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bool devm)
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{
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@ -110,6 +111,8 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
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init.flags = flags;
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if (parent_name)
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init.parent_names = &parent_name;
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else if (parent_hw)
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init.parent_hws = &parent_hw;
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else
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init.parent_data = &pdata;
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init.num_parents = 1;
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@ -148,16 +151,48 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
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const char *name, unsigned int index, unsigned long flags,
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unsigned int mult, unsigned int div)
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{
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return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, index,
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return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, index,
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flags, mult, div, true);
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}
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EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_index);
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/**
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* devm_clk_hw_register_fixed_factor_parent_hw - Register a fixed factor clock with
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* pointer to parent clock
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* @dev: device that is registering this clock
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* @name: name of this clock
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* @parent_hw: pointer to parent clk
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* @flags: fixed factor flags
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* @mult: multiplier
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* @div: divider
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*
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* Return: Pointer to fixed factor clk_hw structure that was registered or
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* an error pointer.
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*/
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struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev,
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const char *name, const struct clk_hw *parent_hw,
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unsigned long flags, unsigned int mult, unsigned int div)
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{
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return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw,
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-1, flags, mult, div, true);
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}
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EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_parent_hw);
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struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev,
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const char *name, const struct clk_hw *parent_hw,
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unsigned long flags, unsigned int mult, unsigned int div)
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{
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return __clk_hw_register_fixed_factor(dev, NULL, name, NULL,
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parent_hw, -1, flags, mult, div,
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false);
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}
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EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_parent_hw);
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struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
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const char *name, const char *parent_name, unsigned long flags,
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unsigned int mult, unsigned int div)
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{
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return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, -1,
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return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1,
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flags, mult, div, false);
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}
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EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor);
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@ -204,22 +239,16 @@ struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
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const char *name, const char *parent_name, unsigned long flags,
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unsigned int mult, unsigned int div)
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{
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return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, -1,
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return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1,
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flags, mult, div, true);
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}
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EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor);
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#ifdef CONFIG_OF
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static const struct of_device_id set_rate_parent_matches[] = {
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{ .compatible = "allwinner,sun4i-a10-pll3-2x-clk" },
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{ /* Sentinel */ },
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};
|
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|
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static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node)
|
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{
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struct clk_hw *hw;
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const char *clk_name = node->name;
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unsigned long flags = 0;
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u32 div, mult;
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int ret;
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|
|
@ -237,11 +266,8 @@ static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node)
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of_property_read_string(node, "clock-output-names", &clk_name);
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|
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if (of_match_node(set_rate_parent_matches, node))
|
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flags |= CLK_SET_RATE_PARENT;
|
||||
|
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hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, 0,
|
||||
flags, mult, div, false);
|
||||
hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, NULL, 0,
|
||||
0, mult, div, false);
|
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if (IS_ERR(hw)) {
|
||||
/*
|
||||
* Clear OF_POPULATED flag so that clock registration can be
|
||||
|
|
|
|||
|
|
@ -4279,54 +4279,6 @@ int devm_clk_hw_register(struct device *dev, struct clk_hw *hw)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(devm_clk_hw_register);
|
||||
|
||||
static int devm_clk_match(struct device *dev, void *res, void *data)
|
||||
{
|
||||
struct clk *c = res;
|
||||
if (WARN_ON(!c))
|
||||
return 0;
|
||||
return c == data;
|
||||
}
|
||||
|
||||
static int devm_clk_hw_match(struct device *dev, void *res, void *data)
|
||||
{
|
||||
struct clk_hw *hw = res;
|
||||
|
||||
if (WARN_ON(!hw))
|
||||
return 0;
|
||||
return hw == data;
|
||||
}
|
||||
|
||||
/**
|
||||
* devm_clk_unregister - resource managed clk_unregister()
|
||||
* @dev: device that is unregistering the clock data
|
||||
* @clk: clock to unregister
|
||||
*
|
||||
* Deallocate a clock allocated with devm_clk_register(). Normally
|
||||
* this function will not need to be called and the resource management
|
||||
* code will ensure that the resource is freed.
|
||||
*/
|
||||
void devm_clk_unregister(struct device *dev, struct clk *clk)
|
||||
{
|
||||
WARN_ON(devres_release(dev, devm_clk_unregister_cb, devm_clk_match, clk));
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(devm_clk_unregister);
|
||||
|
||||
/**
|
||||
* devm_clk_hw_unregister - resource managed clk_hw_unregister()
|
||||
* @dev: device that is unregistering the hardware-specific clock data
|
||||
* @hw: link to hardware-specific clock data
|
||||
*
|
||||
* Unregister a clk_hw registered with devm_clk_hw_register(). Normally
|
||||
* this function will not need to be called and the resource management
|
||||
* code will ensure that the resource is freed.
|
||||
*/
|
||||
void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw)
|
||||
{
|
||||
WARN_ON(devres_release(dev, devm_clk_hw_unregister_cb, devm_clk_hw_match,
|
||||
hw));
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(devm_clk_hw_unregister);
|
||||
|
||||
static void devm_clk_release(struct device *dev, void *res)
|
||||
{
|
||||
clk_put(*(struct clk **)res);
|
||||
|
|
|
|||
|
|
@ -36,6 +36,14 @@ static const struct mtk_gate eth_clks[] = {
|
|||
GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
|
||||
};
|
||||
|
||||
static u16 rst_ofs[] = { 0x34, };
|
||||
|
||||
static const struct mtk_clk_rst_desc clk_rst_desc = {
|
||||
.version = MTK_RST_SIMPLE,
|
||||
.rst_bank_ofs = rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt2701_eth[] = {
|
||||
{ .compatible = "mediatek,mt2701-ethsys", },
|
||||
{}
|
||||
|
|
@ -58,7 +66,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev)
|
|||
"could not register clock provider: %s: %d\n",
|
||||
pdev->name, r);
|
||||
|
||||
mtk_register_reset_controller(node, 1, 0x34);
|
||||
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -35,6 +35,14 @@ static const struct mtk_gate g3d_clks[] = {
|
|||
GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
|
||||
};
|
||||
|
||||
static u16 rst_ofs[] = { 0xc, };
|
||||
|
||||
static const struct mtk_clk_rst_desc clk_rst_desc = {
|
||||
.version = MTK_RST_SIMPLE,
|
||||
.rst_bank_ofs = rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
|
||||
};
|
||||
|
||||
static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
|
|
@ -52,7 +60,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
|
|||
"could not register clock provider: %s: %d\n",
|
||||
pdev->name, r);
|
||||
|
||||
mtk_register_reset_controller(node, 1, 0xc);
|
||||
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -33,6 +33,14 @@ static const struct mtk_gate hif_clks[] = {
|
|||
GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26),
|
||||
};
|
||||
|
||||
static u16 rst_ofs[] = { 0x34, };
|
||||
|
||||
static const struct mtk_clk_rst_desc clk_rst_desc = {
|
||||
.version = MTK_RST_SIMPLE,
|
||||
.rst_bank_ofs = rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt2701_hif[] = {
|
||||
{ .compatible = "mediatek,mt2701-hifsys", },
|
||||
{}
|
||||
|
|
@ -57,7 +65,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev)
|
|||
return r;
|
||||
}
|
||||
|
||||
mtk_register_reset_controller(node, 1, 0x34);
|
||||
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -735,6 +735,24 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = {
|
|||
FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
|
||||
};
|
||||
|
||||
static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
|
||||
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
|
||||
|
||||
static const struct mtk_clk_rst_desc clk_rst_desc[] = {
|
||||
/* infrasys */
|
||||
{
|
||||
.version = MTK_RST_SIMPLE,
|
||||
.rst_bank_ofs = infrasys_rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
|
||||
},
|
||||
/* pericfg */
|
||||
{
|
||||
.version = MTK_RST_SIMPLE,
|
||||
.rst_bank_ofs = pericfg_rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_hw_onecell_data *infra_clk_data;
|
||||
|
||||
static void __init mtk_infrasys_init_early(struct device_node *node)
|
||||
|
|
@ -787,7 +805,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
|
|||
if (r)
|
||||
return r;
|
||||
|
||||
mtk_register_reset_controller(node, 2, 0x30);
|
||||
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -910,7 +928,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
|
|||
if (r)
|
||||
return r;
|
||||
|
||||
mtk_register_reset_controller(node, 2, 0x0);
|
||||
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1258,6 +1258,24 @@ static const struct mtk_pll_data plls[] = {
|
|||
0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
|
||||
};
|
||||
|
||||
static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
|
||||
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
|
||||
|
||||
static const struct mtk_clk_rst_desc clk_rst_desc[] = {
|
||||
/* infra */
|
||||
{
|
||||
.version = MTK_RST_SIMPLE,
|
||||
.rst_bank_ofs = infrasys_rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
|
||||
},
|
||||
/* peri */
|
||||
{
|
||||
.version = MTK_RST_SIMPLE,
|
||||
.rst_bank_ofs = pericfg_rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
|
||||
},
|
||||
};
|
||||
|
||||
static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
|
|
@ -1361,7 +1379,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev)
|
|||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
mtk_register_reset_controller(node, 2, 0x30);
|
||||
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
|
@ -1383,7 +1401,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev)
|
|||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
mtk_register_reset_controller(node, 2, 0);
|
||||
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -65,6 +65,14 @@ static const struct mtk_gate sgmii_clks[] = {
|
|||
"ssusb_cdr_fb", 5),
|
||||
};
|
||||
|
||||
static u16 rst_ofs[] = { 0x34, };
|
||||
|
||||
static const struct mtk_clk_rst_desc clk_rst_desc = {
|
||||
.version = MTK_RST_SIMPLE,
|
||||
.rst_bank_ofs = rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
|
||||
};
|
||||
|
||||
static int clk_mt7622_ethsys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
|
|
@ -82,7 +90,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev)
|
|||
"could not register clock provider: %s: %d\n",
|
||||
pdev->name, r);
|
||||
|
||||
mtk_register_reset_controller(node, 1, 0x34);
|
||||
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -76,6 +76,14 @@ static const struct mtk_gate pcie_clks[] = {
|
|||
GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30),
|
||||
};
|
||||
|
||||
static u16 rst_ofs[] = { 0x34, };
|
||||
|
||||
static const struct mtk_clk_rst_desc clk_rst_desc = {
|
||||
.version = MTK_RST_SIMPLE,
|
||||
.rst_bank_ofs = rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
|
||||
};
|
||||
|
||||
static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
|
|
@ -93,7 +101,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
|
|||
"could not register clock provider: %s: %d\n",
|
||||
pdev->name, r);
|
||||
|
||||
mtk_register_reset_controller(node, 1, 0x34);
|
||||
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
|
@ -115,7 +123,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev)
|
|||
"could not register clock provider: %s: %d\n",
|
||||
pdev->name, r);
|
||||
|
||||
mtk_register_reset_controller(node, 1, 0x34);
|
||||
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -610,6 +610,24 @@ static struct mtk_composite peri_muxes[] = {
|
|||
MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
|
||||
};
|
||||
|
||||
static u16 infrasys_rst_ofs[] = { 0x30, };
|
||||
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
|
||||
|
||||
static const struct mtk_clk_rst_desc clk_rst_desc[] = {
|
||||
/* infrasys */
|
||||
{
|
||||
.version = MTK_RST_SIMPLE,
|
||||
.rst_bank_ofs = infrasys_rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
|
||||
},
|
||||
/* pericfg */
|
||||
{
|
||||
.version = MTK_RST_SIMPLE,
|
||||
.rst_bank_ofs = pericfg_rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
|
||||
},
|
||||
};
|
||||
|
||||
static int mtk_topckgen_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
|
|
@ -663,7 +681,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
|
|||
if (r)
|
||||
return r;
|
||||
|
||||
mtk_register_reset_controller(node, 1, 0x30);
|
||||
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -714,7 +732,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
|
|||
|
||||
clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk);
|
||||
|
||||
mtk_register_reset_controller(node, 2, 0x0);
|
||||
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -76,6 +76,14 @@ static const struct mtk_gate sgmii_clks[2][4] = {
|
|||
}
|
||||
};
|
||||
|
||||
static u16 rst_ofs[] = { 0x34, };
|
||||
|
||||
static const struct mtk_clk_rst_desc clk_rst_desc = {
|
||||
.version = MTK_RST_SIMPLE,
|
||||
.rst_bank_ofs = rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
|
||||
};
|
||||
|
||||
static int clk_mt7629_ethsys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
|
|
@ -92,7 +100,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev)
|
|||
"could not register clock provider: %s: %d\n",
|
||||
pdev->name, r);
|
||||
|
||||
mtk_register_reset_controller(node, 1, 0x34);
|
||||
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -71,6 +71,14 @@ static const struct mtk_gate pcie_clks[] = {
|
|||
GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
|
||||
};
|
||||
|
||||
static u16 rst_ofs[] = { 0x34, };
|
||||
|
||||
static const struct mtk_clk_rst_desc clk_rst_desc = {
|
||||
.version = MTK_RST_SIMPLE,
|
||||
.rst_bank_ofs = rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
|
||||
};
|
||||
|
||||
static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
|
|
@ -88,7 +96,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
|
|||
"could not register clock provider: %s: %d\n",
|
||||
pdev->name, r);
|
||||
|
||||
mtk_register_reset_controller(node, 1, 0x34);
|
||||
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
|
@ -110,7 +118,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev)
|
|||
"could not register clock provider: %s: %d\n",
|
||||
pdev->name, r);
|
||||
|
||||
mtk_register_reset_controller(node, 1, 0x34);
|
||||
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -514,6 +514,24 @@ static const struct mtk_composite peri_clks[] __initconst = {
|
|||
MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
|
||||
};
|
||||
|
||||
static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
|
||||
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
|
||||
|
||||
static const struct mtk_clk_rst_desc clk_rst_desc[] = {
|
||||
/* infrasys */
|
||||
{
|
||||
.version = MTK_RST_SIMPLE,
|
||||
.rst_bank_ofs = infrasys_rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
|
||||
},
|
||||
/* pericfg */
|
||||
{
|
||||
.version = MTK_RST_SIMPLE,
|
||||
.rst_bank_ofs = pericfg_rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
|
||||
}
|
||||
};
|
||||
|
||||
static void __init mtk_topckgen_init(struct device_node *node)
|
||||
{
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
|
|
@ -559,7 +577,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
|
|||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
mtk_register_reset_controller(node, 2, 0x30);
|
||||
mtk_register_reset_controller(node, &clk_rst_desc[0]);
|
||||
}
|
||||
CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init);
|
||||
|
||||
|
|
@ -587,7 +605,7 @@ static void __init mtk_pericfg_init(struct device_node *node)
|
|||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
mtk_register_reset_controller(node, 2, 0);
|
||||
mtk_register_reset_controller(node, &clk_rst_desc[1]);
|
||||
}
|
||||
CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init);
|
||||
|
||||
|
|
|
|||
|
|
@ -819,6 +819,24 @@ static const struct mtk_gate venclt_clks[] __initconst = {
|
|||
GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4),
|
||||
};
|
||||
|
||||
static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
|
||||
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
|
||||
|
||||
static const struct mtk_clk_rst_desc clk_rst_desc[] = {
|
||||
/* infrasys */
|
||||
{
|
||||
.version = MTK_RST_SIMPLE,
|
||||
.rst_bank_ofs = infrasys_rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
|
||||
},
|
||||
/* pericfg */
|
||||
{
|
||||
.version = MTK_RST_SIMPLE,
|
||||
.rst_bank_ofs = pericfg_rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
|
||||
}
|
||||
};
|
||||
|
||||
static struct clk_hw_onecell_data *mt8173_top_clk_data __initdata;
|
||||
static struct clk_hw_onecell_data *mt8173_pll_clk_data __initdata;
|
||||
|
||||
|
|
@ -882,7 +900,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
|
|||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
mtk_register_reset_controller(node, 2, 0x30);
|
||||
mtk_register_reset_controller(node, &clk_rst_desc[0]);
|
||||
}
|
||||
CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init);
|
||||
|
||||
|
|
@ -910,7 +928,7 @@ static void __init mtk_pericfg_init(struct device_node *node)
|
|||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
mtk_register_reset_controller(node, 2, 0);
|
||||
mtk_register_reset_controller(node, &clk_rst_desc[1]);
|
||||
}
|
||||
CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
|
||||
|
||||
|
|
|
|||
|
|
@ -18,9 +18,6 @@
|
|||
|
||||
#include <dt-bindings/clock/mt8183-clk.h>
|
||||
|
||||
/* Infra global controller reset set register */
|
||||
#define INFRA_RST0_SET_OFFSET 0x120
|
||||
|
||||
static DEFINE_SPINLOCK(mt8183_clk_lock);
|
||||
|
||||
static const struct mtk_fixed_clk top_fixed_clks[] = {
|
||||
|
|
@ -1153,6 +1150,19 @@ static const struct mtk_pll_data plls[] = {
|
|||
0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
|
||||
};
|
||||
|
||||
static u16 infra_rst_ofs[] = {
|
||||
INFRA_RST0_SET_OFFSET,
|
||||
INFRA_RST1_SET_OFFSET,
|
||||
INFRA_RST2_SET_OFFSET,
|
||||
INFRA_RST3_SET_OFFSET,
|
||||
};
|
||||
|
||||
static const struct mtk_clk_rst_desc clk_rst_desc = {
|
||||
.version = MTK_RST_SET_CLR,
|
||||
.rst_bank_ofs = infra_rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(infra_rst_ofs),
|
||||
};
|
||||
|
||||
static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
|
|
@ -1240,7 +1250,7 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
|
|||
return r;
|
||||
}
|
||||
|
||||
mtk_register_reset_controller_set_clr(node, 4, INFRA_RST0_SET_OFFSET);
|
||||
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <dt-bindings/clock/mt8186-clk.h>
|
||||
#include <dt-bindings/reset/mt8186-resets.h>
|
||||
|
||||
#include "clk-gate.h"
|
||||
#include "clk-mtk.h"
|
||||
|
|
@ -191,9 +192,31 @@ static const struct mtk_gate infra_ao_clks[] = {
|
|||
GATE_INFRA_AO3(CLK_INFRA_AO_FLASHIF_66M, "infra_ao_flashif_66m", "top_axi", 29),
|
||||
};
|
||||
|
||||
static u16 infra_ao_rst_ofs[] = {
|
||||
INFRA_RST0_SET_OFFSET,
|
||||
INFRA_RST1_SET_OFFSET,
|
||||
INFRA_RST2_SET_OFFSET,
|
||||
INFRA_RST3_SET_OFFSET,
|
||||
INFRA_RST4_SET_OFFSET,
|
||||
};
|
||||
|
||||
static u16 infra_ao_idx_map[] = {
|
||||
[MT8186_INFRA_THERMAL_CTRL_RST] = 0 * RST_NR_PER_BANK + 0,
|
||||
[MT8186_INFRA_PTP_CTRL_RST] = 1 * RST_NR_PER_BANK + 0,
|
||||
};
|
||||
|
||||
static struct mtk_clk_rst_desc infra_ao_rst_desc = {
|
||||
.version = MTK_RST_SET_CLR,
|
||||
.rst_bank_ofs = infra_ao_rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
|
||||
.rst_idx_map = infra_ao_idx_map,
|
||||
.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc infra_ao_desc = {
|
||||
.clks = infra_ao_clks,
|
||||
.num_clks = ARRAY_SIZE(infra_ao_clks),
|
||||
.rst_desc = &infra_ao_rst_desc,
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8186_infra_ao[] = {
|
||||
|
|
|
|||
|
|
@ -12,28 +12,15 @@
|
|||
|
||||
#include <dt-bindings/clock/mt8192-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs msdc_cg_regs = {
|
||||
.set_ofs = 0xb4,
|
||||
.clr_ofs = 0xb4,
|
||||
.sta_ofs = 0xb4,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs msdc_top_cg_regs = {
|
||||
.set_ofs = 0x0,
|
||||
.clr_ofs = 0x0,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
#define GATE_MSDC(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &msdc_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
|
||||
|
||||
#define GATE_MSDC_TOP(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &msdc_top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
|
||||
|
||||
static const struct mtk_gate msdc_clks[] = {
|
||||
GATE_MSDC(CLK_MSDC_AXI_WRAP, "msdc_axi_wrap", "axi_sel", 22),
|
||||
};
|
||||
|
||||
static const struct mtk_gate msdc_top_clks[] = {
|
||||
GATE_MSDC_TOP(CLK_MSDC_TOP_AES_0P, "msdc_top_aes_0p", "aes_msdcfde_sel", 0),
|
||||
GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_0P, "msdc_top_src_0p", "infra_msdc0_src", 1),
|
||||
|
|
@ -52,11 +39,6 @@ static const struct mtk_gate msdc_top_clks[] = {
|
|||
GATE_MSDC_TOP(CLK_MSDC_TOP_AHB2AXI_BRG_AXI, "msdc_top_ahb2axi_brg_axi", "axi_sel", 14),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc msdc_desc = {
|
||||
.clks = msdc_clks,
|
||||
.num_clks = ARRAY_SIZE(msdc_clks),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc msdc_top_desc = {
|
||||
.clks = msdc_top_clks,
|
||||
.num_clks = ARRAY_SIZE(msdc_top_clks),
|
||||
|
|
@ -64,9 +46,6 @@ static const struct mtk_clk_desc msdc_top_desc = {
|
|||
|
||||
static const struct of_device_id of_match_clk_mt8192_msdc[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt8192-msdc",
|
||||
.data = &msdc_desc,
|
||||
}, {
|
||||
.compatible = "mediatek,mt8192-msdc_top",
|
||||
.data = &msdc_top_desc,
|
||||
}, {
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
#include "clk-pll.h"
|
||||
|
||||
#include <dt-bindings/clock/mt8192-clk.h>
|
||||
#include <dt-bindings/reset/mt8192-resets.h>
|
||||
|
||||
static DEFINE_SPINLOCK(mt8192_clk_lock);
|
||||
|
||||
|
|
@ -1114,6 +1115,30 @@ static const struct mtk_gate top_clks[] = {
|
|||
GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25),
|
||||
};
|
||||
|
||||
static u16 infra_ao_rst_ofs[] = {
|
||||
INFRA_RST0_SET_OFFSET,
|
||||
INFRA_RST1_SET_OFFSET,
|
||||
INFRA_RST2_SET_OFFSET,
|
||||
INFRA_RST3_SET_OFFSET,
|
||||
INFRA_RST4_SET_OFFSET,
|
||||
};
|
||||
|
||||
static u16 infra_ao_idx_map[] = {
|
||||
[MT8192_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,
|
||||
[MT8192_INFRA_RST2_PEXTP_PHY_SWRST] = 2 * RST_NR_PER_BANK + 15,
|
||||
[MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,
|
||||
[MT8192_INFRA_RST4_PCIE_TOP_SWRST] = 4 * RST_NR_PER_BANK + 1,
|
||||
[MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 12,
|
||||
};
|
||||
|
||||
static const struct mtk_clk_rst_desc clk_rst_desc = {
|
||||
.version = MTK_RST_SET_CLR,
|
||||
.rst_bank_ofs = infra_ao_rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
|
||||
.rst_idx_map = infra_ao_idx_map,
|
||||
.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
|
||||
};
|
||||
|
||||
#define MT8192_PLL_FMAX (3800UL * MHZ)
|
||||
#define MT8192_PLL_FMIN (1500UL * MHZ)
|
||||
#define MT8192_INTEGER_BITS 8
|
||||
|
|
@ -1240,6 +1265,10 @@ static int clk_mt8192_infra_probe(struct platform_device *pdev)
|
|||
if (r)
|
||||
goto free_clk_data;
|
||||
|
||||
r = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
|
||||
if (r)
|
||||
goto free_clk_data;
|
||||
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
goto free_clk_data;
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
#include "clk-mtk.h"
|
||||
|
||||
#include <dt-bindings/clock/mt8195-clk.h>
|
||||
#include <dt-bindings/reset/mt8195-resets.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
|
|
@ -182,9 +183,32 @@ static const struct mtk_gate infra_ao_clks[] = {
|
|||
GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, "infra_ao_peri_ufs_mem_sub", "mem_466m", 31),
|
||||
};
|
||||
|
||||
static u16 infra_ao_rst_ofs[] = {
|
||||
INFRA_RST0_SET_OFFSET,
|
||||
INFRA_RST1_SET_OFFSET,
|
||||
INFRA_RST2_SET_OFFSET,
|
||||
INFRA_RST3_SET_OFFSET,
|
||||
INFRA_RST4_SET_OFFSET,
|
||||
};
|
||||
|
||||
static u16 infra_ao_idx_map[] = {
|
||||
[MT8195_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,
|
||||
[MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,
|
||||
[MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 10,
|
||||
};
|
||||
|
||||
static struct mtk_clk_rst_desc infra_ao_rst_desc = {
|
||||
.version = MTK_RST_SET_CLR,
|
||||
.rst_bank_ofs = infra_ao_rst_ofs,
|
||||
.rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
|
||||
.rst_idx_map = infra_ao_idx_map,
|
||||
.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc infra_ao_desc = {
|
||||
.clks = infra_ao_clks,
|
||||
.num_clks = ARRAY_SIZE(infra_ao_clks),
|
||||
.rst_desc = &infra_ao_rst_desc,
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8195_infra_ao[] = {
|
||||
|
|
|
|||
|
|
@ -444,6 +444,13 @@ int mtk_clk_simple_probe(struct platform_device *pdev)
|
|||
|
||||
platform_set_drvdata(pdev, clk_data);
|
||||
|
||||
if (mcd->rst_desc) {
|
||||
r = mtk_register_reset_controller_with_dev(&pdev->dev,
|
||||
mcd->rst_desc);
|
||||
if (r)
|
||||
goto unregister_clks;
|
||||
}
|
||||
|
||||
return r;
|
||||
|
||||
unregister_clks:
|
||||
|
|
|
|||
|
|
@ -13,6 +13,8 @@
|
|||
#include <linux/spinlock.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include "reset.h"
|
||||
|
||||
#define MAX_MUX_GATE_BIT 31
|
||||
#define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1)
|
||||
|
||||
|
|
@ -187,15 +189,10 @@ void mtk_free_clk_data(struct clk_hw_onecell_data *clk_data);
|
|||
struct clk_hw *mtk_clk_register_ref2usb_tx(const char *name,
|
||||
const char *parent_name, void __iomem *reg);
|
||||
|
||||
void mtk_register_reset_controller(struct device_node *np,
|
||||
unsigned int num_regs, int regofs);
|
||||
|
||||
void mtk_register_reset_controller_set_clr(struct device_node *np,
|
||||
unsigned int num_regs, int regofs);
|
||||
|
||||
struct mtk_clk_desc {
|
||||
const struct mtk_gate *clks;
|
||||
size_t num_clks;
|
||||
const struct mtk_clk_rst_desc *rst_desc;
|
||||
};
|
||||
|
||||
int mtk_clk_simple_probe(struct platform_device *pdev);
|
||||
|
|
|
|||
|
|
@ -8,55 +8,39 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "reset.h"
|
||||
|
||||
struct mtk_reset {
|
||||
struct regmap *regmap;
|
||||
int regofs;
|
||||
struct reset_controller_dev rcdev;
|
||||
};
|
||||
|
||||
static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
static inline struct mtk_clk_rst_data *to_mtk_clk_rst_data(struct reset_controller_dev *rcdev)
|
||||
{
|
||||
struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
|
||||
unsigned int reg = data->regofs + ((id / 32) << 4);
|
||||
|
||||
return regmap_write(data->regmap, reg, 1);
|
||||
return container_of(rcdev, struct mtk_clk_rst_data, rcdev);
|
||||
}
|
||||
|
||||
static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
static int mtk_reset_update(struct reset_controller_dev *rcdev,
|
||||
unsigned long id, bool deassert)
|
||||
{
|
||||
struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
|
||||
unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4;
|
||||
struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
|
||||
unsigned int val = deassert ? 0 : ~0;
|
||||
|
||||
return regmap_write(data->regmap, reg, 1);
|
||||
return regmap_update_bits(data->regmap,
|
||||
data->desc->rst_bank_ofs[id / RST_NR_PER_BANK],
|
||||
BIT(id % RST_NR_PER_BANK), val);
|
||||
}
|
||||
|
||||
static int mtk_reset_assert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
unsigned long id)
|
||||
{
|
||||
struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
|
||||
|
||||
return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2),
|
||||
BIT(id % 32), ~0);
|
||||
return mtk_reset_update(rcdev, id, false);
|
||||
}
|
||||
|
||||
static int mtk_reset_deassert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
unsigned long id)
|
||||
{
|
||||
struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
|
||||
|
||||
return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2),
|
||||
BIT(id % 32), 0);
|
||||
return mtk_reset_update(rcdev, id, true);
|
||||
}
|
||||
|
||||
static int mtk_reset(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
static int mtk_reset(struct reset_controller_dev *rcdev, unsigned long id)
|
||||
{
|
||||
int ret;
|
||||
|
||||
|
|
@ -67,8 +51,32 @@ static int mtk_reset(struct reset_controller_dev *rcdev,
|
|||
return mtk_reset_deassert(rcdev, id);
|
||||
}
|
||||
|
||||
static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev,
|
||||
unsigned long id, bool deassert)
|
||||
{
|
||||
struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
|
||||
unsigned int deassert_ofs = deassert ? 0x4 : 0;
|
||||
|
||||
return regmap_write(data->regmap,
|
||||
data->desc->rst_bank_ofs[id / RST_NR_PER_BANK] +
|
||||
deassert_ofs,
|
||||
BIT(id % RST_NR_PER_BANK));
|
||||
}
|
||||
|
||||
static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
return mtk_reset_update_set_clr(rcdev, id, false);
|
||||
}
|
||||
|
||||
static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
return mtk_reset_update_set_clr(rcdev, id, true);
|
||||
}
|
||||
|
||||
static int mtk_reset_set_clr(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
unsigned long id)
|
||||
{
|
||||
int ret;
|
||||
|
||||
|
|
@ -90,51 +98,135 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = {
|
|||
.reset = mtk_reset_set_clr,
|
||||
};
|
||||
|
||||
static void mtk_register_reset_controller_common(struct device_node *np,
|
||||
unsigned int num_regs, int regofs,
|
||||
const struct reset_control_ops *reset_ops)
|
||||
static int reset_xlate(struct reset_controller_dev *rcdev,
|
||||
const struct of_phandle_args *reset_spec)
|
||||
{
|
||||
struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
|
||||
|
||||
if (reset_spec->args[0] >= rcdev->nr_resets ||
|
||||
reset_spec->args[0] >= data->desc->rst_idx_map_nr)
|
||||
return -EINVAL;
|
||||
|
||||
return data->desc->rst_idx_map[reset_spec->args[0]];
|
||||
}
|
||||
|
||||
int mtk_register_reset_controller(struct device_node *np,
|
||||
const struct mtk_clk_rst_desc *desc)
|
||||
{
|
||||
struct mtk_reset *data;
|
||||
int ret;
|
||||
struct regmap *regmap;
|
||||
const struct reset_control_ops *rcops = NULL;
|
||||
struct mtk_clk_rst_data *data;
|
||||
int ret;
|
||||
|
||||
if (!desc) {
|
||||
pr_err("mtk clock reset desc is NULL\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (desc->version) {
|
||||
case MTK_RST_SIMPLE:
|
||||
rcops = &mtk_reset_ops;
|
||||
break;
|
||||
case MTK_RST_SET_CLR:
|
||||
rcops = &mtk_reset_ops_set_clr;
|
||||
break;
|
||||
default:
|
||||
pr_err("Unknown reset version %d\n", desc->version);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
regmap = device_node_to_regmap(np);
|
||||
if (IS_ERR(regmap)) {
|
||||
pr_err("Cannot find regmap for %pOF: %pe\n", np, regmap);
|
||||
return;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
data = kzalloc(sizeof(*data), GFP_KERNEL);
|
||||
if (!data)
|
||||
return;
|
||||
return -ENOMEM;
|
||||
|
||||
data->desc = desc;
|
||||
data->regmap = regmap;
|
||||
data->regofs = regofs;
|
||||
data->rcdev.owner = THIS_MODULE;
|
||||
data->rcdev.nr_resets = num_regs * 32;
|
||||
data->rcdev.ops = reset_ops;
|
||||
data->rcdev.ops = rcops;
|
||||
data->rcdev.of_node = np;
|
||||
|
||||
if (data->desc->rst_idx_map_nr > 0) {
|
||||
data->rcdev.of_reset_n_cells = 1;
|
||||
data->rcdev.nr_resets = desc->rst_idx_map_nr;
|
||||
data->rcdev.of_xlate = reset_xlate;
|
||||
} else {
|
||||
data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK;
|
||||
}
|
||||
|
||||
ret = reset_controller_register(&data->rcdev);
|
||||
if (ret) {
|
||||
pr_err("could not register reset controller: %d\n", ret);
|
||||
kfree(data);
|
||||
return;
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void mtk_register_reset_controller(struct device_node *np,
|
||||
unsigned int num_regs, int regofs)
|
||||
int mtk_register_reset_controller_with_dev(struct device *dev,
|
||||
const struct mtk_clk_rst_desc *desc)
|
||||
{
|
||||
mtk_register_reset_controller_common(np, num_regs, regofs,
|
||||
&mtk_reset_ops);
|
||||
}
|
||||
struct device_node *np = dev->of_node;
|
||||
struct regmap *regmap;
|
||||
const struct reset_control_ops *rcops = NULL;
|
||||
struct mtk_clk_rst_data *data;
|
||||
int ret;
|
||||
|
||||
void mtk_register_reset_controller_set_clr(struct device_node *np,
|
||||
unsigned int num_regs, int regofs)
|
||||
{
|
||||
mtk_register_reset_controller_common(np, num_regs, regofs,
|
||||
&mtk_reset_ops_set_clr);
|
||||
if (!desc) {
|
||||
dev_err(dev, "mtk clock reset desc is NULL\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (desc->version) {
|
||||
case MTK_RST_SIMPLE:
|
||||
rcops = &mtk_reset_ops;
|
||||
break;
|
||||
case MTK_RST_SET_CLR:
|
||||
rcops = &mtk_reset_ops_set_clr;
|
||||
break;
|
||||
default:
|
||||
dev_err(dev, "Unknown reset version %d\n", desc->version);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
regmap = device_node_to_regmap(np);
|
||||
if (IS_ERR(regmap)) {
|
||||
dev_err(dev, "Cannot find regmap %pe\n", regmap);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
data->desc = desc;
|
||||
data->regmap = regmap;
|
||||
data->rcdev.owner = THIS_MODULE;
|
||||
data->rcdev.ops = rcops;
|
||||
data->rcdev.of_node = np;
|
||||
data->rcdev.dev = dev;
|
||||
|
||||
if (data->desc->rst_idx_map_nr > 0) {
|
||||
data->rcdev.of_reset_n_cells = 1;
|
||||
data->rcdev.nr_resets = desc->rst_idx_map_nr;
|
||||
data->rcdev.of_xlate = reset_xlate;
|
||||
} else {
|
||||
data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK;
|
||||
}
|
||||
|
||||
ret = devm_reset_controller_register(dev, &data->rcdev);
|
||||
if (ret) {
|
||||
dev_err(dev, "could not register reset controller: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
|
|||
82
drivers/clk/mediatek/reset.h
Normal file
82
drivers/clk/mediatek/reset.h
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2022 MediaTek Inc.
|
||||
*/
|
||||
|
||||
#ifndef __DRV_CLK_MTK_RESET_H
|
||||
#define __DRV_CLK_MTK_RESET_H
|
||||
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#define RST_NR_PER_BANK 32
|
||||
|
||||
/* Infra global controller reset set register */
|
||||
#define INFRA_RST0_SET_OFFSET 0x120
|
||||
#define INFRA_RST1_SET_OFFSET 0x130
|
||||
#define INFRA_RST2_SET_OFFSET 0x140
|
||||
#define INFRA_RST3_SET_OFFSET 0x150
|
||||
#define INFRA_RST4_SET_OFFSET 0x730
|
||||
|
||||
/**
|
||||
* enum mtk_reset_version - Version of MediaTek clock reset controller.
|
||||
* @MTK_RST_SIMPLE: Use the same registers for bit set and clear.
|
||||
* @MTK_RST_SET_CLR: Use separate registers for bit set and clear.
|
||||
* @MTK_RST_MAX: Total quantity of version for MediaTek clock reset controller.
|
||||
*/
|
||||
enum mtk_reset_version {
|
||||
MTK_RST_SIMPLE = 0,
|
||||
MTK_RST_SET_CLR,
|
||||
MTK_RST_MAX,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct mtk_clk_rst_desc - Description of MediaTek clock reset.
|
||||
* @version: Reset version which is defined in enum mtk_reset_version.
|
||||
* @rst_bank_ofs: Pointer to an array containing base offsets of the reset register.
|
||||
* @rst_bank_nr: Quantity of reset bank.
|
||||
* @rst_idx_map:Pointer to an array containing ids if input argument is index.
|
||||
* This array is not necessary if our input argument does not mean index.
|
||||
* @rst_idx_map_nr: Quantity of reset index map.
|
||||
*/
|
||||
struct mtk_clk_rst_desc {
|
||||
enum mtk_reset_version version;
|
||||
u16 *rst_bank_ofs;
|
||||
u32 rst_bank_nr;
|
||||
u16 *rst_idx_map;
|
||||
u32 rst_idx_map_nr;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct mtk_clk_rst_data - Data of MediaTek clock reset controller.
|
||||
* @regmap: Pointer to base address of reset register address.
|
||||
* @rcdev: Reset controller device.
|
||||
* @desc: Pointer to description of the reset controller.
|
||||
*/
|
||||
struct mtk_clk_rst_data {
|
||||
struct regmap *regmap;
|
||||
struct reset_controller_dev rcdev;
|
||||
const struct mtk_clk_rst_desc *desc;
|
||||
};
|
||||
|
||||
/**
|
||||
* mtk_register_reset_controller - Register MediaTek clock reset controller
|
||||
* @np: Pointer to device node.
|
||||
* @desc: Constant pointer to description of clock reset.
|
||||
*
|
||||
* Return: 0 on success and errorno otherwise.
|
||||
*/
|
||||
int mtk_register_reset_controller(struct device_node *np,
|
||||
const struct mtk_clk_rst_desc *desc);
|
||||
|
||||
/**
|
||||
* mtk_register_reset_controller - Register mediatek clock reset controller with device
|
||||
* @np: Pointer to device.
|
||||
* @desc: Constant pointer to description of clock reset.
|
||||
*
|
||||
* Return: 0 on success and errorno otherwise.
|
||||
*/
|
||||
int mtk_register_reset_controller_with_dev(struct device *dev,
|
||||
const struct mtk_clk_rst_desc *desc);
|
||||
|
||||
#endif /* __DRV_CLK_MTK_RESET_H */
|
||||
|
|
@ -1657,35 +1657,6 @@ static struct clk_regmap *const sm1_clk_regmaps[] = {
|
|||
&sm1_sysclk_b_en,
|
||||
};
|
||||
|
||||
static int devm_clk_get_enable(struct device *dev, char *id)
|
||||
{
|
||||
struct clk *clk;
|
||||
int ret;
|
||||
|
||||
clk = devm_clk_get(dev, id);
|
||||
if (IS_ERR(clk)) {
|
||||
ret = PTR_ERR(clk);
|
||||
dev_err_probe(dev, ret, "failed to get %s", id);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to enable %s", id);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devm_add_action_or_reset(dev,
|
||||
(void(*)(void *))clk_disable_unprepare,
|
||||
clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to add reset action on %s", id);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct axg_audio_reset_data {
|
||||
struct reset_controller_dev rstc;
|
||||
struct regmap *map;
|
||||
|
|
@ -1787,6 +1758,7 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
|
|||
struct regmap *map;
|
||||
void __iomem *regs;
|
||||
struct clk_hw *hw;
|
||||
struct clk *clk;
|
||||
int ret, i;
|
||||
|
||||
data = of_device_get_match_data(dev);
|
||||
|
|
@ -1804,9 +1776,9 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
/* Get the mandatory peripheral clock */
|
||||
ret = devm_clk_get_enable(dev, "pclk");
|
||||
if (ret)
|
||||
return ret;
|
||||
clk = devm_clk_get_enabled(dev, "pclk");
|
||||
if (IS_ERR(clk))
|
||||
return PTR_ERR(clk);
|
||||
|
||||
ret = device_reset(dev);
|
||||
if (ret) {
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ static const struct omap_clkctrl_bit_data omap4_aess_bit_data[] __initconst = {
|
|||
};
|
||||
|
||||
static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = {
|
||||
"abe_cm:clk:0018:26",
|
||||
"abe-clkctrl:0018:26",
|
||||
"pad_clks_ck",
|
||||
"slimbus_clk",
|
||||
NULL,
|
||||
|
|
@ -76,7 +76,7 @@ static const struct omap_clkctrl_bit_data omap4_dmic_bit_data[] __initconst = {
|
|||
};
|
||||
|
||||
static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = {
|
||||
"abe_cm:clk:0020:26",
|
||||
"abe-clkctrl:0020:26",
|
||||
"pad_clks_ck",
|
||||
"slimbus_clk",
|
||||
NULL,
|
||||
|
|
@ -89,7 +89,7 @@ static const struct omap_clkctrl_bit_data omap4_mcasp_bit_data[] __initconst = {
|
|||
};
|
||||
|
||||
static const char * const omap4_func_mcbsp1_gfclk_parents[] __initconst = {
|
||||
"abe_cm:clk:0028:26",
|
||||
"abe-clkctrl:0028:26",
|
||||
"pad_clks_ck",
|
||||
"slimbus_clk",
|
||||
NULL,
|
||||
|
|
@ -102,7 +102,7 @@ static const struct omap_clkctrl_bit_data omap4_mcbsp1_bit_data[] __initconst =
|
|||
};
|
||||
|
||||
static const char * const omap4_func_mcbsp2_gfclk_parents[] __initconst = {
|
||||
"abe_cm:clk:0030:26",
|
||||
"abe-clkctrl:0030:26",
|
||||
"pad_clks_ck",
|
||||
"slimbus_clk",
|
||||
NULL,
|
||||
|
|
@ -115,7 +115,7 @@ static const struct omap_clkctrl_bit_data omap4_mcbsp2_bit_data[] __initconst =
|
|||
};
|
||||
|
||||
static const char * const omap4_func_mcbsp3_gfclk_parents[] __initconst = {
|
||||
"abe_cm:clk:0038:26",
|
||||
"abe-clkctrl:0038:26",
|
||||
"pad_clks_ck",
|
||||
"slimbus_clk",
|
||||
NULL,
|
||||
|
|
@ -183,18 +183,18 @@ static const struct omap_clkctrl_bit_data omap4_timer8_bit_data[] __initconst =
|
|||
|
||||
static const struct omap_clkctrl_reg_data omap4_abe_clkctrl_regs[] __initconst = {
|
||||
{ OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" },
|
||||
{ OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" },
|
||||
{ OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
|
||||
{ OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
|
||||
{ OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
|
||||
{ OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe_cm:clk:0020:24" },
|
||||
{ OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
|
||||
{ OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
|
||||
{ OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
|
||||
{ OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0040:8" },
|
||||
{ OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
|
||||
{ OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
|
||||
{ OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
|
||||
{ OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
|
||||
{ OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
|
||||
{ OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe-clkctrl:0020:24" },
|
||||
{ OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
|
||||
{ OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
|
||||
{ OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" },
|
||||
{ OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0040:8" },
|
||||
{ OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" },
|
||||
{ OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" },
|
||||
{ OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" },
|
||||
{ OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" },
|
||||
{ OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
|
||||
{ 0 },
|
||||
};
|
||||
|
|
@ -287,7 +287,7 @@ static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = {
|
|||
|
||||
static const struct omap_clkctrl_reg_data omap4_iss_clkctrl_regs[] __initconst = {
|
||||
{ OMAP4_ISS_CLKCTRL, omap4_iss_bit_data, CLKF_SW_SUP, "ducati_clk_mux_ck" },
|
||||
{ OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss_cm:clk:0008:24" },
|
||||
{ OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss-clkctrl:0008:24" },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
|
|
@ -320,7 +320,7 @@ static const struct omap_clkctrl_bit_data omap4_dss_core_bit_data[] __initconst
|
|||
};
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap4_l3_dss_clkctrl_regs[] __initconst = {
|
||||
{ OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3_dss_cm:clk:0000:8" },
|
||||
{ OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3-dss-clkctrl:0000:8" },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
|
|
@ -336,7 +336,7 @@ static const struct omap_clkctrl_bit_data omap4_gpu_bit_data[] __initconst = {
|
|||
};
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap4_l3_gfx_clkctrl_regs[] __initconst = {
|
||||
{ OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3_gfx_cm:clk:0000:24" },
|
||||
{ OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3-gfx-clkctrl:0000:24" },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
|
|
@ -372,12 +372,12 @@ static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = {
|
|||
};
|
||||
|
||||
static const char * const omap4_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
|
||||
"l3_init_cm:clk:0038:24",
|
||||
"l3-init-clkctrl:0038:24",
|
||||
NULL,
|
||||
};
|
||||
|
||||
static const char * const omap4_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
|
||||
"l3_init_cm:clk:0038:25",
|
||||
"l3-init-clkctrl:0038:25",
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
|
@ -418,7 +418,7 @@ static const struct omap_clkctrl_bit_data omap4_usb_host_hs_bit_data[] __initcon
|
|||
};
|
||||
|
||||
static const char * const omap4_usb_otg_hs_xclk_parents[] __initconst = {
|
||||
"l3_init_cm:clk:0040:24",
|
||||
"l3-init-clkctrl:0040:24",
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
|
@ -452,14 +452,14 @@ static const struct omap_clkctrl_bit_data omap4_ocp2scp_usb_phy_bit_data[] __ini
|
|||
};
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap4_l3_init_clkctrl_regs[] __initconst = {
|
||||
{ OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0008:24" },
|
||||
{ OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0010:24" },
|
||||
{ OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:0018:24" },
|
||||
{ OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0008:24" },
|
||||
{ OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0010:24" },
|
||||
{ OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:0018:24" },
|
||||
{ OMAP4_USB_HOST_HS_CLKCTRL, omap4_usb_host_hs_bit_data, CLKF_SW_SUP, "init_60m_fclk" },
|
||||
{ OMAP4_USB_OTG_HS_CLKCTRL, omap4_usb_otg_hs_bit_data, CLKF_HW_SUP, "l3_div_ck" },
|
||||
{ OMAP4_USB_TLL_HS_CLKCTRL, omap4_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_div_ck" },
|
||||
{ OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" },
|
||||
{ OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:00c0:8" },
|
||||
{ OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:00c0:8" },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
|
|
@ -530,7 +530,7 @@ static const struct omap_clkctrl_bit_data omap4_gpio6_bit_data[] __initconst = {
|
|||
};
|
||||
|
||||
static const char * const omap4_per_mcbsp4_gfclk_parents[] __initconst = {
|
||||
"l4_per_cm:clk:00c0:26",
|
||||
"l4-per-clkctrl:00c0:26",
|
||||
"pad_clks_ck",
|
||||
NULL,
|
||||
};
|
||||
|
|
@ -570,12 +570,12 @@ static const struct omap_clkctrl_bit_data omap4_slimbus2_bit_data[] __initconst
|
|||
};
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initconst = {
|
||||
{ OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0008:24" },
|
||||
{ OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0010:24" },
|
||||
{ OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0018:24" },
|
||||
{ OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0020:24" },
|
||||
{ OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0028:24" },
|
||||
{ OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0030:24" },
|
||||
{ OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0008:24" },
|
||||
{ OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0010:24" },
|
||||
{ OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0018:24" },
|
||||
{ OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0020:24" },
|
||||
{ OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0028:24" },
|
||||
{ OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0030:24" },
|
||||
{ OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" },
|
||||
{ OMAP4_GPIO2_CLKCTRL, omap4_gpio2_bit_data, CLKF_HW_SUP, "l4_div_ck" },
|
||||
{ OMAP4_GPIO3_CLKCTRL, omap4_gpio3_bit_data, CLKF_HW_SUP, "l4_div_ck" },
|
||||
|
|
@ -588,14 +588,14 @@ static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initcons
|
|||
{ OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
|
||||
{ OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
|
||||
{ OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" },
|
||||
{ OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:00c0:24" },
|
||||
{ OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:00c0:24" },
|
||||
{ OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
|
||||
{ OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
|
||||
{ OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
|
||||
{ OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
|
||||
{ OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
|
||||
{ OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
|
||||
{ OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0118:8" },
|
||||
{ OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0118:8" },
|
||||
{ OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
|
||||
{ OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
|
||||
{ OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
|
||||
|
|
@ -630,7 +630,7 @@ static const struct omap_clkctrl_reg_data omap4_l4_wkup_clkctrl_regs[] __initcon
|
|||
{ OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" },
|
||||
{ OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
|
||||
{ OMAP4_GPIO1_CLKCTRL, omap4_gpio1_bit_data, CLKF_HW_SUP, "l4_wkup_clk_mux_ck" },
|
||||
{ OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0020:24" },
|
||||
{ OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4-wkup-clkctrl:0020:24" },
|
||||
{ OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" },
|
||||
{ OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
|
||||
{ 0 },
|
||||
|
|
@ -644,7 +644,7 @@ static const char * const omap4_pmd_stm_clock_mux_ck_parents[] __initconst = {
|
|||
};
|
||||
|
||||
static const char * const omap4_trace_clk_div_div_ck_parents[] __initconst = {
|
||||
"emu_sys_cm:clk:0000:22",
|
||||
"emu-sys-clkctrl:0000:22",
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
|
@ -662,7 +662,7 @@ static const struct omap_clkctrl_div_data omap4_trace_clk_div_div_ck_data __init
|
|||
};
|
||||
|
||||
static const char * const omap4_stm_clk_div_ck_parents[] __initconst = {
|
||||
"emu_sys_cm:clk:0000:20",
|
||||
"emu-sys-clkctrl:0000:20",
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
|
@ -716,73 +716,73 @@ static struct ti_dt_clk omap44xx_clks[] = {
|
|||
* hwmod support. Once hwmod is removed, these can be removed
|
||||
* also.
|
||||
*/
|
||||
DT_CLK(NULL, "aess_fclk", "abe_cm:0008:24"),
|
||||
DT_CLK(NULL, "cm2_dm10_mux", "l4_per_cm:0008:24"),
|
||||
DT_CLK(NULL, "cm2_dm11_mux", "l4_per_cm:0010:24"),
|
||||
DT_CLK(NULL, "cm2_dm2_mux", "l4_per_cm:0018:24"),
|
||||
DT_CLK(NULL, "cm2_dm3_mux", "l4_per_cm:0020:24"),
|
||||
DT_CLK(NULL, "cm2_dm4_mux", "l4_per_cm:0028:24"),
|
||||
DT_CLK(NULL, "cm2_dm9_mux", "l4_per_cm:0030:24"),
|
||||
DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
|
||||
DT_CLK(NULL, "dmt1_clk_mux", "l4_wkup_cm:0020:24"),
|
||||
DT_CLK(NULL, "dss_48mhz_clk", "l3_dss_cm:0000:9"),
|
||||
DT_CLK(NULL, "dss_dss_clk", "l3_dss_cm:0000:8"),
|
||||
DT_CLK(NULL, "dss_sys_clk", "l3_dss_cm:0000:10"),
|
||||
DT_CLK(NULL, "dss_tv_clk", "l3_dss_cm:0000:11"),
|
||||
DT_CLK(NULL, "fdif_fck", "iss_cm:0008:24"),
|
||||
DT_CLK(NULL, "func_dmic_abe_gfclk", "abe_cm:0018:24"),
|
||||
DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe_cm:0020:24"),
|
||||
DT_CLK(NULL, "func_mcbsp1_gfclk", "abe_cm:0028:24"),
|
||||
DT_CLK(NULL, "func_mcbsp2_gfclk", "abe_cm:0030:24"),
|
||||
DT_CLK(NULL, "func_mcbsp3_gfclk", "abe_cm:0038:24"),
|
||||
DT_CLK(NULL, "gpio1_dbclk", "l4_wkup_cm:0018:8"),
|
||||
DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0040:8"),
|
||||
DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0048:8"),
|
||||
DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0050:8"),
|
||||
DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0058:8"),
|
||||
DT_CLK(NULL, "gpio6_dbclk", "l4_per_cm:0060:8"),
|
||||
DT_CLK(NULL, "hsi_fck", "l3_init_cm:0018:24"),
|
||||
DT_CLK(NULL, "hsmmc1_fclk", "l3_init_cm:0008:24"),
|
||||
DT_CLK(NULL, "hsmmc2_fclk", "l3_init_cm:0010:24"),
|
||||
DT_CLK(NULL, "iss_ctrlclk", "iss_cm:0000:8"),
|
||||
DT_CLK(NULL, "mcasp_sync_mux_ck", "abe_cm:0020:26"),
|
||||
DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
|
||||
DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
|
||||
DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
|
||||
DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4_per_cm:00c0:26"),
|
||||
DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3_init_cm:00c0:8"),
|
||||
DT_CLK(NULL, "otg_60m_gfclk", "l3_init_cm:0040:24"),
|
||||
DT_CLK(NULL, "per_mcbsp4_gfclk", "l4_per_cm:00c0:24"),
|
||||
DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu_sys_cm:0000:20"),
|
||||
DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu_sys_cm:0000:22"),
|
||||
DT_CLK(NULL, "sgx_clk_mux", "l3_gfx_cm:0000:24"),
|
||||
DT_CLK(NULL, "slimbus1_fclk_0", "abe_cm:0040:8"),
|
||||
DT_CLK(NULL, "slimbus1_fclk_1", "abe_cm:0040:9"),
|
||||
DT_CLK(NULL, "slimbus1_fclk_2", "abe_cm:0040:10"),
|
||||
DT_CLK(NULL, "slimbus1_slimbus_clk", "abe_cm:0040:11"),
|
||||
DT_CLK(NULL, "slimbus2_fclk_0", "l4_per_cm:0118:8"),
|
||||
DT_CLK(NULL, "slimbus2_fclk_1", "l4_per_cm:0118:9"),
|
||||
DT_CLK(NULL, "slimbus2_slimbus_clk", "l4_per_cm:0118:10"),
|
||||
DT_CLK(NULL, "stm_clk_div_ck", "emu_sys_cm:0000:27"),
|
||||
DT_CLK(NULL, "timer5_sync_mux", "abe_cm:0048:24"),
|
||||
DT_CLK(NULL, "timer6_sync_mux", "abe_cm:0050:24"),
|
||||
DT_CLK(NULL, "timer7_sync_mux", "abe_cm:0058:24"),
|
||||
DT_CLK(NULL, "timer8_sync_mux", "abe_cm:0060:24"),
|
||||
DT_CLK(NULL, "trace_clk_div_div_ck", "emu_sys_cm:0000:24"),
|
||||
DT_CLK(NULL, "usb_host_hs_func48mclk", "l3_init_cm:0038:15"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3_init_cm:0038:13"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3_init_cm:0038:14"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3_init_cm:0038:11"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3_init_cm:0038:12"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3_init_cm:0038:8"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3_init_cm:0038:9"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init_cm:0038:10"),
|
||||
DT_CLK(NULL, "usb_otg_hs_xclk", "l3_init_cm:0040:8"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3_init_cm:0048:8"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3_init_cm:0048:9"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3_init_cm:0048:10"),
|
||||
DT_CLK(NULL, "utmi_p1_gfclk", "l3_init_cm:0038:24"),
|
||||
DT_CLK(NULL, "utmi_p2_gfclk", "l3_init_cm:0038:25"),
|
||||
DT_CLK(NULL, "aess_fclk", "abe-clkctrl:0008:24"),
|
||||
DT_CLK(NULL, "cm2_dm10_mux", "l4-per-clkctrl:0008:24"),
|
||||
DT_CLK(NULL, "cm2_dm11_mux", "l4-per-clkctrl:0010:24"),
|
||||
DT_CLK(NULL, "cm2_dm2_mux", "l4-per-clkctrl:0018:24"),
|
||||
DT_CLK(NULL, "cm2_dm3_mux", "l4-per-clkctrl:0020:24"),
|
||||
DT_CLK(NULL, "cm2_dm4_mux", "l4-per-clkctrl:0028:24"),
|
||||
DT_CLK(NULL, "cm2_dm9_mux", "l4-per-clkctrl:0030:24"),
|
||||
DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"),
|
||||
DT_CLK(NULL, "dmt1_clk_mux", "l4-wkup-clkctrl:0020:24"),
|
||||
DT_CLK(NULL, "dss_48mhz_clk", "l3-dss-clkctrl:0000:9"),
|
||||
DT_CLK(NULL, "dss_dss_clk", "l3-dss-clkctrl:0000:8"),
|
||||
DT_CLK(NULL, "dss_sys_clk", "l3-dss-clkctrl:0000:10"),
|
||||
DT_CLK(NULL, "dss_tv_clk", "l3-dss-clkctrl:0000:11"),
|
||||
DT_CLK(NULL, "fdif_fck", "iss-clkctrl:0008:24"),
|
||||
DT_CLK(NULL, "func_dmic_abe_gfclk", "abe-clkctrl:0018:24"),
|
||||
DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe-clkctrl:0020:24"),
|
||||
DT_CLK(NULL, "func_mcbsp1_gfclk", "abe-clkctrl:0028:24"),
|
||||
DT_CLK(NULL, "func_mcbsp2_gfclk", "abe-clkctrl:0030:24"),
|
||||
DT_CLK(NULL, "func_mcbsp3_gfclk", "abe-clkctrl:0038:24"),
|
||||
DT_CLK(NULL, "gpio1_dbclk", "l4-wkup-clkctrl:0018:8"),
|
||||
DT_CLK(NULL, "gpio2_dbclk", "l4-per-clkctrl:0040:8"),
|
||||
DT_CLK(NULL, "gpio3_dbclk", "l4-per-clkctrl:0048:8"),
|
||||
DT_CLK(NULL, "gpio4_dbclk", "l4-per-clkctrl:0050:8"),
|
||||
DT_CLK(NULL, "gpio5_dbclk", "l4-per-clkctrl:0058:8"),
|
||||
DT_CLK(NULL, "gpio6_dbclk", "l4-per-clkctrl:0060:8"),
|
||||
DT_CLK(NULL, "hsi_fck", "l3-init-clkctrl:0018:24"),
|
||||
DT_CLK(NULL, "hsmmc1_fclk", "l3-init-clkctrl:0008:24"),
|
||||
DT_CLK(NULL, "hsmmc2_fclk", "l3-init-clkctrl:0010:24"),
|
||||
DT_CLK(NULL, "iss_ctrlclk", "iss-clkctrl:0000:8"),
|
||||
DT_CLK(NULL, "mcasp_sync_mux_ck", "abe-clkctrl:0020:26"),
|
||||
DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
|
||||
DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
|
||||
DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
|
||||
DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4-per-clkctrl:00c0:26"),
|
||||
DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3-init-clkctrl:00c0:8"),
|
||||
DT_CLK(NULL, "otg_60m_gfclk", "l3-init-clkctrl:0040:24"),
|
||||
DT_CLK(NULL, "per_mcbsp4_gfclk", "l4-per-clkctrl:00c0:24"),
|
||||
DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu-sys-clkctrl:0000:20"),
|
||||
DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu-sys-clkctrl:0000:22"),
|
||||
DT_CLK(NULL, "sgx_clk_mux", "l3-gfx-clkctrl:0000:24"),
|
||||
DT_CLK(NULL, "slimbus1_fclk_0", "abe-clkctrl:0040:8"),
|
||||
DT_CLK(NULL, "slimbus1_fclk_1", "abe-clkctrl:0040:9"),
|
||||
DT_CLK(NULL, "slimbus1_fclk_2", "abe-clkctrl:0040:10"),
|
||||
DT_CLK(NULL, "slimbus1_slimbus_clk", "abe-clkctrl:0040:11"),
|
||||
DT_CLK(NULL, "slimbus2_fclk_0", "l4-per-clkctrl:0118:8"),
|
||||
DT_CLK(NULL, "slimbus2_fclk_1", "l4-per-clkctrl:0118:9"),
|
||||
DT_CLK(NULL, "slimbus2_slimbus_clk", "l4-per-clkctrl:0118:10"),
|
||||
DT_CLK(NULL, "stm_clk_div_ck", "emu-sys-clkctrl:0000:27"),
|
||||
DT_CLK(NULL, "timer5_sync_mux", "abe-clkctrl:0048:24"),
|
||||
DT_CLK(NULL, "timer6_sync_mux", "abe-clkctrl:0050:24"),
|
||||
DT_CLK(NULL, "timer7_sync_mux", "abe-clkctrl:0058:24"),
|
||||
DT_CLK(NULL, "timer8_sync_mux", "abe-clkctrl:0060:24"),
|
||||
DT_CLK(NULL, "trace_clk_div_div_ck", "emu-sys-clkctrl:0000:24"),
|
||||
DT_CLK(NULL, "usb_host_hs_func48mclk", "l3-init-clkctrl:0038:15"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3-init-clkctrl:0038:13"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3-init-clkctrl:0038:14"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3-init-clkctrl:0038:11"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3-init-clkctrl:0038:12"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3-init-clkctrl:0038:8"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3-init-clkctrl:0038:9"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init-clkctrl:0038:10"),
|
||||
DT_CLK(NULL, "usb_otg_hs_xclk", "l3-init-clkctrl:0040:8"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3-init-clkctrl:0048:8"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3-init-clkctrl:0048:9"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3-init-clkctrl:0048:10"),
|
||||
DT_CLK(NULL, "utmi_p1_gfclk", "l3-init-clkctrl:0038:24"),
|
||||
DT_CLK(NULL, "utmi_p2_gfclk", "l3-init-clkctrl:0038:25"),
|
||||
{ .node_name = NULL },
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ static const struct omap_clkctrl_bit_data omap5_aess_bit_data[] __initconst = {
|
|||
};
|
||||
|
||||
static const char * const omap5_dmic_gfclk_parents[] __initconst = {
|
||||
"abe_cm:clk:0018:26",
|
||||
"abe-clkctrl:0018:26",
|
||||
"pad_clks_ck",
|
||||
"slimbus_clk",
|
||||
NULL,
|
||||
|
|
@ -70,7 +70,7 @@ static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = {
|
|||
};
|
||||
|
||||
static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = {
|
||||
"abe_cm:clk:0028:26",
|
||||
"abe-clkctrl:0028:26",
|
||||
"pad_clks_ck",
|
||||
"slimbus_clk",
|
||||
NULL,
|
||||
|
|
@ -83,7 +83,7 @@ static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst =
|
|||
};
|
||||
|
||||
static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = {
|
||||
"abe_cm:clk:0030:26",
|
||||
"abe-clkctrl:0030:26",
|
||||
"pad_clks_ck",
|
||||
"slimbus_clk",
|
||||
NULL,
|
||||
|
|
@ -96,7 +96,7 @@ static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst =
|
|||
};
|
||||
|
||||
static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = {
|
||||
"abe_cm:clk:0038:26",
|
||||
"abe-clkctrl:0038:26",
|
||||
"pad_clks_ck",
|
||||
"slimbus_clk",
|
||||
NULL,
|
||||
|
|
@ -136,16 +136,16 @@ static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst =
|
|||
|
||||
static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = {
|
||||
{ OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
|
||||
{ OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" },
|
||||
{ OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
|
||||
{ OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
|
||||
{ OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
|
||||
{ OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
|
||||
{ OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
|
||||
{ OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
|
||||
{ OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
|
||||
{ OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
|
||||
{ OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
|
||||
{ OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
|
||||
{ OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
|
||||
{ OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
|
||||
{ OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
|
||||
{ OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" },
|
||||
{ OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" },
|
||||
{ OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" },
|
||||
{ OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" },
|
||||
{ OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
|
|
@ -268,12 +268,12 @@ static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = {
|
|||
};
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = {
|
||||
{ OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0008:24" },
|
||||
{ OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0010:24" },
|
||||
{ OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0018:24" },
|
||||
{ OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0020:24" },
|
||||
{ OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
|
||||
{ OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
|
||||
{ OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" },
|
||||
{ OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" },
|
||||
{ OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" },
|
||||
{ OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" },
|
||||
{ OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" },
|
||||
{ OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0030:24" },
|
||||
{ OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
|
||||
{ OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
|
||||
{ OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
|
||||
|
|
@ -345,7 +345,7 @@ static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst
|
|||
};
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = {
|
||||
{ OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
|
||||
{ OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
|
|
@ -378,7 +378,7 @@ static const struct omap_clkctrl_bit_data omap5_gpu_core_bit_data[] __initconst
|
|||
};
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = {
|
||||
{ OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24" },
|
||||
{ OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu-clkctrl:0000:24" },
|
||||
{ 0 },
|
||||
};
|
||||
|
||||
|
|
@ -389,7 +389,7 @@ static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = {
|
|||
};
|
||||
|
||||
static const char * const omap5_mmc1_fclk_parents[] __initconst = {
|
||||
"l3init_cm:clk:0008:24",
|
||||
"l3init-clkctrl:0008:24",
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
|
@ -405,7 +405,7 @@ static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = {
|
|||
};
|
||||
|
||||
static const char * const omap5_mmc2_fclk_parents[] __initconst = {
|
||||
"l3init_cm:clk:0010:24",
|
||||
"l3init-clkctrl:0010:24",
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
|
@ -430,12 +430,12 @@ static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initcons
|
|||
};
|
||||
|
||||
static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
|
||||
"l3init_cm:clk:0038:24",
|
||||
"l3init-clkctrl:0038:24",
|
||||
NULL,
|
||||
};
|
||||
|
||||
static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
|
||||
"l3init_cm:clk:0038:25",
|
||||
"l3init-clkctrl:0038:25",
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
|
@ -494,8 +494,8 @@ static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initcons
|
|||
};
|
||||
|
||||
static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = {
|
||||
{ OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
|
||||
{ OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
|
||||
{ OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" },
|
||||
{ OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },
|
||||
{ OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" },
|
||||
{ OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
|
||||
{ OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
|
||||
|
|
@ -519,7 +519,7 @@ static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initcon
|
|||
{ OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
|
||||
{ OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
|
||||
{ OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
|
||||
{ OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
|
||||
{ OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
|
||||
{ OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
|
||||
{ OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
|
||||
{ 0 },
|
||||
|
|
@ -549,58 +549,58 @@ const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
|
|||
static struct ti_dt_clk omap54xx_clks[] = {
|
||||
DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
|
||||
DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"),
|
||||
DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"),
|
||||
DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
|
||||
DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
|
||||
DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
|
||||
DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
|
||||
DT_CLK(NULL, "dss_sys_clk", "dss_cm:0000:10"),
|
||||
DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
|
||||
DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0040:8"),
|
||||
DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0048:8"),
|
||||
DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0050:8"),
|
||||
DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0058:8"),
|
||||
DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0060:8"),
|
||||
DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:00f0:8"),
|
||||
DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:00f8:8"),
|
||||
DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"),
|
||||
DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
|
||||
DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"),
|
||||
DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
|
||||
DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"),
|
||||
DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
|
||||
DT_CLK(NULL, "mmc1_32khz_clk", "l3init_cm:0008:8"),
|
||||
DT_CLK(NULL, "mmc1_fclk", "l3init_cm:0008:25"),
|
||||
DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
|
||||
DT_CLK(NULL, "mmc2_fclk", "l3init_cm:0010:25"),
|
||||
DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
|
||||
DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
|
||||
DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"),
|
||||
DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"),
|
||||
DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
|
||||
DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"),
|
||||
DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"),
|
||||
DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"),
|
||||
DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"),
|
||||
DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"),
|
||||
DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"),
|
||||
DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"),
|
||||
DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init_cm:0038:13"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init_cm:0038:14"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init_cm:0038:7"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init_cm:0038:11"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init_cm:0038:12"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init_cm:0038:6"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init_cm:0038:8"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init_cm:0038:9"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init_cm:0038:10"),
|
||||
DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init_cm:00d0:8"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init_cm:0048:8"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init_cm:0048:9"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init_cm:0048:10"),
|
||||
DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"),
|
||||
DT_CLK(NULL, "utmi_p2_gfclk", "l3init_cm:0038:25"),
|
||||
DT_CLK(NULL, "dmic_gfclk", "abe-clkctrl:0018:24"),
|
||||
DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"),
|
||||
DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
|
||||
DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
|
||||
DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
|
||||
DT_CLK(NULL, "dss_sys_clk", "dss-clkctrl:0000:10"),
|
||||
DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
|
||||
DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0040:8"),
|
||||
DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0048:8"),
|
||||
DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0050:8"),
|
||||
DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0058:8"),
|
||||
DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0060:8"),
|
||||
DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00f0:8"),
|
||||
DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f8:8"),
|
||||
DT_CLK(NULL, "mcbsp1_gfclk", "abe-clkctrl:0028:24"),
|
||||
DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
|
||||
DT_CLK(NULL, "mcbsp2_gfclk", "abe-clkctrl:0030:24"),
|
||||
DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
|
||||
DT_CLK(NULL, "mcbsp3_gfclk", "abe-clkctrl:0038:24"),
|
||||
DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
|
||||
DT_CLK(NULL, "mmc1_32khz_clk", "l3init-clkctrl:0008:8"),
|
||||
DT_CLK(NULL, "mmc1_fclk", "l3init-clkctrl:0008:25"),
|
||||
DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
|
||||
DT_CLK(NULL, "mmc2_fclk", "l3init-clkctrl:0010:25"),
|
||||
DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
|
||||
DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
|
||||
DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0008:24"),
|
||||
DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0010:24"),
|
||||
DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
|
||||
DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0018:24"),
|
||||
DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0020:24"),
|
||||
DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0028:24"),
|
||||
DT_CLK(NULL, "timer5_gfclk_mux", "abe-clkctrl:0048:24"),
|
||||
DT_CLK(NULL, "timer6_gfclk_mux", "abe-clkctrl:0050:24"),
|
||||
DT_CLK(NULL, "timer7_gfclk_mux", "abe-clkctrl:0058:24"),
|
||||
DT_CLK(NULL, "timer8_gfclk_mux", "abe-clkctrl:0060:24"),
|
||||
DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0030:24"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init-clkctrl:0038:13"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init-clkctrl:0038:14"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init-clkctrl:0038:7"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init-clkctrl:0038:11"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init-clkctrl:0038:12"),
|
||||
DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init-clkctrl:0038:6"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init-clkctrl:0038:8"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init-clkctrl:0038:9"),
|
||||
DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init-clkctrl:0038:10"),
|
||||
DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init-clkctrl:00d0:8"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init-clkctrl:0048:8"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init-clkctrl:0048:9"),
|
||||
DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init-clkctrl:0048:10"),
|
||||
DT_CLK(NULL, "utmi_p1_gfclk", "l3init-clkctrl:0038:24"),
|
||||
DT_CLK(NULL, "utmi_p2_gfclk", "l3init-clkctrl:0038:25"),
|
||||
{ .node_name = NULL },
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -528,10 +528,6 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
|
|||
char *c;
|
||||
u16 soc_mask = 0;
|
||||
|
||||
if (!(ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) &&
|
||||
of_node_name_eq(node, "clk"))
|
||||
ti_clk_features.flags |= TI_CLK_CLKCTRL_COMPAT;
|
||||
|
||||
addrp = of_get_address(node, 0, NULL, NULL);
|
||||
addr = (u32)of_translate_address(node, addrp);
|
||||
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8186
|
||||
#define _DT_BINDINGS_RESET_CONTROLLER_MT8186
|
||||
|
||||
/* TOPRGU resets */
|
||||
#define MT8186_TOPRGU_INFRA_SW_RST 0
|
||||
#define MT8186_TOPRGU_MM_SW_RST 1
|
||||
#define MT8186_TOPRGU_MFG_SW_RST 2
|
||||
|
|
@ -33,4 +34,8 @@
|
|||
/* MMSYS resets */
|
||||
#define MT8186_MMSYS_SW0_RST_B_DISP_DSI0 19
|
||||
|
||||
/* INFRA resets */
|
||||
#define MT8186_INFRA_THERMAL_CTRL_RST 0
|
||||
#define MT8186_INFRA_PTP_CTRL_RST 1
|
||||
|
||||
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8186 */
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
|
||||
#define _DT_BINDINGS_RESET_CONTROLLER_MT8192
|
||||
|
||||
/* TOPRGU resets */
|
||||
#define MT8192_TOPRGU_MM_SW_RST 1
|
||||
#define MT8192_TOPRGU_MFG_SW_RST 2
|
||||
#define MT8192_TOPRGU_VENC_SW_RST 3
|
||||
|
|
@ -30,4 +31,11 @@
|
|||
/* MMSYS resets */
|
||||
#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0 15
|
||||
|
||||
/* INFRA resets */
|
||||
#define MT8192_INFRA_RST0_THERM_CTRL_SWRST 0
|
||||
#define MT8192_INFRA_RST2_PEXTP_PHY_SWRST 1
|
||||
#define MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST 2
|
||||
#define MT8192_INFRA_RST4_PCIE_TOP_SWRST 3
|
||||
#define MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST 4
|
||||
|
||||
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195
|
||||
#define _DT_BINDINGS_RESET_CONTROLLER_MT8195
|
||||
|
||||
/* TOPRGU resets */
|
||||
#define MT8195_TOPRGU_CONN_MCU_SW_RST 0
|
||||
#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1
|
||||
#define MT8195_TOPRGU_APU_SW_RST 2
|
||||
|
|
@ -26,4 +27,9 @@
|
|||
|
||||
#define MT8195_TOPRGU_SW_RST_NUM 16
|
||||
|
||||
/* INFRA resets */
|
||||
#define MT8195_INFRA_RST0_THERM_CTRL_SWRST 0
|
||||
#define MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST 1
|
||||
#define MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST 2
|
||||
|
||||
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
|
||||
|
|
|
|||
|
|
@ -831,6 +831,25 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name,
|
|||
__devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
|
||||
NULL, (flags), (reg), (shift), (width), \
|
||||
(clk_divider_flags), NULL, (lock))
|
||||
/**
|
||||
* devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework
|
||||
* @dev: device registering this clock
|
||||
* @name: name of this clock
|
||||
* @parent_hw: pointer to parent clk
|
||||
* @flags: framework-specific flags
|
||||
* @reg: register address to adjust divider
|
||||
* @shift: number of bits to shift the bitfield
|
||||
* @width: width of the bitfield
|
||||
* @clk_divider_flags: divider-specific flags for this clock
|
||||
* @lock: shared register lock for this clock
|
||||
*/
|
||||
#define devm_clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, \
|
||||
reg, shift, width, \
|
||||
clk_divider_flags, lock) \
|
||||
__devm_clk_hw_register_divider((dev), NULL, (name), NULL, \
|
||||
(parent_hw), NULL, (flags), (reg), \
|
||||
(shift), (width), (clk_divider_flags), \
|
||||
NULL, (lock))
|
||||
/**
|
||||
* devm_clk_hw_register_divider_table - register a table based divider clock
|
||||
* with the clock framework (devres variant)
|
||||
|
|
@ -961,6 +980,13 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name,
|
|||
(parent_names), NULL, NULL, (flags), (reg), \
|
||||
(shift), BIT((width)) - 1, (clk_mux_flags), \
|
||||
NULL, (lock))
|
||||
#define devm_clk_hw_register_mux_parent_hws(dev, name, parent_hws, \
|
||||
num_parents, flags, reg, shift, \
|
||||
width, clk_mux_flags, lock) \
|
||||
__devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
|
||||
(parent_hws), NULL, (flags), (reg), \
|
||||
(shift), BIT((width)) - 1, \
|
||||
(clk_mux_flags), NULL, (lock))
|
||||
|
||||
int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int flags,
|
||||
unsigned int val);
|
||||
|
|
@ -1006,6 +1032,14 @@ struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
|
|||
struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
|
||||
const char *name, unsigned int index, unsigned long flags,
|
||||
unsigned int mult, unsigned int div);
|
||||
|
||||
struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev,
|
||||
const char *name, const struct clk_hw *parent_hw,
|
||||
unsigned long flags, unsigned int mult, unsigned int div);
|
||||
|
||||
struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev,
|
||||
const char *name, const struct clk_hw *parent_hw,
|
||||
unsigned long flags, unsigned int mult, unsigned int div);
|
||||
/**
|
||||
* struct clk_fractional_divider - adjustable fractional divider clock
|
||||
*
|
||||
|
|
@ -1176,10 +1210,8 @@ int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
|
|||
int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
|
||||
|
||||
void clk_unregister(struct clk *clk);
|
||||
void devm_clk_unregister(struct device *dev, struct clk *clk);
|
||||
|
||||
void clk_hw_unregister(struct clk_hw *hw);
|
||||
void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
|
||||
|
||||
/* helper functions */
|
||||
const char *__clk_get_name(const struct clk *clk);
|
||||
|
|
|
|||
|
|
@ -443,32 +443,130 @@ int __must_check devm_clk_bulk_get_all(struct device *dev,
|
|||
* @dev: device for clock "consumer"
|
||||
* @id: clock consumer ID
|
||||
*
|
||||
* Returns a struct clk corresponding to the clock producer, or
|
||||
* Context: May sleep.
|
||||
*
|
||||
* Return: a struct clk corresponding to the clock producer, or
|
||||
* valid IS_ERR() condition containing errno. The implementation
|
||||
* uses @dev and @id to determine the clock consumer, and thereby
|
||||
* the clock producer. (IOW, @id may be identical strings, but
|
||||
* clk_get may return different clock producers depending on @dev.)
|
||||
*
|
||||
* Drivers must assume that the clock source is not enabled.
|
||||
*
|
||||
* devm_clk_get should not be called from within interrupt context.
|
||||
* Drivers must assume that the clock source is neither prepared nor
|
||||
* enabled.
|
||||
*
|
||||
* The clock will automatically be freed when the device is unbound
|
||||
* from the bus.
|
||||
*/
|
||||
struct clk *devm_clk_get(struct device *dev, const char *id);
|
||||
|
||||
/**
|
||||
* devm_clk_get_prepared - devm_clk_get() + clk_prepare()
|
||||
* @dev: device for clock "consumer"
|
||||
* @id: clock consumer ID
|
||||
*
|
||||
* Context: May sleep.
|
||||
*
|
||||
* Return: a struct clk corresponding to the clock producer, or
|
||||
* valid IS_ERR() condition containing errno. The implementation
|
||||
* uses @dev and @id to determine the clock consumer, and thereby
|
||||
* the clock producer. (IOW, @id may be identical strings, but
|
||||
* clk_get may return different clock producers depending on @dev.)
|
||||
*
|
||||
* The returned clk (if valid) is prepared. Drivers must however assume
|
||||
* that the clock is not enabled.
|
||||
*
|
||||
* The clock will automatically be unprepared and freed when the device
|
||||
* is unbound from the bus.
|
||||
*/
|
||||
struct clk *devm_clk_get_prepared(struct device *dev, const char *id);
|
||||
|
||||
/**
|
||||
* devm_clk_get_enabled - devm_clk_get() + clk_prepare_enable()
|
||||
* @dev: device for clock "consumer"
|
||||
* @id: clock consumer ID
|
||||
*
|
||||
* Context: May sleep.
|
||||
*
|
||||
* Return: a struct clk corresponding to the clock producer, or
|
||||
* valid IS_ERR() condition containing errno. The implementation
|
||||
* uses @dev and @id to determine the clock consumer, and thereby
|
||||
* the clock producer. (IOW, @id may be identical strings, but
|
||||
* clk_get may return different clock producers depending on @dev.)
|
||||
*
|
||||
* The returned clk (if valid) is prepared and enabled.
|
||||
*
|
||||
* The clock will automatically be disabled, unprepared and freed
|
||||
* when the device is unbound from the bus.
|
||||
*/
|
||||
struct clk *devm_clk_get_enabled(struct device *dev, const char *id);
|
||||
|
||||
/**
|
||||
* devm_clk_get_optional - lookup and obtain a managed reference to an optional
|
||||
* clock producer.
|
||||
* @dev: device for clock "consumer"
|
||||
* @id: clock consumer ID
|
||||
*
|
||||
* Behaves the same as devm_clk_get() except where there is no clock producer.
|
||||
* In this case, instead of returning -ENOENT, the function returns NULL.
|
||||
* Context: May sleep.
|
||||
*
|
||||
* Return: a struct clk corresponding to the clock producer, or
|
||||
* valid IS_ERR() condition containing errno. The implementation
|
||||
* uses @dev and @id to determine the clock consumer, and thereby
|
||||
* the clock producer. If no such clk is found, it returns NULL
|
||||
* which serves as a dummy clk. That's the only difference compared
|
||||
* to devm_clk_get().
|
||||
*
|
||||
* Drivers must assume that the clock source is neither prepared nor
|
||||
* enabled.
|
||||
*
|
||||
* The clock will automatically be freed when the device is unbound
|
||||
* from the bus.
|
||||
*/
|
||||
struct clk *devm_clk_get_optional(struct device *dev, const char *id);
|
||||
|
||||
/**
|
||||
* devm_clk_get_optional_prepared - devm_clk_get_optional() + clk_prepare()
|
||||
* @dev: device for clock "consumer"
|
||||
* @id: clock consumer ID
|
||||
*
|
||||
* Context: May sleep.
|
||||
*
|
||||
* Return: a struct clk corresponding to the clock producer, or
|
||||
* valid IS_ERR() condition containing errno. The implementation
|
||||
* uses @dev and @id to determine the clock consumer, and thereby
|
||||
* the clock producer. If no such clk is found, it returns NULL
|
||||
* which serves as a dummy clk. That's the only difference compared
|
||||
* to devm_clk_get_prepared().
|
||||
*
|
||||
* The returned clk (if valid) is prepared. Drivers must however
|
||||
* assume that the clock is not enabled.
|
||||
*
|
||||
* The clock will automatically be unprepared and freed when the
|
||||
* device is unbound from the bus.
|
||||
*/
|
||||
struct clk *devm_clk_get_optional_prepared(struct device *dev, const char *id);
|
||||
|
||||
/**
|
||||
* devm_clk_get_optional_enabled - devm_clk_get_optional() +
|
||||
* clk_prepare_enable()
|
||||
* @dev: device for clock "consumer"
|
||||
* @id: clock consumer ID
|
||||
*
|
||||
* Context: May sleep.
|
||||
*
|
||||
* Return: a struct clk corresponding to the clock producer, or
|
||||
* valid IS_ERR() condition containing errno. The implementation
|
||||
* uses @dev and @id to determine the clock consumer, and thereby
|
||||
* the clock producer. If no such clk is found, it returns NULL
|
||||
* which serves as a dummy clk. That's the only difference compared
|
||||
* to devm_clk_get_enabled().
|
||||
*
|
||||
* The returned clk (if valid) is prepared and enabled.
|
||||
*
|
||||
* The clock will automatically be disabled, unprepared and freed
|
||||
* when the device is unbound from the bus.
|
||||
*/
|
||||
struct clk *devm_clk_get_optional_enabled(struct device *dev, const char *id);
|
||||
|
||||
/**
|
||||
* devm_get_clk_from_child - lookup and obtain a managed reference to a
|
||||
* clock producer from child node.
|
||||
|
|
@ -813,12 +911,36 @@ static inline struct clk *devm_clk_get(struct device *dev, const char *id)
|
|||
return NULL;
|
||||
}
|
||||
|
||||
static inline struct clk *devm_clk_get_prepared(struct device *dev,
|
||||
const char *id)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline struct clk *devm_clk_get_enabled(struct device *dev,
|
||||
const char *id)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline struct clk *devm_clk_get_optional(struct device *dev,
|
||||
const char *id)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline struct clk *devm_clk_get_optional_prepared(struct device *dev,
|
||||
const char *id)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline struct clk *devm_clk_get_optional_enabled(struct device *dev,
|
||||
const char *id)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline int __must_check devm_clk_bulk_get(struct device *dev, int num_clks,
|
||||
struct clk_bulk_data *clks)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in a new issue