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wifi: rtw89: add XTAL SI for WiFi 7 chips

Browse source 
The XTAL SI is a serial interface to indirectly access registers of
analog hardware circuit. Since WiFi 7 chips use different registers, add
a ops to access them via common functions. This patch doesn't change logic
for existing chips.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://msgid.link/20231211083341.118047-2-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih 2023-12-11 16:33:36 +08:00 committed by Kalle Valo
parent f0536b0d5f
commit efde4f6dd1
4 changed files with 88 additions and 6 deletions
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11
drivers/net/wireless/realtek/rtw89/mac.c
View file

@ -5946,7 +5946,8 @@ int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,
return 0;
}
int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
static
int rtw89_mac_write_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
{
u32 val32;
int ret;
@ -5968,9 +5969,9 @@ int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask
return 0;
}
EXPORT_SYMBOL(rtw89_mac_write_xtal_si);
int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
static
int rtw89_mac_read_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
{
u32 val32;
int ret;
@ -5993,7 +5994,6 @@ int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
return 0;
}
EXPORT_SYMBOL(rtw89_mac_read_xtal_si);
static
void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta)
@ -6127,6 +6127,9 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_ax = {
.get_txpwr_cr = rtw89_mac_get_txpwr_cr_ax,
.write_xtal_si = rtw89_mac_write_xtal_si_ax,
.read_xtal_si = rtw89_mac_read_xtal_si_ax,
.dump_qta_lost = rtw89_mac_dump_qta_lost_ax,
.dump_err_status = rtw89_mac_dump_err_status_ax,

21
drivers/net/wireless/realtek/rtw89/mac.h
View file

@ -935,6 +935,9 @@ struct rtw89_mac_gen_def {
enum rtw89_phy_idx phy_idx,
u32 reg_base, u32 *cr);
int (*write_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask);
int (*read_xtal_si)(struct rtw89_dev *rtwdev, u8 offset, u8 *val);
void (*dump_qta_lost)(struct rtw89_dev *rtwdev);
void (*dump_err_status)(struct rtw89_dev *rtwdev,
enum mac_ax_err_info err);
@ -1296,8 +1299,22 @@ enum rtw89_mac_xtal_si_offset {
#define FULL_BIT_MASK GENMASK(7, 0)
};
int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask);
int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val);
static inline
int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
{
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
return mac->write_xtal_si(rtwdev, offset, val, mask);
}
static inline
int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
{
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
return mac->read_xtal_si(rtwdev, offset, val);
}
void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev,
enum rtw89_machdr_frame_type type,

54
drivers/net/wireless/realtek/rtw89/mac_be.c
View file

@ -348,6 +348,57 @@ static void rtw89_mac_dmac_func_pre_en_be(struct rtw89_dev *rtwdev)
rtw89_write32_set(rtwdev, R_BE_DMAC_TABLE_CTRL, B_BE_DMAC_ADDR_MODE);
}
static
int rtw89_mac_write_xtal_si_be(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
{
u32 val32;
int ret;
val32 = u32_encode_bits(offset, B_BE_WL_XTAL_SI_ADDR_MASK) |
u32_encode_bits(val, B_BE_WL_XTAL_SI_DATA_MASK) |
u32_encode_bits(mask, B_BE_WL_XTAL_SI_BITMASK_MASK) |
u32_encode_bits(XTAL_SI_NORMAL_WRITE, B_BE_WL_XTAL_SI_MODE_MASK) |
u32_encode_bits(0, B_BE_WL_XTAL_SI_CHIPID_MASK) |
B_BE_WL_XTAL_SI_CMD_POLL;
rtw89_write32(rtwdev, R_BE_WLAN_XTAL_SI_CTRL, val32);
ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_WL_XTAL_SI_CMD_POLL),
50, 50000, false, rtwdev, R_BE_WLAN_XTAL_SI_CTRL);
if (ret) {
rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n",
offset, val, mask);
return ret;
}
return 0;
}
static
int rtw89_mac_read_xtal_si_be(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
{
u32 val32;
int ret;
val32 = u32_encode_bits(offset, B_BE_WL_XTAL_SI_ADDR_MASK) |
u32_encode_bits(0x0, B_BE_WL_XTAL_SI_DATA_MASK) |
u32_encode_bits(0x0, B_BE_WL_XTAL_SI_BITMASK_MASK) |
u32_encode_bits(XTAL_SI_NORMAL_READ, B_BE_WL_XTAL_SI_MODE_MASK) |
u32_encode_bits(0, B_BE_WL_XTAL_SI_CHIPID_MASK) |
B_BE_WL_XTAL_SI_CMD_POLL;
rtw89_write32(rtwdev, R_BE_WLAN_XTAL_SI_CTRL, val32);
ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_WL_XTAL_SI_CMD_POLL),
50, 50000, false, rtwdev, R_BE_WLAN_XTAL_SI_CTRL);
if (ret) {
rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset);
return ret;
}
*val = rtw89_read8(rtwdev, R_BE_WLAN_XTAL_SI_CTRL + 1);
return 0;
}
static void rtw89_mac_disable_cpu_be(struct rtw89_dev *rtwdev)
{
u32 val32;
@ -1121,6 +1172,9 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_be = {
.get_txpwr_cr = rtw89_mac_get_txpwr_cr_be,
.write_xtal_si = rtw89_mac_write_xtal_si_be,
.read_xtal_si = rtw89_mac_read_xtal_si_be,
.dump_qta_lost = rtw89_mac_dump_qta_lost_be,
.dump_err_status = rtw89_mac_dump_err_status_be,

8
drivers/net/wireless/realtek/rtw89/reg.h
View file

@ -4085,6 +4085,14 @@
#define R_BE_UDM2 0x01F8
#define B_BE_UDM2_EPC_RA_MASK GENMASK(31, 0)
#define R_BE_WLAN_XTAL_SI_CTRL 0x0270
#define B_BE_WL_XTAL_SI_CMD_POLL BIT(31)
#define B_BE_WL_XTAL_SI_CHIPID_MASK GENMASK(30, 28)
#define B_BE_WL_XTAL_SI_MODE_MASK GENMASK(25, 24)
#define B_BE_WL_XTAL_SI_BITMASK_MASK GENMASK(23, 16)
#define B_BE_WL_XTAL_SI_DATA_MASK GENMASK(15, 8)
#define B_BE_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0)
#define R_BE_IC_PWR_STATE 0x03F0
#define B_BE_WHOLE_SYS_PWR_STE_MASK GENMASK(25, 16)
#define MAC_AX_SYS_ACT 0x220