mirror of
https://github.com/torvalds/linux
synced 2024-09-06 18:01:05 +00:00
- Work around an erratum on GIC700, where a race between a CPU
handling a wake-up interrupt, a change of affinity, and another CPU going to sleep can result in a lack of wake-up event on the next interrupt. - Fix the locking required on a VPE for GICv4 - Enable Rockchip 3588001 erratum workaround for RK3588S - Fix the irq-bcm6345-l1 assumtions of the boot CPU always be the first CPU in the system -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmTGKO4ACgkQEsHwGGHe VUrFeQ//XELNf+LvlnKKSrkCpwDHE5E0AKYWlB7baMZCNKOLM826uNHQRhRfE7B3 UWZwM4vpzUaS3z2+RQTLv0ExrFvMoJ/twbVqI7D2c+HFu+BzJNjxQ6RbVtyVQm6a 3EODHN4+kwW/RYr5ZVNJlQUECj3u1a3bGNzlCozsB8Ju4p8uEHR2LtgrWBYWKHXK h4zPn1EQDRR0giHf2Vzh6HOP9y6fi7MXfTspxULZcl/z5OBXhQy9g09nu1jl8C/7 Jif3wQR7a5n2Sz32VbT10Ken45qyivAWZwnPPGQr9qwwrDry+ZnSt2oBvFD75dqc lpfzb3hFFwzCOSOgxoX1GIJgEsxbwgbGvIgH5Urg3bTxlvU+Ov1snQpjhqXZNdtI 6qd6b71SOhPo2/Tb6hEJjxmTgRm1uBIFVZMhqyvKzajNUrXdeo0QdZdR5Njvbe1y w7ix/0IdLIs14AzGS4X5SeoULz2N4GbDQUe2NisHk+SEa/dSWKy8dlGTEmxb8iLu Zs8PDnjDCJeGck/p8ObeEhyWS8/j6MkyXhgPa8+DMS/I16zpuaf4xhzkof5sUIiB a1maJLMfoEOnJjFjI349NxJU/58cDRvHGZXUPYQdp+WQP/Iovuoth1ZR3Algjgbg m97b/8WR9HpZVq0ZlAwgPcazvAfwTiP/9rlgEjE2O1HRNI1wlck= =a+f0 -----END PGP SIGNATURE----- Merge tag 'irq_urgent_for_v6.5_rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq fixes from Borislav Petkov: - Work around an erratum on GIC700, where a race between a CPU handling a wake-up interrupt, a change of affinity, and another CPU going to sleep can result in a lack of wake-up event on the next interrupt - Fix the locking required on a VPE for GICv4 - Enable Rockchip 3588001 erratum workaround for RK3588S - Fix the irq-bcm6345-l1 assumtions of the boot CPU always be the first CPU in the system * tag 'irq_urgent_for_v6.5_rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/gic-v3: Workaround for GIC-700 erratum 2941627 irqchip/gic-v3: Enable Rockchip 3588001 erratum workaround for RK3588S irqchip/gic-v4.1: Properly lock VPEs when doing a directLPI invalidation irq-bcm6345-l1: Do not assume a fixed block to cpu mapping
This commit is contained in:
commit
eb9fe1791b
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@ -148,6 +148,9 @@ stable kernels.
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| ARM | MMU-700 | #2268618,2812531| N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | GIC-700 | #2941627 | ARM64_ERRATUM_2941627 |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_845719 |
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+----------------+-----------------+-----------------+-----------------------------+
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| Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_843419 |
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@ -82,6 +82,7 @@ struct bcm6345_l1_chip {
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};
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struct bcm6345_l1_cpu {
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struct bcm6345_l1_chip *intc;
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void __iomem *map_base;
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unsigned int parent_irq;
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u32 enable_cache[];
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@ -115,17 +116,11 @@ static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc,
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static void bcm6345_l1_irq_handle(struct irq_desc *desc)
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{
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struct bcm6345_l1_chip *intc = irq_desc_get_handler_data(desc);
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struct bcm6345_l1_cpu *cpu;
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struct bcm6345_l1_cpu *cpu = irq_desc_get_handler_data(desc);
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struct bcm6345_l1_chip *intc = cpu->intc;
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned int idx;
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#ifdef CONFIG_SMP
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cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
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#else
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cpu = intc->cpus[0];
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#endif
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chained_irq_enter(chip, desc);
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for (idx = 0; idx < intc->n_words; idx++) {
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@ -253,6 +248,7 @@ static int __init bcm6345_l1_init_one(struct device_node *dn,
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if (!cpu)
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return -ENOMEM;
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cpu->intc = intc;
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cpu->map_base = ioremap(res.start, sz);
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if (!cpu->map_base)
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return -ENOMEM;
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@ -271,7 +267,7 @@ static int __init bcm6345_l1_init_one(struct device_node *dn,
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return -EINVAL;
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}
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irq_set_chained_handler_and_data(cpu->parent_irq,
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bcm6345_l1_irq_handle, intc);
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bcm6345_l1_irq_handle, cpu);
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return 0;
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}
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@ -273,13 +273,23 @@ static void vpe_to_cpuid_unlock(struct its_vpe *vpe, unsigned long flags)
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raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);
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}
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static struct irq_chip its_vpe_irq_chip;
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static int irq_to_cpuid_lock(struct irq_data *d, unsigned long *flags)
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{
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struct its_vlpi_map *map = get_vlpi_map(d);
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struct its_vpe *vpe = NULL;
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int cpu;
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if (map) {
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cpu = vpe_to_cpuid_lock(map->vpe, flags);
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if (d->chip == &its_vpe_irq_chip) {
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vpe = irq_data_get_irq_chip_data(d);
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} else {
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struct its_vlpi_map *map = get_vlpi_map(d);
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if (map)
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vpe = map->vpe;
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}
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if (vpe) {
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cpu = vpe_to_cpuid_lock(vpe, flags);
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} else {
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/* Physical LPIs are already locked via the irq_desc lock */
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struct its_device *its_dev = irq_data_get_irq_chip_data(d);
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@ -293,10 +303,18 @@ static int irq_to_cpuid_lock(struct irq_data *d, unsigned long *flags)
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static void irq_to_cpuid_unlock(struct irq_data *d, unsigned long flags)
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{
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struct its_vlpi_map *map = get_vlpi_map(d);
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struct its_vpe *vpe = NULL;
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if (map)
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vpe_to_cpuid_unlock(map->vpe, flags);
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if (d->chip == &its_vpe_irq_chip) {
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vpe = irq_data_get_irq_chip_data(d);
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} else {
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struct its_vlpi_map *map = get_vlpi_map(d);
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if (map)
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vpe = map->vpe;
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}
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if (vpe)
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vpe_to_cpuid_unlock(vpe, flags);
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}
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static struct its_collection *valid_col(struct its_collection *col)
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@ -1433,13 +1451,28 @@ static void wait_for_syncr(void __iomem *rdbase)
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cpu_relax();
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}
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static void __direct_lpi_inv(struct irq_data *d, u64 val)
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{
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void __iomem *rdbase;
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unsigned long flags;
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int cpu;
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/* Target the redistributor this LPI is currently routed to */
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cpu = irq_to_cpuid_lock(d, &flags);
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raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
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rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
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gic_write_lpir(val, rdbase + GICR_INVLPIR);
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wait_for_syncr(rdbase);
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raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
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irq_to_cpuid_unlock(d, flags);
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}
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static void direct_lpi_inv(struct irq_data *d)
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{
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struct its_vlpi_map *map = get_vlpi_map(d);
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void __iomem *rdbase;
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unsigned long flags;
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u64 val;
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int cpu;
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if (map) {
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struct its_device *its_dev = irq_data_get_irq_chip_data(d);
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@ -1453,15 +1486,7 @@ static void direct_lpi_inv(struct irq_data *d)
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val = d->hwirq;
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}
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/* Target the redistributor this LPI is currently routed to */
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cpu = irq_to_cpuid_lock(d, &flags);
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raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
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rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
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gic_write_lpir(val, rdbase + GICR_INVLPIR);
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wait_for_syncr(rdbase);
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raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
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irq_to_cpuid_unlock(d, flags);
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__direct_lpi_inv(d, val);
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}
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static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
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@ -3953,18 +3978,10 @@ static void its_vpe_send_inv(struct irq_data *d)
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{
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struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
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if (gic_rdists->has_direct_lpi) {
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void __iomem *rdbase;
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/* Target the redistributor this VPE is currently known on */
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raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
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rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
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gic_write_lpir(d->parent_data->hwirq, rdbase + GICR_INVLPIR);
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wait_for_syncr(rdbase);
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raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
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} else {
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if (gic_rdists->has_direct_lpi)
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__direct_lpi_inv(d, d->parent_data->hwirq);
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else
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its_vpe_send_cmd(vpe, its_send_inv);
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}
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}
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static void its_vpe_mask_irq(struct irq_data *d)
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@ -4727,7 +4744,8 @@ static bool __maybe_unused its_enable_rk3588001(void *data)
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{
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struct its_node *its = data;
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if (!of_machine_is_compatible("rockchip,rk3588"))
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if (!of_machine_is_compatible("rockchip,rk3588") &&
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!of_machine_is_compatible("rockchip,rk3588s"))
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return false;
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its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE;
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@ -69,6 +69,8 @@ struct gic_chip_data {
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static void __iomem *t241_dist_base_alias[T241_CHIPS_MAX] __read_mostly;
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static DEFINE_STATIC_KEY_FALSE(gic_nvidia_t241_erratum);
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static DEFINE_STATIC_KEY_FALSE(gic_arm64_2941627_erratum);
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static struct gic_chip_data gic_data __read_mostly;
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static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
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@ -592,10 +594,39 @@ static void gic_irq_nmi_teardown(struct irq_data *d)
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gic_irq_set_prio(d, GICD_INT_DEF_PRI);
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}
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static bool gic_arm64_erratum_2941627_needed(struct irq_data *d)
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{
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enum gic_intid_range range;
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if (!static_branch_unlikely(&gic_arm64_2941627_erratum))
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return false;
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range = get_intid_range(d);
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/*
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* The workaround is needed if the IRQ is an SPI and
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* the target cpu is different from the one we are
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* executing on.
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*/
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return (range == SPI_RANGE || range == ESPI_RANGE) &&
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!cpumask_test_cpu(raw_smp_processor_id(),
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irq_data_get_effective_affinity_mask(d));
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}
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static void gic_eoi_irq(struct irq_data *d)
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{
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write_gicreg(gic_irq(d), ICC_EOIR1_EL1);
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isb();
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if (gic_arm64_erratum_2941627_needed(d)) {
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/*
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* Make sure the GIC stream deactivate packet
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* issued by ICC_EOIR1_EL1 has completed before
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* deactivating through GICD_IACTIVER.
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*/
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dsb(sy);
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gic_poke_irq(d, GICD_ICACTIVER);
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}
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}
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static void gic_eoimode1_eoi_irq(struct irq_data *d)
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*/
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if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
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return;
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gic_write_dir(gic_irq(d));
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if (!gic_arm64_erratum_2941627_needed(d))
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gic_write_dir(gic_irq(d));
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else
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gic_poke_irq(d, GICD_ICACTIVER);
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}
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static int gic_set_type(struct irq_data *d, unsigned int type)
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@ -1816,6 +1851,12 @@ static bool gic_enable_quirk_asr8601(void *data)
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return true;
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}
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static bool gic_enable_quirk_arm64_2941627(void *data)
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{
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static_branch_enable(&gic_arm64_2941627_erratum);
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return true;
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}
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static const struct gic_quirk gic_quirks[] = {
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{
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.desc = "GICv3: Qualcomm MSM8996 broken firmware",
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.mask = 0xffffffff,
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.init = gic_enable_quirk_nvidia_t241,
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},
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{
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/*
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* GIC-700: 2941627 workaround - IP variant [0,1]
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*
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*/
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.desc = "GICv3: ARM64 erratum 2941627",
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.iidr = 0x0400043b,
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.mask = 0xff0e0fff,
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.init = gic_enable_quirk_arm64_2941627,
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},
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{
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/*
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* GIC-700: 2941627 workaround - IP variant [2]
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*/
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.desc = "GICv3: ARM64 erratum 2941627",
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.iidr = 0x0402043b,
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.mask = 0xff0f0fff,
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.init = gic_enable_quirk_arm64_2941627,
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},
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{
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}
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};
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