mirror of
https://github.com/torvalds/linux
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Merge tag 'drm-msm-next-2017-06-20' of git://people.freedesktop.org/~robclark/linux into drm-next
This time around, the biggest thing is a bunch of GEM rework for more fine grained locking and prep work to handle multiple address spaces (ie. per-process pagetables). Also some HDMI fixes for 8x96 (snapdragon 820). One unrelated bus patch, for something that seems to get merged through whatever random tree (and has all the right ack's). * tag 'drm-msm-next-2017-06-20' of git://people.freedesktop.org/~robclark/linux: drm/msm: Fix potential buffer overflow issue bus: SIMPLE_PM_BUS does not depend on ARCH_RENESAS drm/msm: Separate locking of buffer resources from struct_mutex drm/msm/hdmi: Fix HDMI pink strip issue seen on 8x96 drm/msm/hdmi: 8996 PLL: Populate unprepare drm/msm/hdmi: Use bitwise operators when building register values drm/msm: update generated headers drm/msm: remove address-space id drm/msm: support for an arbitrary number of address spaces drm/msm: refactor how we handle vram carveout buffers drm/msm: pass address-space to _get_iova() and friends drm/msm/mdp4+5: move aspace/id to base class drm/msm/mdp5: kill pipe_lock drm/msm: fix locking inconsistency for gpu->hw_init() drm/msm: Remove memptrs->wptr drm/msm: Add a struct to pass configuration to msm_gpu_init() drm/msm: Add hint to DRM_IOCTL_MSM_GEM_INFO to return an object IOVA drm/msm: Remove idle function hook drm/msm: Remove DRM_MSM_NUM_IOCTLS drm/msm: gpu: Enable zap shader for A5XX
This commit is contained in:
Dave Airlie
commit
eafae133e4
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@ -121,7 +121,6 @@ config QCOM_EBI2
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config SIMPLE_PM_BUS
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bool "Simple Power-Managed Bus Driver"
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depends on OF && PM
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depends on ARCH_RENESAS || COMPILE_TEST
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help
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Driver for transparent busses that don't need a real driver, but
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where the bus controller is part of a PM domain, or under the control
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|
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@ -5,6 +5,7 @@ config DRM_MSM
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depends on ARCH_QCOM || (ARM && COMPILE_TEST)
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depends on OF && COMMON_CLK
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depends on MMU
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select QCOM_MDT_LOADER
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select REGULATOR
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select DRM_KMS_HELPER
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select DRM_PANEL
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|
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@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
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|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
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||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
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Copyright (C) 2013-2016 by the following authors:
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Copyright (C) 2013-2017 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
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@ -352,6 +352,38 @@ static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_cln
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#define REG_A2XX_RBBM_DEBUG 0x0000039b
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||||
#define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c
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#define A2XX_RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE 0x00000001
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#define A2XX_RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE 0x00000002
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#define A2XX_RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE 0x00000004
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#define A2XX_RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE 0x00000008
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#define A2XX_RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE 0x00000010
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#define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE 0x00000020
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#define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040
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#define A2XX_RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080
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#define A2XX_RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE 0x00000100
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#define A2XX_RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE 0x00000200
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#define A2XX_RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE 0x00000400
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#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE 0x00000800
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#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE 0x00001000
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#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE 0x00002000
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#define A2XX_RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE 0x00004000
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||||
#define A2XX_RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE 0x00008000
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#define A2XX_RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE 0x00010000
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#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE 0x00020000
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#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE 0x00040000
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#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000
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#define A2XX_RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE 0x00100000
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#define A2XX_RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE 0x00200000
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#define A2XX_RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE 0x00400000
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#define A2XX_RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE 0x00800000
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#define A2XX_RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE 0x01000000
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#define A2XX_RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE 0x02000000
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#define A2XX_RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE 0x04000000
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||||
#define A2XX_RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE 0x08000000
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#define A2XX_RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE 0x10000000
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#define A2XX_RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE 0x20000000
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#define A2XX_RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE 0x40000000
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#define A2XX_RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000
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#define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d
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|
||||
|
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@ -477,12 +509,43 @@ static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x000
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#define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81
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||||
|
||||
#define REG_A2XX_PA_SU_FACE_DATA 0x00000c86
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||||
#define A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK 0xffffffe0
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#define A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT 5
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static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val)
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||||
{
|
||||
return ((val) << A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT) & A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK;
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||||
}
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||||
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||||
#define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00
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#define A2XX_SQ_GPR_MANAGEMENT_REG_DYNAMIC 0x00000001
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#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK 0x00000ff0
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#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT 4
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static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val)
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{
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return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK;
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}
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#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK 0x000ff000
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#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT 12
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static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val)
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{
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return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK;
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}
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#define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01
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#define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02
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#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK 0x00000fff
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#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT 0
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static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val)
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{
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return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK;
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}
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#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK 0x0fff0000
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#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT 16
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static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val)
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{
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return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK;
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}
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#define REG_A2XX_SQ_DEBUG_MISC 0x00000d05
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@ -742,6 +805,24 @@ static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
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#define REG_A2XX_RB_BLEND_ALPHA 0x00002108
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#define REG_A2XX_RB_FOG_COLOR 0x00002109
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#define A2XX_RB_FOG_COLOR_FOG_RED__MASK 0x000000ff
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#define A2XX_RB_FOG_COLOR_FOG_RED__SHIFT 0
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static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val)
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{
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return ((val) << A2XX_RB_FOG_COLOR_FOG_RED__SHIFT) & A2XX_RB_FOG_COLOR_FOG_RED__MASK;
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}
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#define A2XX_RB_FOG_COLOR_FOG_GREEN__MASK 0x0000ff00
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#define A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT 8
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static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val)
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{
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return ((val) << A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT) & A2XX_RB_FOG_COLOR_FOG_GREEN__MASK;
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}
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#define A2XX_RB_FOG_COLOR_FOG_BLUE__MASK 0x00ff0000
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#define A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT 16
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static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val)
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{
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return ((val) << A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT) & A2XX_RB_FOG_COLOR_FOG_BLUE__MASK;
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}
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#define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c
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#define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
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@ -890,14 +971,146 @@ static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val)
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#define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000
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#define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182
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#define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK 0x0000ffff
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#define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT 0
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static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val)
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{
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return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK;
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}
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#define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK 0xffff0000
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#define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT 16
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static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val)
|
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{
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return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK;
|
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}
|
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#define REG_A2XX_SQ_WRAPPING_0 0x00002183
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#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK 0x0000000f
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#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT 0
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static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val)
|
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{
|
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return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK;
|
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}
|
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#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK 0x000000f0
|
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#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT 4
|
||||
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val)
|
||||
{
|
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return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK;
|
||||
}
|
||||
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK 0x00000f00
|
||||
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT 8
|
||||
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK;
|
||||
}
|
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#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK 0x0000f000
|
||||
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT 12
|
||||
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK;
|
||||
}
|
||||
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK 0x000f0000
|
||||
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT 16
|
||||
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK;
|
||||
}
|
||||
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK 0x00f00000
|
||||
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT 20
|
||||
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK;
|
||||
}
|
||||
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK 0x0f000000
|
||||
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT 24
|
||||
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK;
|
||||
}
|
||||
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK 0xf0000000
|
||||
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT 28
|
||||
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK;
|
||||
}
|
||||
|
||||
#define REG_A2XX_SQ_WRAPPING_1 0x00002184
|
||||
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK 0x0000000f
|
||||
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT 0
|
||||
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK;
|
||||
}
|
||||
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK 0x000000f0
|
||||
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT 4
|
||||
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK;
|
||||
}
|
||||
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK 0x00000f00
|
||||
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT 8
|
||||
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK;
|
||||
}
|
||||
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK 0x0000f000
|
||||
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT 12
|
||||
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK;
|
||||
}
|
||||
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK 0x000f0000
|
||||
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT 16
|
||||
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK;
|
||||
}
|
||||
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK 0x00f00000
|
||||
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT 20
|
||||
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK;
|
||||
}
|
||||
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK 0x0f000000
|
||||
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT 24
|
||||
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK;
|
||||
}
|
||||
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK 0xf0000000
|
||||
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT 28
|
||||
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK;
|
||||
}
|
||||
|
||||
#define REG_A2XX_SQ_PS_PROGRAM 0x000021f6
|
||||
#define A2XX_SQ_PS_PROGRAM_BASE__MASK 0x00000fff
|
||||
#define A2XX_SQ_PS_PROGRAM_BASE__SHIFT 0
|
||||
static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_PS_PROGRAM_BASE__SHIFT) & A2XX_SQ_PS_PROGRAM_BASE__MASK;
|
||||
}
|
||||
#define A2XX_SQ_PS_PROGRAM_SIZE__MASK 0x00fff000
|
||||
#define A2XX_SQ_PS_PROGRAM_SIZE__SHIFT 12
|
||||
static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_PS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_PS_PROGRAM_SIZE__MASK;
|
||||
}
|
||||
|
||||
#define REG_A2XX_SQ_VS_PROGRAM 0x000021f7
|
||||
#define A2XX_SQ_VS_PROGRAM_BASE__MASK 0x00000fff
|
||||
#define A2XX_SQ_VS_PROGRAM_BASE__SHIFT 0
|
||||
static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_VS_PROGRAM_BASE__SHIFT) & A2XX_SQ_VS_PROGRAM_BASE__MASK;
|
||||
}
|
||||
#define A2XX_SQ_VS_PROGRAM_SIZE__MASK 0x00fff000
|
||||
#define A2XX_SQ_VS_PROGRAM_SIZE__SHIFT 12
|
||||
static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_VS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_VS_PROGRAM_SIZE__MASK;
|
||||
}
|
||||
|
||||
#define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9
|
||||
|
||||
|
|
@ -1304,6 +1517,14 @@ static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_a
|
|||
}
|
||||
|
||||
#define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293
|
||||
#define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ENA 0x00000001
|
||||
#define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK 0x0000007e
|
||||
#define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT 1
|
||||
static inline uint32_t A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT) & A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK;
|
||||
}
|
||||
#define A2XX_PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z 0x00000100
|
||||
|
||||
#define REG_A2XX_VGT_ENHANCE 0x00002294
|
||||
|
||||
|
|
@ -1319,6 +1540,18 @@ static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val)
|
|||
#define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400
|
||||
|
||||
#define REG_A2XX_PA_SC_AA_CONFIG 0x00002301
|
||||
#define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK 0x00000007
|
||||
#define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT 0
|
||||
static inline uint32_t A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT) & A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK;
|
||||
}
|
||||
#define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK 0x0001e000
|
||||
#define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT 13
|
||||
static inline uint32_t A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT) & A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK;
|
||||
}
|
||||
|
||||
#define REG_A2XX_PA_SU_VTX_CNTL 0x00002302
|
||||
#define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001
|
||||
|
|
@ -1407,8 +1640,20 @@ static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val)
|
|||
#define REG_A2XX_PA_SC_AA_MASK 0x00002312
|
||||
|
||||
#define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316
|
||||
#define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK 0x00000007
|
||||
#define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT 0
|
||||
static inline uint32_t A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT) & A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK;
|
||||
}
|
||||
|
||||
#define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317
|
||||
#define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK 0x00000003
|
||||
#define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT 0
|
||||
static inline uint32_t A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT) & A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK;
|
||||
}
|
||||
|
||||
#define REG_A2XX_RB_COPY_CONTROL 0x00002318
|
||||
#define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007
|
||||
|
|
|
|||
|
|
@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2016 by the following authors:
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@
|
|||
extern bool hang_debug;
|
||||
|
||||
static void a3xx_dump(struct msm_gpu *gpu);
|
||||
static bool a3xx_idle(struct msm_gpu *gpu);
|
||||
|
||||
static bool a3xx_me_init(struct msm_gpu *gpu)
|
||||
{
|
||||
|
|
@ -65,7 +66,7 @@ static bool a3xx_me_init(struct msm_gpu *gpu)
|
|||
OUT_RING(ring, 0x00000000);
|
||||
|
||||
gpu->funcs->flush(gpu);
|
||||
return gpu->funcs->idle(gpu);
|
||||
return a3xx_idle(gpu);
|
||||
}
|
||||
|
||||
static int a3xx_hw_init(struct msm_gpu *gpu)
|
||||
|
|
@ -446,7 +447,6 @@ static const struct adreno_gpu_funcs funcs = {
|
|||
.last_fence = adreno_last_fence,
|
||||
.submit = adreno_submit,
|
||||
.flush = adreno_flush,
|
||||
.idle = a3xx_idle,
|
||||
.irq = a3xx_irq,
|
||||
.destroy = a3xx_destroy,
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
|
|
|
|||
|
|
@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2016 by the following authors:
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
@ -3010,11 +3010,11 @@ static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
|
|||
static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; }
|
||||
|
||||
static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; }
|
||||
#define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xfffffff0
|
||||
#define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 4
|
||||
#define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xffffffff
|
||||
#define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 0
|
||||
static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val)
|
||||
{
|
||||
return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK;
|
||||
return ((val) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; }
|
||||
|
|
@ -3829,6 +3829,44 @@ static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
|
|||
|
||||
#define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_EN0 0x000030c0
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_EN1 0x000030c1
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_EN2 0x000030c2
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_EN3 0x000030c3
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_SEL0 0x000030d0
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_SEL1 0x000030d1
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_SEL2 0x000030d2
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_SEL3 0x000030d3
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_LOW0 0x000030d8
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_LOW1 0x000030d9
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_LOW2 0x000030da
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_LOW3 0x000030db
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_HIGH0 0x000030e0
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_HIGH1 0x000030e1
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_HIGH2 0x000030e2
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_HIGH3 0x000030e3
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
|
||||
|
||||
#define REG_A4XX_UNKNOWN_0CC5 0x00000cc5
|
||||
|
||||
#define REG_A4XX_UNKNOWN_0CC6 0x00000cc6
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@
|
|||
|
||||
extern bool hang_debug;
|
||||
static void a4xx_dump(struct msm_gpu *gpu);
|
||||
static bool a4xx_idle(struct msm_gpu *gpu);
|
||||
|
||||
/*
|
||||
* a4xx_enable_hwcg() - Program the clock control registers
|
||||
|
|
@ -137,7 +138,7 @@ static bool a4xx_me_init(struct msm_gpu *gpu)
|
|||
OUT_RING(ring, 0x00000000);
|
||||
|
||||
gpu->funcs->flush(gpu);
|
||||
return gpu->funcs->idle(gpu);
|
||||
return a4xx_idle(gpu);
|
||||
}
|
||||
|
||||
static int a4xx_hw_init(struct msm_gpu *gpu)
|
||||
|
|
@ -534,7 +535,6 @@ static const struct adreno_gpu_funcs funcs = {
|
|||
.last_fence = adreno_last_fence,
|
||||
.submit = adreno_submit,
|
||||
.flush = adreno_flush,
|
||||
.idle = a4xx_idle,
|
||||
.irq = a4xx_irq,
|
||||
.destroy = a4xx_destroy,
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -11,6 +11,12 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/cpumask.h>
|
||||
#include <linux/qcom_scm.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/of_reserved_mem.h>
|
||||
#include <linux/soc/qcom/mdt_loader.h>
|
||||
#include "msm_gem.h"
|
||||
#include "msm_mmu.h"
|
||||
#include "a5xx_gpu.h"
|
||||
|
|
@ -18,6 +24,62 @@
|
|||
extern bool hang_debug;
|
||||
static void a5xx_dump(struct msm_gpu *gpu);
|
||||
|
||||
#define GPU_PAS_ID 13
|
||||
|
||||
#if IS_ENABLED(CONFIG_QCOM_MDT_LOADER)
|
||||
|
||||
static int zap_shader_load_mdt(struct device *dev, const char *fwname)
|
||||
{
|
||||
const struct firmware *fw;
|
||||
phys_addr_t mem_phys;
|
||||
ssize_t mem_size;
|
||||
void *mem_region = NULL;
|
||||
int ret;
|
||||
|
||||
/* Request the MDT file for the firmware */
|
||||
ret = request_firmware(&fw, fwname, dev);
|
||||
if (ret) {
|
||||
DRM_DEV_ERROR(dev, "Unable to load %s\n", fwname);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Figure out how much memory we need */
|
||||
mem_size = qcom_mdt_get_size(fw);
|
||||
if (mem_size < 0) {
|
||||
ret = mem_size;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Allocate memory for the firmware image */
|
||||
mem_region = dmam_alloc_coherent(dev, mem_size, &mem_phys, GFP_KERNEL);
|
||||
if (!mem_region) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* Load the rest of the MDT */
|
||||
ret = qcom_mdt_load(dev, fw, fwname, GPU_PAS_ID, mem_region, mem_phys,
|
||||
mem_size);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
/* Send the image to the secure world */
|
||||
ret = qcom_scm_pas_auth_and_reset(GPU_PAS_ID);
|
||||
if (ret)
|
||||
DRM_DEV_ERROR(dev, "Unable to authorize the image\n");
|
||||
|
||||
out:
|
||||
release_firmware(fw);
|
||||
|
||||
return ret;
|
||||
}
|
||||
#else
|
||||
static int zap_shader_load_mdt(struct device *dev, const char *fwname)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
|
||||
struct msm_file_private *ctx)
|
||||
{
|
||||
|
|
@ -225,7 +287,7 @@ static int a5xx_me_init(struct msm_gpu *gpu)
|
|||
|
||||
gpu->funcs->flush(gpu);
|
||||
|
||||
return gpu->funcs->idle(gpu) ? 0 : -EINVAL;
|
||||
return a5xx_idle(gpu) ? 0 : -EINVAL;
|
||||
}
|
||||
|
||||
static struct drm_gem_object *a5xx_ucode_load_bo(struct msm_gpu *gpu,
|
||||
|
|
@ -235,24 +297,21 @@ static struct drm_gem_object *a5xx_ucode_load_bo(struct msm_gpu *gpu,
|
|||
struct drm_gem_object *bo;
|
||||
void *ptr;
|
||||
|
||||
mutex_lock(&drm->struct_mutex);
|
||||
bo = msm_gem_new(drm, fw->size - 4, MSM_BO_UNCACHED);
|
||||
mutex_unlock(&drm->struct_mutex);
|
||||
|
||||
bo = msm_gem_new_locked(drm, fw->size - 4, MSM_BO_UNCACHED);
|
||||
if (IS_ERR(bo))
|
||||
return bo;
|
||||
|
||||
ptr = msm_gem_get_vaddr(bo);
|
||||
if (!ptr) {
|
||||
drm_gem_object_unreference_unlocked(bo);
|
||||
drm_gem_object_unreference(bo);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
if (iova) {
|
||||
int ret = msm_gem_get_iova(bo, gpu->id, iova);
|
||||
int ret = msm_gem_get_iova(bo, gpu->aspace, iova);
|
||||
|
||||
if (ret) {
|
||||
drm_gem_object_unreference_unlocked(bo);
|
||||
drm_gem_object_unreference(bo);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
}
|
||||
|
|
@ -304,6 +363,98 @@ static int a5xx_ucode_init(struct msm_gpu *gpu)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#define SCM_GPU_ZAP_SHADER_RESUME 0
|
||||
|
||||
static int a5xx_zap_shader_resume(struct msm_gpu *gpu)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = qcom_scm_set_remote_state(SCM_GPU_ZAP_SHADER_RESUME, GPU_PAS_ID);
|
||||
if (ret)
|
||||
DRM_ERROR("%s: zap-shader resume failed: %d\n",
|
||||
gpu->name, ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Set up a child device to "own" the zap shader */
|
||||
static int a5xx_zap_shader_dev_init(struct device *parent, struct device *dev)
|
||||
{
|
||||
struct device_node *node;
|
||||
int ret;
|
||||
|
||||
if (dev->parent)
|
||||
return 0;
|
||||
|
||||
/* Find the sub-node for the zap shader */
|
||||
node = of_get_child_by_name(parent->of_node, "zap-shader");
|
||||
if (!node) {
|
||||
DRM_DEV_ERROR(parent, "zap-shader not found in device tree\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
dev->parent = parent;
|
||||
dev->of_node = node;
|
||||
dev_set_name(dev, "adreno_zap_shader");
|
||||
|
||||
ret = device_register(dev);
|
||||
if (ret) {
|
||||
DRM_DEV_ERROR(parent, "Couldn't register zap shader device\n");
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = of_reserved_mem_device_init(dev);
|
||||
if (ret) {
|
||||
DRM_DEV_ERROR(parent, "Unable to set up the reserved memory\n");
|
||||
device_unregister(dev);
|
||||
}
|
||||
|
||||
out:
|
||||
if (ret)
|
||||
dev->parent = NULL;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int a5xx_zap_shader_init(struct msm_gpu *gpu)
|
||||
{
|
||||
static bool loaded;
|
||||
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
|
||||
struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
|
||||
struct platform_device *pdev = a5xx_gpu->pdev;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* If the zap shader is already loaded into memory we just need to kick
|
||||
* the remote processor to reinitialize it
|
||||
*/
|
||||
if (loaded)
|
||||
return a5xx_zap_shader_resume(gpu);
|
||||
|
||||
/* We need SCM to be able to load the firmware */
|
||||
if (!qcom_scm_is_available()) {
|
||||
DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n");
|
||||
return -EPROBE_DEFER;
|
||||
}
|
||||
|
||||
/* Each GPU has a target specific zap shader firmware name to use */
|
||||
if (!adreno_gpu->info->zapfw) {
|
||||
DRM_DEV_ERROR(&pdev->dev,
|
||||
"Zap shader firmware file not specified for this target\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = a5xx_zap_shader_dev_init(&pdev->dev, &a5xx_gpu->zap_dev);
|
||||
|
||||
if (!ret)
|
||||
ret = zap_shader_load_mdt(&a5xx_gpu->zap_dev,
|
||||
adreno_gpu->info->zapfw);
|
||||
|
||||
loaded = !ret;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#define A5XX_INT_MASK (A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR | \
|
||||
A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT | \
|
||||
A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT | \
|
||||
|
|
@ -484,12 +635,31 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
|
|||
OUT_RING(gpu->rb, 0x0F);
|
||||
|
||||
gpu->funcs->flush(gpu);
|
||||
if (!gpu->funcs->idle(gpu))
|
||||
if (!a5xx_idle(gpu))
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Put the GPU into unsecure mode */
|
||||
gpu_write(gpu, REG_A5XX_RBBM_SECVID_TRUST_CNTL, 0x0);
|
||||
/*
|
||||
* Try to load a zap shader into the secure world. If successful
|
||||
* we can use the CP to switch out of secure mode. If not then we
|
||||
* have no resource but to try to switch ourselves out manually. If we
|
||||
* guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will
|
||||
* be blocked and a permissions violation will soon follow.
|
||||
*/
|
||||
ret = a5xx_zap_shader_init(gpu);
|
||||
if (!ret) {
|
||||
OUT_PKT7(gpu->rb, CP_SET_SECURE_MODE, 1);
|
||||
OUT_RING(gpu->rb, 0x00000000);
|
||||
|
||||
gpu->funcs->flush(gpu);
|
||||
if (!a5xx_idle(gpu))
|
||||
return -EINVAL;
|
||||
} else {
|
||||
/* Print a warning so if we die, we know why */
|
||||
dev_warn_once(gpu->dev->dev,
|
||||
"Zap shader not enabled - using SECVID_TRUST_CNTL instead\n");
|
||||
gpu_write(gpu, REG_A5XX_RBBM_SECVID_TRUST_CNTL, 0x0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -521,21 +691,24 @@ static void a5xx_destroy(struct msm_gpu *gpu)
|
|||
|
||||
DBG("%s", gpu->name);
|
||||
|
||||
if (a5xx_gpu->zap_dev.parent)
|
||||
device_unregister(&a5xx_gpu->zap_dev);
|
||||
|
||||
if (a5xx_gpu->pm4_bo) {
|
||||
if (a5xx_gpu->pm4_iova)
|
||||
msm_gem_put_iova(a5xx_gpu->pm4_bo, gpu->id);
|
||||
msm_gem_put_iova(a5xx_gpu->pm4_bo, gpu->aspace);
|
||||
drm_gem_object_unreference_unlocked(a5xx_gpu->pm4_bo);
|
||||
}
|
||||
|
||||
if (a5xx_gpu->pfp_bo) {
|
||||
if (a5xx_gpu->pfp_iova)
|
||||
msm_gem_put_iova(a5xx_gpu->pfp_bo, gpu->id);
|
||||
msm_gem_put_iova(a5xx_gpu->pfp_bo, gpu->aspace);
|
||||
drm_gem_object_unreference_unlocked(a5xx_gpu->pfp_bo);
|
||||
}
|
||||
|
||||
if (a5xx_gpu->gpmu_bo) {
|
||||
if (a5xx_gpu->gpmu_iova)
|
||||
msm_gem_put_iova(a5xx_gpu->gpmu_bo, gpu->id);
|
||||
msm_gem_put_iova(a5xx_gpu->gpmu_bo, gpu->aspace);
|
||||
drm_gem_object_unreference_unlocked(a5xx_gpu->gpmu_bo);
|
||||
}
|
||||
|
||||
|
|
@ -556,7 +729,7 @@ static inline bool _a5xx_check_idle(struct msm_gpu *gpu)
|
|||
A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT);
|
||||
}
|
||||
|
||||
static bool a5xx_idle(struct msm_gpu *gpu)
|
||||
bool a5xx_idle(struct msm_gpu *gpu)
|
||||
{
|
||||
/* wait for CP to drain ringbuffer: */
|
||||
if (!adreno_idle(gpu))
|
||||
|
|
@ -861,7 +1034,6 @@ static const struct adreno_gpu_funcs funcs = {
|
|||
.last_fence = adreno_last_fence,
|
||||
.submit = a5xx_submit,
|
||||
.flush = adreno_flush,
|
||||
.idle = a5xx_idle,
|
||||
.irq = a5xx_irq,
|
||||
.destroy = a5xx_destroy,
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
|
|
|
|||
|
|
@ -36,6 +36,8 @@ struct a5xx_gpu {
|
|||
uint32_t gpmu_dwords;
|
||||
|
||||
uint32_t lm_leakage;
|
||||
|
||||
struct device zap_dev;
|
||||
};
|
||||
|
||||
#define to_a5xx_gpu(x) container_of(x, struct a5xx_gpu, base)
|
||||
|
|
@ -56,5 +58,6 @@ static inline int spin_usecs(struct msm_gpu *gpu, uint32_t usecs,
|
|||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
bool a5xx_idle(struct msm_gpu *gpu);
|
||||
|
||||
#endif /* __A5XX_GPU_H__ */
|
||||
|
|
|
|||
|
|
@ -194,7 +194,7 @@ static int a5xx_gpmu_init(struct msm_gpu *gpu)
|
|||
|
||||
gpu->funcs->flush(gpu);
|
||||
|
||||
if (!gpu->funcs->idle(gpu)) {
|
||||
if (!a5xx_idle(gpu)) {
|
||||
DRM_ERROR("%s: Unable to load GPMU firmware. GPMU will not be active\n",
|
||||
gpu->name);
|
||||
return -EINVAL;
|
||||
|
|
@ -294,14 +294,12 @@ void a5xx_gpmu_ucode_init(struct msm_gpu *gpu)
|
|||
*/
|
||||
bosize = (cmds_size + (cmds_size / TYPE4_MAX_PAYLOAD) + 1) << 2;
|
||||
|
||||
mutex_lock(&drm->struct_mutex);
|
||||
a5xx_gpu->gpmu_bo = msm_gem_new(drm, bosize, MSM_BO_UNCACHED);
|
||||
mutex_unlock(&drm->struct_mutex);
|
||||
|
||||
a5xx_gpu->gpmu_bo = msm_gem_new_locked(drm, bosize, MSM_BO_UNCACHED);
|
||||
if (IS_ERR(a5xx_gpu->gpmu_bo))
|
||||
goto err;
|
||||
|
||||
if (msm_gem_get_iova(a5xx_gpu->gpmu_bo, gpu->id, &a5xx_gpu->gpmu_iova))
|
||||
if (msm_gem_get_iova(a5xx_gpu->gpmu_bo, gpu->aspace,
|
||||
&a5xx_gpu->gpmu_iova))
|
||||
goto err;
|
||||
|
||||
ptr = msm_gem_get_vaddr(a5xx_gpu->gpmu_bo);
|
||||
|
|
@ -330,9 +328,9 @@ void a5xx_gpmu_ucode_init(struct msm_gpu *gpu)
|
|||
|
||||
err:
|
||||
if (a5xx_gpu->gpmu_iova)
|
||||
msm_gem_put_iova(a5xx_gpu->gpmu_bo, gpu->id);
|
||||
msm_gem_put_iova(a5xx_gpu->gpmu_bo, gpu->aspace);
|
||||
if (a5xx_gpu->gpmu_bo)
|
||||
drm_gem_object_unreference_unlocked(a5xx_gpu->gpmu_bo);
|
||||
drm_gem_object_unreference(a5xx_gpu->gpmu_bo);
|
||||
|
||||
a5xx_gpu->gpmu_bo = NULL;
|
||||
a5xx_gpu->gpmu_iova = 0;
|
||||
|
|
|
|||
|
|
@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2016 by the following authors:
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
@ -421,6 +421,35 @@ static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
|
|||
#define REG_AXXX_CP_IB2_BUFSZ 0x0000045b
|
||||
|
||||
#define REG_AXXX_CP_STAT 0x0000047f
|
||||
#define AXXX_CP_STAT_CP_BUSY 0x80000000
|
||||
#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY 0x40000000
|
||||
#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY 0x20000000
|
||||
#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY 0x10000000
|
||||
#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY 0x08000000
|
||||
#define AXXX_CP_STAT_ME_BUSY 0x04000000
|
||||
#define AXXX_CP_STAT_MIU_WR_C_BUSY 0x02000000
|
||||
#define AXXX_CP_STAT_CP_3D_BUSY 0x00800000
|
||||
#define AXXX_CP_STAT_CP_NRT_BUSY 0x00400000
|
||||
#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY 0x00200000
|
||||
#define AXXX_CP_STAT_RCIU_ME_BUSY 0x00100000
|
||||
#define AXXX_CP_STAT_RCIU_PFP_BUSY 0x00080000
|
||||
#define AXXX_CP_STAT_MEQ_RING_BUSY 0x00040000
|
||||
#define AXXX_CP_STAT_PFP_BUSY 0x00020000
|
||||
#define AXXX_CP_STAT_ST_QUEUE_BUSY 0x00010000
|
||||
#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY 0x00002000
|
||||
#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY 0x00001000
|
||||
#define AXXX_CP_STAT_RING_QUEUE_BUSY 0x00000800
|
||||
#define AXXX_CP_STAT_CSF_BUSY 0x00000400
|
||||
#define AXXX_CP_STAT_CSF_ST_BUSY 0x00000200
|
||||
#define AXXX_CP_STAT_EVENT_BUSY 0x00000100
|
||||
#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY 0x00000080
|
||||
#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY 0x00000040
|
||||
#define AXXX_CP_STAT_CSF_RING_BUSY 0x00000020
|
||||
#define AXXX_CP_STAT_RCIU_BUSY 0x00000010
|
||||
#define AXXX_CP_STAT_RBIU_BUSY 0x00000008
|
||||
#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY 0x00000004
|
||||
#define AXXX_CP_STAT_MIU_RD_REQ_BUSY 0x00000002
|
||||
#define AXXX_CP_STAT_MIU_WR_BUSY 0x00000001
|
||||
|
||||
#define REG_AXXX_CP_SCRATCH_REG0 0x00000578
|
||||
|
||||
|
|
|
|||
|
|
@ -86,6 +86,7 @@ static const struct adreno_info gpulist[] = {
|
|||
ADRENO_QUIRK_FAULT_DETECT_MASK,
|
||||
.init = a5xx_gpu_init,
|
||||
.gpmufw = "a530v3_gpmu.fw2",
|
||||
.zapfw = "a530_zap.mdt",
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -158,7 +159,9 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
|
|||
int ret;
|
||||
|
||||
pm_runtime_get_sync(&pdev->dev);
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
ret = msm_gpu_hw_init(gpu);
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
pm_runtime_put_sync(&pdev->dev);
|
||||
if (ret) {
|
||||
dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ int adreno_hw_init(struct msm_gpu *gpu)
|
|||
|
||||
DBG("%s", gpu->name);
|
||||
|
||||
ret = msm_gem_get_iova(gpu->rb->bo, gpu->id, &gpu->rb_iova);
|
||||
ret = msm_gem_get_iova(gpu->rb->bo, gpu->aspace, &gpu->rb_iova);
|
||||
if (ret) {
|
||||
gpu->rb_iova = 0;
|
||||
dev_err(gpu->dev->dev, "could not map ringbuffer: %d\n", ret);
|
||||
|
|
@ -77,7 +77,6 @@ int adreno_hw_init(struct msm_gpu *gpu)
|
|||
/* reset completed fence seqno: */
|
||||
adreno_gpu->memptrs->fence = gpu->fctx->completed_fence;
|
||||
adreno_gpu->memptrs->rptr = 0;
|
||||
adreno_gpu->memptrs->wptr = 0;
|
||||
|
||||
/* Setup REG_CP_RB_CNTL: */
|
||||
adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
|
||||
|
|
@ -258,7 +257,6 @@ void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
|
|||
seq_printf(m, "fence: %d/%d\n", adreno_gpu->memptrs->fence,
|
||||
gpu->fctx->last_fence);
|
||||
seq_printf(m, "rptr: %d\n", get_rptr(adreno_gpu));
|
||||
seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr);
|
||||
seq_printf(m, "rb wptr: %d\n", get_wptr(gpu->rb));
|
||||
|
||||
/* dump these out in a form that can be parsed by demsm: */
|
||||
|
|
@ -294,7 +292,6 @@ void adreno_dump_info(struct msm_gpu *gpu)
|
|||
printk("fence: %d/%d\n", adreno_gpu->memptrs->fence,
|
||||
gpu->fctx->last_fence);
|
||||
printk("rptr: %d\n", get_rptr(adreno_gpu));
|
||||
printk("wptr: %d\n", adreno_gpu->memptrs->wptr);
|
||||
printk("rb wptr: %d\n", get_wptr(gpu->rb));
|
||||
}
|
||||
|
||||
|
|
@ -342,6 +339,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
|
|||
struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs)
|
||||
{
|
||||
struct adreno_platform_config *config = pdev->dev.platform_data;
|
||||
struct msm_gpu_config adreno_gpu_config = { 0 };
|
||||
struct msm_gpu *gpu = &adreno_gpu->base;
|
||||
int ret;
|
||||
|
||||
|
|
@ -360,9 +358,16 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
|
|||
DBG("fast_rate=%u, slow_rate=27000000, bus_freq=%u",
|
||||
gpu->fast_rate, gpu->bus_freq);
|
||||
|
||||
adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
|
||||
adreno_gpu_config.irqname = "kgsl_3d0_irq";
|
||||
|
||||
adreno_gpu_config.va_start = SZ_16M;
|
||||
adreno_gpu_config.va_end = 0xffffffff;
|
||||
|
||||
adreno_gpu_config.ringsz = RB_SIZE;
|
||||
|
||||
ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
|
||||
adreno_gpu->info->name, "kgsl_3d0_reg_memory", "kgsl_3d0_irq",
|
||||
RB_SIZE);
|
||||
adreno_gpu->info->name, &adreno_gpu_config);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -392,10 +397,8 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
|
|||
return ret;
|
||||
}
|
||||
|
||||
mutex_lock(&drm->struct_mutex);
|
||||
adreno_gpu->memptrs_bo = msm_gem_new(drm, sizeof(*adreno_gpu->memptrs),
|
||||
MSM_BO_UNCACHED);
|
||||
mutex_unlock(&drm->struct_mutex);
|
||||
if (IS_ERR(adreno_gpu->memptrs_bo)) {
|
||||
ret = PTR_ERR(adreno_gpu->memptrs_bo);
|
||||
adreno_gpu->memptrs_bo = NULL;
|
||||
|
|
@ -409,7 +412,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
|
|||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ret = msm_gem_get_iova(adreno_gpu->memptrs_bo, gpu->id,
|
||||
ret = msm_gem_get_iova(adreno_gpu->memptrs_bo, gpu->aspace,
|
||||
&adreno_gpu->memptrs_iova);
|
||||
if (ret) {
|
||||
dev_err(drm->dev, "could not map memptrs: %d\n", ret);
|
||||
|
|
@ -428,7 +431,7 @@ void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
|
|||
msm_gem_put_vaddr(adreno_gpu->memptrs_bo);
|
||||
|
||||
if (adreno_gpu->memptrs_iova)
|
||||
msm_gem_put_iova(adreno_gpu->memptrs_bo, gpu->id);
|
||||
msm_gem_put_iova(adreno_gpu->memptrs_bo, gpu->aspace);
|
||||
|
||||
drm_gem_object_unreference_unlocked(adreno_gpu->memptrs_bo);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -77,6 +77,7 @@ struct adreno_info {
|
|||
uint32_t gmem;
|
||||
enum adreno_quirks quirks;
|
||||
struct msm_gpu *(*init)(struct drm_device *dev);
|
||||
const char *zapfw;
|
||||
};
|
||||
|
||||
const struct adreno_info *adreno_info(struct adreno_rev rev);
|
||||
|
|
@ -86,7 +87,6 @@ const struct adreno_info *adreno_info(struct adreno_rev rev);
|
|||
|
||||
struct adreno_rbmemptrs {
|
||||
volatile uint32_t rptr;
|
||||
volatile uint32_t wptr;
|
||||
volatile uint32_t fence;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2016 by the following authors:
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
@ -67,10 +67,18 @@ enum vgt_event_type {
|
|||
PERFCOUNTER_STOP = 24,
|
||||
VS_FETCH_DONE = 27,
|
||||
FACENESS_FLUSH = 28,
|
||||
FLUSH_SO_0 = 17,
|
||||
FLUSH_SO_1 = 18,
|
||||
FLUSH_SO_2 = 19,
|
||||
FLUSH_SO_3 = 20,
|
||||
UNK_19 = 25,
|
||||
UNK_1C = 28,
|
||||
UNK_1D = 29,
|
||||
BLIT = 30,
|
||||
UNK_26 = 38,
|
||||
UNK_25 = 37,
|
||||
LRZ_FLUSH = 38,
|
||||
UNK_2C = 44,
|
||||
UNK_2D = 45,
|
||||
};
|
||||
|
||||
enum pc_di_primtype {
|
||||
|
|
@ -134,11 +142,13 @@ enum adreno_pm4_type3_packets {
|
|||
CP_WAIT_IB_PFD_COMPLETE = 93,
|
||||
CP_REG_RMW = 33,
|
||||
CP_SET_BIN_DATA = 47,
|
||||
CP_SET_BIN_DATA5 = 47,
|
||||
CP_REG_TO_MEM = 62,
|
||||
CP_MEM_WRITE = 61,
|
||||
CP_MEM_WRITE_CNTR = 79,
|
||||
CP_COND_EXEC = 68,
|
||||
CP_COND_WRITE = 69,
|
||||
CP_COND_WRITE5 = 69,
|
||||
CP_EVENT_WRITE = 70,
|
||||
CP_EVENT_WRITE_SHD = 88,
|
||||
CP_EVENT_WRITE_CFL = 89,
|
||||
|
|
@ -165,6 +175,7 @@ enum adreno_pm4_type3_packets {
|
|||
CP_SET_PROTECTED_MODE = 95,
|
||||
CP_BOOTSTRAP_UCODE = 111,
|
||||
CP_LOAD_STATE = 48,
|
||||
CP_LOAD_STATE4 = 48,
|
||||
CP_COND_INDIRECT_BUFFER_PFE = 58,
|
||||
CP_COND_INDIRECT_BUFFER_PFD = 50,
|
||||
CP_INDIRECT_BUFFER_PFE = 63,
|
||||
|
|
@ -204,6 +215,7 @@ enum adreno_pm4_type3_packets {
|
|||
CP_COMPUTE_CHECKPOINT = 110,
|
||||
CP_MEM_TO_MEM = 115,
|
||||
CP_BLIT = 44,
|
||||
CP_UNK_39 = 57,
|
||||
IN_IB_PREFETCH_END = 23,
|
||||
IN_SUBBLK_PREFETCH = 31,
|
||||
IN_INSTR_PREFETCH = 32,
|
||||
|
|
@ -239,21 +251,61 @@ enum adreno_state_src {
|
|||
SS_INDIRECT_STM = 6,
|
||||
};
|
||||
|
||||
enum a4xx_state_block {
|
||||
SB4_VS_TEX = 0,
|
||||
SB4_HS_TEX = 1,
|
||||
SB4_DS_TEX = 2,
|
||||
SB4_GS_TEX = 3,
|
||||
SB4_FS_TEX = 4,
|
||||
SB4_CS_TEX = 5,
|
||||
SB4_VS_SHADER = 8,
|
||||
SB4_HS_SHADER = 9,
|
||||
SB4_DS_SHADER = 10,
|
||||
SB4_GS_SHADER = 11,
|
||||
SB4_FS_SHADER = 12,
|
||||
SB4_CS_SHADER = 13,
|
||||
SB4_SSBO = 14,
|
||||
SB4_CS_SSBO = 15,
|
||||
};
|
||||
|
||||
enum a4xx_state_type {
|
||||
ST4_SHADER = 0,
|
||||
ST4_CONSTANTS = 1,
|
||||
};
|
||||
|
||||
enum a4xx_state_src {
|
||||
SS4_DIRECT = 0,
|
||||
SS4_INDIRECT = 2,
|
||||
};
|
||||
|
||||
enum a4xx_index_size {
|
||||
INDEX4_SIZE_8_BIT = 0,
|
||||
INDEX4_SIZE_16_BIT = 1,
|
||||
INDEX4_SIZE_32_BIT = 2,
|
||||
};
|
||||
|
||||
enum cp_cond_function {
|
||||
WRITE_ALWAYS = 0,
|
||||
WRITE_LT = 1,
|
||||
WRITE_LE = 2,
|
||||
WRITE_EQ = 3,
|
||||
WRITE_NE = 4,
|
||||
WRITE_GE = 5,
|
||||
WRITE_GT = 6,
|
||||
};
|
||||
|
||||
enum render_mode_cmd {
|
||||
BYPASS = 1,
|
||||
BINNING = 2,
|
||||
GMEM = 3,
|
||||
BLIT2D = 5,
|
||||
BLIT2DSCALE = 7,
|
||||
};
|
||||
|
||||
enum cp_blit_cmd {
|
||||
BLIT_OP_FILL = 0,
|
||||
BLIT_OP_BLIT = 1,
|
||||
BLIT_OP_COPY = 1,
|
||||
BLIT_OP_SCALE = 3,
|
||||
};
|
||||
|
||||
#define REG_CP_LOAD_STATE_0 0x00000000
|
||||
|
|
@ -296,12 +348,52 @@ static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
|
|||
return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_LOAD_STATE_2 0x00000002
|
||||
#define CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
|
||||
#define CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__SHIFT 0
|
||||
static inline uint32_t CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(uint32_t val)
|
||||
#define REG_CP_LOAD_STATE4_0 0x00000000
|
||||
#define CP_LOAD_STATE4_0_DST_OFF__MASK 0x0000ffff
|
||||
#define CP_LOAD_STATE4_0_DST_OFF__SHIFT 0
|
||||
static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__MASK;
|
||||
return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK;
|
||||
}
|
||||
#define CP_LOAD_STATE4_0_STATE_SRC__MASK 0x00030000
|
||||
#define CP_LOAD_STATE4_0_STATE_SRC__SHIFT 16
|
||||
static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)
|
||||
{
|
||||
return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK;
|
||||
}
|
||||
#define CP_LOAD_STATE4_0_STATE_BLOCK__MASK 0x003c0000
|
||||
#define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT 18
|
||||
static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)
|
||||
{
|
||||
return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK;
|
||||
}
|
||||
#define CP_LOAD_STATE4_0_NUM_UNIT__MASK 0xffc00000
|
||||
#define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT 22
|
||||
static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_LOAD_STATE4_1 0x00000001
|
||||
#define CP_LOAD_STATE4_1_STATE_TYPE__MASK 0x00000003
|
||||
#define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT 0
|
||||
static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)
|
||||
{
|
||||
return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK;
|
||||
}
|
||||
#define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK 0xfffffffc
|
||||
#define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT 2
|
||||
static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)
|
||||
{
|
||||
return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_LOAD_STATE4_2 0x00000002
|
||||
#define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
|
||||
#define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT 0
|
||||
static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DRAW_INDX_0 0x00000000
|
||||
|
|
@ -570,6 +662,52 @@ static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
|
|||
return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_DATA5_0 0x00000000
|
||||
#define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK 0x003f0000
|
||||
#define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT 16
|
||||
static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;
|
||||
}
|
||||
#define CP_SET_BIN_DATA5_0_VSC_N__MASK 0x07c00000
|
||||
#define CP_SET_BIN_DATA5_0_VSC_N__SHIFT 22
|
||||
static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_DATA5_1 0x00000001
|
||||
#define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK 0xffffffff
|
||||
#define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT 0
|
||||
static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_DATA5_2 0x00000002
|
||||
#define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK 0xffffffff
|
||||
#define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT 0
|
||||
static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_DATA5_3 0x00000003
|
||||
#define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK 0xffffffff
|
||||
#define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT 0
|
||||
static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_DATA5_4 0x00000004
|
||||
#define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK 0xffffffff
|
||||
#define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT 0
|
||||
static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_REG_TO_MEM_0 0x00000000
|
||||
#define CP_REG_TO_MEM_0_REG__MASK 0x0000ffff
|
||||
#define CP_REG_TO_MEM_0_REG__SHIFT 0
|
||||
|
|
@ -594,6 +732,128 @@ static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
|
|||
return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_MEM_TO_MEM_0 0x00000000
|
||||
#define CP_MEM_TO_MEM_0_NEG_A 0x00000001
|
||||
#define CP_MEM_TO_MEM_0_NEG_B 0x00000002
|
||||
#define CP_MEM_TO_MEM_0_NEG_C 0x00000004
|
||||
#define CP_MEM_TO_MEM_0_DOUBLE 0x20000000
|
||||
|
||||
#define REG_CP_COND_WRITE_0 0x00000000
|
||||
#define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007
|
||||
#define CP_COND_WRITE_0_FUNCTION__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;
|
||||
}
|
||||
#define CP_COND_WRITE_0_POLL_MEMORY 0x00000010
|
||||
#define CP_COND_WRITE_0_WRITE_MEMORY 0x00000100
|
||||
|
||||
#define REG_CP_COND_WRITE_1 0x00000001
|
||||
#define CP_COND_WRITE_1_POLL_ADDR__MASK 0xffffffff
|
||||
#define CP_COND_WRITE_1_POLL_ADDR__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE_2 0x00000002
|
||||
#define CP_COND_WRITE_2_REF__MASK 0xffffffff
|
||||
#define CP_COND_WRITE_2_REF__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE_3 0x00000003
|
||||
#define CP_COND_WRITE_3_MASK__MASK 0xffffffff
|
||||
#define CP_COND_WRITE_3_MASK__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE_4 0x00000004
|
||||
#define CP_COND_WRITE_4_WRITE_ADDR__MASK 0xffffffff
|
||||
#define CP_COND_WRITE_4_WRITE_ADDR__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE_5 0x00000005
|
||||
#define CP_COND_WRITE_5_WRITE_DATA__MASK 0xffffffff
|
||||
#define CP_COND_WRITE_5_WRITE_DATA__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE5_0 0x00000000
|
||||
#define CP_COND_WRITE5_0_FUNCTION__MASK 0x00000007
|
||||
#define CP_COND_WRITE5_0_FUNCTION__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
|
||||
}
|
||||
#define CP_COND_WRITE5_0_POLL_MEMORY 0x00000010
|
||||
#define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100
|
||||
|
||||
#define REG_CP_COND_WRITE5_1 0x00000001
|
||||
#define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK 0xffffffff
|
||||
#define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE5_2 0x00000002
|
||||
#define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK 0xffffffff
|
||||
#define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE5_3 0x00000003
|
||||
#define CP_COND_WRITE5_3_REF__MASK 0xffffffff
|
||||
#define CP_COND_WRITE5_3_REF__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE5_4 0x00000004
|
||||
#define CP_COND_WRITE5_4_MASK__MASK 0xffffffff
|
||||
#define CP_COND_WRITE5_4_MASK__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE5_5 0x00000005
|
||||
#define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK 0xffffffff
|
||||
#define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE5_6 0x00000006
|
||||
#define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK 0xffffffff
|
||||
#define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE5_7 0x00000007
|
||||
#define CP_COND_WRITE5_7_WRITE_DATA__MASK 0xffffffff
|
||||
#define CP_COND_WRITE5_7_WRITE_DATA__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DISPATCH_COMPUTE_0 0x00000000
|
||||
|
||||
#define REG_CP_DISPATCH_COMPUTE_1 0x00000001
|
||||
|
|
@ -645,6 +905,7 @@ static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_CP_SET_RENDER_MODE_3 0x00000003
|
||||
#define CP_SET_RENDER_MODE_3_VSC_ENABLE 0x00000008
|
||||
#define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010
|
||||
|
||||
#define REG_CP_SET_RENDER_MODE_4 0x00000004
|
||||
|
|
@ -673,6 +934,50 @@ static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
|
|||
return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COMPUTE_CHECKPOINT_0 0x00000000
|
||||
#define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK 0xffffffff
|
||||
#define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT 0
|
||||
static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COMPUTE_CHECKPOINT_1 0x00000001
|
||||
#define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK 0xffffffff
|
||||
#define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT 0
|
||||
static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002
|
||||
|
||||
#define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003
|
||||
|
||||
#define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004
|
||||
#define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK 0xffffffff
|
||||
#define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT 0
|
||||
static inline uint32_t CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005
|
||||
#define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff
|
||||
#define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT 0
|
||||
static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COMPUTE_CHECKPOINT_6 0x00000006
|
||||
#define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK 0xffffffff
|
||||
#define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT 0
|
||||
static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_PERFCOUNTER_ACTION_0 0x00000000
|
||||
|
||||
#define REG_CP_PERFCOUNTER_ACTION_1 0x00000001
|
||||
|
|
@ -698,6 +1003,7 @@ static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
|
|||
{
|
||||
return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
|
||||
}
|
||||
#define CP_EVENT_WRITE_0_TIMESTAMP 0x40000000
|
||||
|
||||
#define REG_CP_EVENT_WRITE_1 0x00000001
|
||||
#define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff
|
||||
|
|
@ -781,5 +1087,31 @@ static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
|
|||
return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_EXEC_CS_0 0x00000000
|
||||
|
||||
#define REG_CP_EXEC_CS_1 0x00000001
|
||||
#define CP_EXEC_CS_1_NGROUPS_X__MASK 0xffffffff
|
||||
#define CP_EXEC_CS_1_NGROUPS_X__SHIFT 0
|
||||
static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_EXEC_CS_2 0x00000002
|
||||
#define CP_EXEC_CS_2_NGROUPS_Y__MASK 0xffffffff
|
||||
#define CP_EXEC_CS_2_NGROUPS_Y__SHIFT 0
|
||||
static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_EXEC_CS_3 0x00000003
|
||||
#define CP_EXEC_CS_3_NGROUPS_Z__MASK 0xffffffff
|
||||
#define CP_EXEC_CS_3_NGROUPS_Z__SHIFT 0
|
||||
static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;
|
||||
}
|
||||
|
||||
|
||||
#endif /* ADRENO_PM4_XML */
|
||||
|
|
|
|||
|
|
@ -8,8 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /local/mnt/workspace/source_trees/envytools/rnndb/../rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-01-11 05:19:19)
|
||||
- /local/mnt/workspace/source_trees/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-05-09 06:32:54)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
#include "dsi.xml.h"
|
||||
#include "sfpb.xml.h"
|
||||
#include "dsi_cfg.h"
|
||||
#include "msm_kms.h"
|
||||
|
||||
static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
|
||||
{
|
||||
|
|
@ -975,23 +976,23 @@ static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
|
|||
static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, int size)
|
||||
{
|
||||
struct drm_device *dev = msm_host->dev;
|
||||
struct msm_drm_private *priv = dev->dev_private;
|
||||
const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
|
||||
int ret;
|
||||
uint64_t iova;
|
||||
|
||||
if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
msm_host->tx_gem_obj = msm_gem_new(dev, size, MSM_BO_UNCACHED);
|
||||
if (IS_ERR(msm_host->tx_gem_obj)) {
|
||||
ret = PTR_ERR(msm_host->tx_gem_obj);
|
||||
pr_err("%s: failed to allocate gem, %d\n",
|
||||
__func__, ret);
|
||||
msm_host->tx_gem_obj = NULL;
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = msm_gem_get_iova_locked(msm_host->tx_gem_obj, 0, &iova);
|
||||
ret = msm_gem_get_iova(msm_host->tx_gem_obj,
|
||||
priv->kms->aspace, &iova);
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
if (ret) {
|
||||
pr_err("%s: failed to get iova, %d\n", __func__, ret);
|
||||
|
|
@ -1141,12 +1142,15 @@ static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
|
|||
static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
|
||||
{
|
||||
const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
|
||||
struct drm_device *dev = msm_host->dev;
|
||||
struct msm_drm_private *priv = dev->dev_private;
|
||||
int ret;
|
||||
uint64_t dma_base;
|
||||
bool triggered;
|
||||
|
||||
if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {
|
||||
ret = msm_gem_get_iova(msm_host->tx_gem_obj, 0, &dma_base);
|
||||
ret = msm_gem_get_iova(msm_host->tx_gem_obj,
|
||||
priv->kms->aspace, &dma_base);
|
||||
if (ret) {
|
||||
pr_err("%s: failed to get iova: %d\n", __func__, ret);
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -8,19 +8,19 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
|
|
@ -8,19 +8,19 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
|
|
@ -8,19 +8,19 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
|
|
@ -8,19 +8,19 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2016 by the following authors:
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
@ -111,6 +111,32 @@ static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val)
|
|||
#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE 0x00000040
|
||||
#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE 0x00000080
|
||||
|
||||
#define REG_HDMI_INFOFRAME_CTRL1 0x00000030
|
||||
#define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK 0x0000003f
|
||||
#define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT 0
|
||||
static inline uint32_t HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(uint32_t val)
|
||||
{
|
||||
return ((val) << HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK;
|
||||
}
|
||||
#define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK 0x00003f00
|
||||
#define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT 8
|
||||
static inline uint32_t HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE(uint32_t val)
|
||||
{
|
||||
return ((val) << HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK;
|
||||
}
|
||||
#define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK 0x003f0000
|
||||
#define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT 16
|
||||
static inline uint32_t HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE(uint32_t val)
|
||||
{
|
||||
return ((val) << HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK;
|
||||
}
|
||||
#define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK 0x3f000000
|
||||
#define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT 24
|
||||
static inline uint32_t HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE(uint32_t val)
|
||||
{
|
||||
return ((val) << HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK;
|
||||
}
|
||||
|
||||
#define REG_HDMI_GEN_PKT_CTRL 0x00000034
|
||||
#define HDMI_GEN_PKT_CTRL_GENERIC0_SEND 0x00000001
|
||||
#define HDMI_GEN_PKT_CTRL_GENERIC0_CONT 0x00000002
|
||||
|
|
@ -463,7 +489,7 @@ static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val)
|
|||
#define REG_HDMI_CEC_RD_FILTER 0x000002b0
|
||||
|
||||
#define REG_HDMI_ACTIVE_HSYNC 0x000002b4
|
||||
#define HDMI_ACTIVE_HSYNC_START__MASK 0x00000fff
|
||||
#define HDMI_ACTIVE_HSYNC_START__MASK 0x00001fff
|
||||
#define HDMI_ACTIVE_HSYNC_START__SHIFT 0
|
||||
static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val)
|
||||
{
|
||||
|
|
@ -477,13 +503,13 @@ static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_HDMI_ACTIVE_VSYNC 0x000002b8
|
||||
#define HDMI_ACTIVE_VSYNC_START__MASK 0x00000fff
|
||||
#define HDMI_ACTIVE_VSYNC_START__MASK 0x00001fff
|
||||
#define HDMI_ACTIVE_VSYNC_START__SHIFT 0
|
||||
static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val)
|
||||
{
|
||||
return ((val) << HDMI_ACTIVE_VSYNC_START__SHIFT) & HDMI_ACTIVE_VSYNC_START__MASK;
|
||||
}
|
||||
#define HDMI_ACTIVE_VSYNC_END__MASK 0x0fff0000
|
||||
#define HDMI_ACTIVE_VSYNC_END__MASK 0x1fff0000
|
||||
#define HDMI_ACTIVE_VSYNC_END__SHIFT 16
|
||||
static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val)
|
||||
{
|
||||
|
|
@ -491,13 +517,13 @@ static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_HDMI_VSYNC_ACTIVE_F2 0x000002bc
|
||||
#define HDMI_VSYNC_ACTIVE_F2_START__MASK 0x00000fff
|
||||
#define HDMI_VSYNC_ACTIVE_F2_START__MASK 0x00001fff
|
||||
#define HDMI_VSYNC_ACTIVE_F2_START__SHIFT 0
|
||||
static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val)
|
||||
{
|
||||
return ((val) << HDMI_VSYNC_ACTIVE_F2_START__SHIFT) & HDMI_VSYNC_ACTIVE_F2_START__MASK;
|
||||
}
|
||||
#define HDMI_VSYNC_ACTIVE_F2_END__MASK 0x0fff0000
|
||||
#define HDMI_VSYNC_ACTIVE_F2_END__MASK 0x1fff0000
|
||||
#define HDMI_VSYNC_ACTIVE_F2_END__SHIFT 16
|
||||
static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val)
|
||||
{
|
||||
|
|
@ -505,13 +531,13 @@ static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_HDMI_TOTAL 0x000002c0
|
||||
#define HDMI_TOTAL_H_TOTAL__MASK 0x00000fff
|
||||
#define HDMI_TOTAL_H_TOTAL__MASK 0x00001fff
|
||||
#define HDMI_TOTAL_H_TOTAL__SHIFT 0
|
||||
static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val)
|
||||
{
|
||||
return ((val) << HDMI_TOTAL_H_TOTAL__SHIFT) & HDMI_TOTAL_H_TOTAL__MASK;
|
||||
}
|
||||
#define HDMI_TOTAL_V_TOTAL__MASK 0x0fff0000
|
||||
#define HDMI_TOTAL_V_TOTAL__MASK 0x1fff0000
|
||||
#define HDMI_TOTAL_V_TOTAL__SHIFT 16
|
||||
static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val)
|
||||
{
|
||||
|
|
@ -519,7 +545,7 @@ static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val)
|
|||
}
|
||||
|
||||
#define REG_HDMI_VSYNC_TOTAL_F2 0x000002c4
|
||||
#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK 0x00000fff
|
||||
#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK 0x00001fff
|
||||
#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT 0
|
||||
static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -175,10 +175,10 @@ int msm_hdmi_audio_update(struct hdmi *hdmi)
|
|||
/* configure infoframe: */
|
||||
hdmi_audio_infoframe_pack(info, buf, sizeof(buf));
|
||||
hdmi_write(hdmi, REG_HDMI_AUDIO_INFO0,
|
||||
(buf[3] << 0) || (buf[4] << 8) ||
|
||||
(buf[5] << 16) || (buf[6] << 24));
|
||||
(buf[3] << 0) | (buf[4] << 8) |
|
||||
(buf[5] << 16) | (buf[6] << 24));
|
||||
hdmi_write(hdmi, REG_HDMI_AUDIO_INFO1,
|
||||
(buf[7] << 0) || (buf[8] << 8));
|
||||
(buf[7] << 0) | (buf[8] << 8));
|
||||
|
||||
hdmi_write(hdmi, REG_HDMI_GC, 0);
|
||||
|
||||
|
|
|
|||
|
|
@ -86,6 +86,65 @@ static void power_off(struct drm_bridge *bridge)
|
|||
}
|
||||
}
|
||||
|
||||
#define AVI_IFRAME_LINE_NUMBER 1
|
||||
|
||||
static void msm_hdmi_config_avi_infoframe(struct hdmi *hdmi)
|
||||
{
|
||||
struct drm_crtc *crtc = hdmi->encoder->crtc;
|
||||
const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
|
||||
union hdmi_infoframe frame;
|
||||
u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
|
||||
u32 val;
|
||||
int len;
|
||||
|
||||
drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode);
|
||||
|
||||
len = hdmi_infoframe_pack(&frame, buffer, sizeof(buffer));
|
||||
if (len < 0) {
|
||||
dev_err(&hdmi->pdev->dev,
|
||||
"failed to configure avi infoframe\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* the AVI_INFOx registers don't map exactly to how the AVI infoframes
|
||||
* are packed according to the spec. The checksum from the header is
|
||||
* written to the LSB byte of AVI_INFO0 and the version is written to
|
||||
* the third byte from the LSB of AVI_INFO3
|
||||
*/
|
||||
hdmi_write(hdmi, REG_HDMI_AVI_INFO(0),
|
||||
buffer[3] |
|
||||
buffer[4] << 8 |
|
||||
buffer[5] << 16 |
|
||||
buffer[6] << 24);
|
||||
|
||||
hdmi_write(hdmi, REG_HDMI_AVI_INFO(1),
|
||||
buffer[7] |
|
||||
buffer[8] << 8 |
|
||||
buffer[9] << 16 |
|
||||
buffer[10] << 24);
|
||||
|
||||
hdmi_write(hdmi, REG_HDMI_AVI_INFO(2),
|
||||
buffer[11] |
|
||||
buffer[12] << 8 |
|
||||
buffer[13] << 16 |
|
||||
buffer[14] << 24);
|
||||
|
||||
hdmi_write(hdmi, REG_HDMI_AVI_INFO(3),
|
||||
buffer[15] |
|
||||
buffer[16] << 8 |
|
||||
buffer[1] << 24);
|
||||
|
||||
hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL0,
|
||||
HDMI_INFOFRAME_CTRL0_AVI_SEND |
|
||||
HDMI_INFOFRAME_CTRL0_AVI_CONT);
|
||||
|
||||
val = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL1);
|
||||
val &= ~HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK;
|
||||
val |= HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(AVI_IFRAME_LINE_NUMBER);
|
||||
hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL1, val);
|
||||
}
|
||||
|
||||
static void msm_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
|
||||
{
|
||||
struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
|
||||
|
|
@ -98,7 +157,10 @@ static void msm_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
|
|||
msm_hdmi_phy_resource_enable(phy);
|
||||
msm_hdmi_power_on(bridge);
|
||||
hdmi->power_on = true;
|
||||
msm_hdmi_audio_update(hdmi);
|
||||
if (hdmi->hdmi_mode) {
|
||||
msm_hdmi_config_avi_infoframe(hdmi);
|
||||
msm_hdmi_audio_update(hdmi);
|
||||
}
|
||||
}
|
||||
|
||||
msm_hdmi_phy_powerup(phy, hdmi->pixclock);
|
||||
|
|
@ -134,7 +196,8 @@ static void msm_hdmi_bridge_post_disable(struct drm_bridge *bridge)
|
|||
if (hdmi->power_on) {
|
||||
power_off(bridge);
|
||||
hdmi->power_on = false;
|
||||
msm_hdmi_audio_update(hdmi);
|
||||
if (hdmi->hdmi_mode)
|
||||
msm_hdmi_audio_update(hdmi);
|
||||
msm_hdmi_phy_resource_disable(phy);
|
||||
}
|
||||
}
|
||||
|
|
@ -196,7 +259,8 @@ static void msm_hdmi_bridge_mode_set(struct drm_bridge *bridge,
|
|||
DBG("frame_ctrl=%08x", frame_ctrl);
|
||||
hdmi_write(hdmi, REG_HDMI_FRAME_CTRL, frame_ctrl);
|
||||
|
||||
msm_hdmi_audio_update(hdmi);
|
||||
if (hdmi->hdmi_mode)
|
||||
msm_hdmi_audio_update(hdmi);
|
||||
}
|
||||
|
||||
static const struct drm_bridge_funcs msm_hdmi_bridge_funcs = {
|
||||
|
|
|
|||
|
|
@ -670,6 +670,11 @@ static unsigned long hdmi_8996_pll_recalc_rate(struct clk_hw *hw,
|
|||
|
||||
static void hdmi_8996_pll_unprepare(struct clk_hw *hw)
|
||||
{
|
||||
struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw);
|
||||
struct hdmi_phy *phy = pll_get_phy(pll);
|
||||
|
||||
hdmi_phy_write(phy, REG_HDMI_8996_PHY_CFG, 0x6);
|
||||
usleep_range(100, 150);
|
||||
}
|
||||
|
||||
static int hdmi_8996_pll_is_enabled(struct clk_hw *hw)
|
||||
|
|
|
|||
|
|
@ -8,19 +8,19 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
|
|
@ -8,19 +8,19 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
|
|
@ -126,8 +126,9 @@ static void unref_cursor_worker(struct drm_flip_work *work, void *val)
|
|||
struct mdp4_crtc *mdp4_crtc =
|
||||
container_of(work, struct mdp4_crtc, unref_cursor_work);
|
||||
struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base);
|
||||
struct msm_kms *kms = &mdp4_kms->base.base;
|
||||
|
||||
msm_gem_put_iova(val, mdp4_kms->id);
|
||||
msm_gem_put_iova(val, kms->aspace);
|
||||
drm_gem_object_unreference_unlocked(val);
|
||||
}
|
||||
|
||||
|
|
@ -360,6 +361,7 @@ static void update_cursor(struct drm_crtc *crtc)
|
|||
{
|
||||
struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
|
||||
struct mdp4_kms *mdp4_kms = get_kms(crtc);
|
||||
struct msm_kms *kms = &mdp4_kms->base.base;
|
||||
enum mdp4_dma dma = mdp4_crtc->dma;
|
||||
unsigned long flags;
|
||||
|
||||
|
|
@ -372,7 +374,7 @@ static void update_cursor(struct drm_crtc *crtc)
|
|||
if (next_bo) {
|
||||
/* take a obj ref + iova ref when we start scanning out: */
|
||||
drm_gem_object_reference(next_bo);
|
||||
msm_gem_get_iova_locked(next_bo, mdp4_kms->id, &iova);
|
||||
msm_gem_get_iova(next_bo, kms->aspace, &iova);
|
||||
|
||||
/* enable cursor: */
|
||||
mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma),
|
||||
|
|
@ -409,6 +411,7 @@ static int mdp4_crtc_cursor_set(struct drm_crtc *crtc,
|
|||
{
|
||||
struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
|
||||
struct mdp4_kms *mdp4_kms = get_kms(crtc);
|
||||
struct msm_kms *kms = &mdp4_kms->base.base;
|
||||
struct drm_device *dev = crtc->dev;
|
||||
struct drm_gem_object *cursor_bo, *old_bo;
|
||||
unsigned long flags;
|
||||
|
|
@ -429,7 +432,7 @@ static int mdp4_crtc_cursor_set(struct drm_crtc *crtc,
|
|||
}
|
||||
|
||||
if (cursor_bo) {
|
||||
ret = msm_gem_get_iova(cursor_bo, mdp4_kms->id, &iova);
|
||||
ret = msm_gem_get_iova(cursor_bo, kms->aspace, &iova);
|
||||
if (ret)
|
||||
goto fail;
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -160,10 +160,10 @@ static void mdp4_destroy(struct msm_kms *kms)
|
|||
{
|
||||
struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
|
||||
struct device *dev = mdp4_kms->dev->dev;
|
||||
struct msm_gem_address_space *aspace = mdp4_kms->aspace;
|
||||
struct msm_gem_address_space *aspace = kms->aspace;
|
||||
|
||||
if (mdp4_kms->blank_cursor_iova)
|
||||
msm_gem_put_iova(mdp4_kms->blank_cursor_bo, mdp4_kms->id);
|
||||
msm_gem_put_iova(mdp4_kms->blank_cursor_bo, kms->aspace);
|
||||
drm_gem_object_unreference_unlocked(mdp4_kms->blank_cursor_bo);
|
||||
|
||||
if (aspace) {
|
||||
|
|
@ -510,7 +510,7 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev)
|
|||
goto fail;
|
||||
}
|
||||
|
||||
mdp4_kms->aspace = aspace;
|
||||
kms->aspace = aspace;
|
||||
|
||||
ret = aspace->mmu->funcs->attach(aspace->mmu, iommu_ports,
|
||||
ARRAY_SIZE(iommu_ports));
|
||||
|
|
@ -522,22 +522,13 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev)
|
|||
aspace = NULL;
|
||||
}
|
||||
|
||||
mdp4_kms->id = msm_register_address_space(dev, aspace);
|
||||
if (mdp4_kms->id < 0) {
|
||||
ret = mdp4_kms->id;
|
||||
dev_err(dev->dev, "failed to register mdp4 iommu: %d\n", ret);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
ret = modeset_init(mdp4_kms);
|
||||
if (ret) {
|
||||
dev_err(dev->dev, "modeset_init failed: %d\n", ret);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC);
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
if (IS_ERR(mdp4_kms->blank_cursor_bo)) {
|
||||
ret = PTR_ERR(mdp4_kms->blank_cursor_bo);
|
||||
dev_err(dev->dev, "could not allocate blank-cursor bo: %d\n", ret);
|
||||
|
|
@ -545,7 +536,7 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev)
|
|||
goto fail;
|
||||
}
|
||||
|
||||
ret = msm_gem_get_iova(mdp4_kms->blank_cursor_bo, mdp4_kms->id,
|
||||
ret = msm_gem_get_iova(mdp4_kms->blank_cursor_bo, kms->aspace,
|
||||
&mdp4_kms->blank_cursor_iova);
|
||||
if (ret) {
|
||||
dev_err(dev->dev, "could not pin blank-cursor bo: %d\n", ret);
|
||||
|
|
|
|||
|
|
@ -34,9 +34,6 @@ struct mdp4_kms {
|
|||
|
||||
int rev;
|
||||
|
||||
/* mapper-id used to request GEM buffer mapped for scanout: */
|
||||
int id;
|
||||
|
||||
void __iomem *mmio;
|
||||
|
||||
struct regulator *vdd;
|
||||
|
|
@ -45,7 +42,6 @@ struct mdp4_kms {
|
|||
struct clk *pclk;
|
||||
struct clk *lut_clk;
|
||||
struct clk *axi_clk;
|
||||
struct msm_gem_address_space *aspace;
|
||||
|
||||
struct mdp_irq error_handler;
|
||||
|
||||
|
|
|
|||
|
|
@ -103,13 +103,14 @@ static int mdp4_plane_prepare_fb(struct drm_plane *plane,
|
|||
{
|
||||
struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
|
||||
struct mdp4_kms *mdp4_kms = get_kms(plane);
|
||||
struct msm_kms *kms = &mdp4_kms->base.base;
|
||||
struct drm_framebuffer *fb = new_state->fb;
|
||||
|
||||
if (!fb)
|
||||
return 0;
|
||||
|
||||
DBG("%s: prepare: FB[%u]", mdp4_plane->name, fb->base.id);
|
||||
return msm_framebuffer_prepare(fb, mdp4_kms->id);
|
||||
return msm_framebuffer_prepare(fb, kms->aspace);
|
||||
}
|
||||
|
||||
static void mdp4_plane_cleanup_fb(struct drm_plane *plane,
|
||||
|
|
@ -117,13 +118,14 @@ static void mdp4_plane_cleanup_fb(struct drm_plane *plane,
|
|||
{
|
||||
struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
|
||||
struct mdp4_kms *mdp4_kms = get_kms(plane);
|
||||
struct msm_kms *kms = &mdp4_kms->base.base;
|
||||
struct drm_framebuffer *fb = old_state->fb;
|
||||
|
||||
if (!fb)
|
||||
return;
|
||||
|
||||
DBG("%s: cleanup: FB[%u]", mdp4_plane->name, fb->base.id);
|
||||
msm_framebuffer_cleanup(fb, mdp4_kms->id);
|
||||
msm_framebuffer_cleanup(fb, kms->aspace);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -161,6 +163,7 @@ static void mdp4_plane_set_scanout(struct drm_plane *plane,
|
|||
{
|
||||
struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
|
||||
struct mdp4_kms *mdp4_kms = get_kms(plane);
|
||||
struct msm_kms *kms = &mdp4_kms->base.base;
|
||||
enum mdp4_pipe pipe = mdp4_plane->pipe;
|
||||
|
||||
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_STRIDE_A(pipe),
|
||||
|
|
@ -172,13 +175,13 @@ static void mdp4_plane_set_scanout(struct drm_plane *plane,
|
|||
MDP4_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
|
||||
|
||||
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP0_BASE(pipe),
|
||||
msm_framebuffer_iova(fb, mdp4_kms->id, 0));
|
||||
msm_framebuffer_iova(fb, kms->aspace, 0));
|
||||
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP1_BASE(pipe),
|
||||
msm_framebuffer_iova(fb, mdp4_kms->id, 1));
|
||||
msm_framebuffer_iova(fb, kms->aspace, 1));
|
||||
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP2_BASE(pipe),
|
||||
msm_framebuffer_iova(fb, mdp4_kms->id, 2));
|
||||
msm_framebuffer_iova(fb, kms->aspace, 2));
|
||||
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRCP3_BASE(pipe),
|
||||
msm_framebuffer_iova(fb, mdp4_kms->id, 3));
|
||||
msm_framebuffer_iova(fb, kms->aspace, 3));
|
||||
|
||||
plane->fb = fb;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -8,9 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /local/mnt/workspace/source_trees/envytools/rnndb/../rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-01-11 05:19:19)
|
||||
- /local/mnt/workspace/source_trees/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-05-09 06:32:54)
|
||||
- /local/mnt/workspace/source_trees/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2016-01-07 08:45:55)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
|
|
|||
|
|
@ -160,8 +160,9 @@ static void unref_cursor_worker(struct drm_flip_work *work, void *val)
|
|||
struct mdp5_crtc *mdp5_crtc =
|
||||
container_of(work, struct mdp5_crtc, unref_cursor_work);
|
||||
struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base);
|
||||
struct msm_kms *kms = &mdp5_kms->base.base;
|
||||
|
||||
msm_gem_put_iova(val, mdp5_kms->id);
|
||||
msm_gem_put_iova(val, kms->aspace);
|
||||
drm_gem_object_unreference_unlocked(val);
|
||||
}
|
||||
|
||||
|
|
@ -724,6 +725,7 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
|
|||
struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline;
|
||||
struct drm_device *dev = crtc->dev;
|
||||
struct mdp5_kms *mdp5_kms = get_kms(crtc);
|
||||
struct msm_kms *kms = &mdp5_kms->base.base;
|
||||
struct drm_gem_object *cursor_bo, *old_bo = NULL;
|
||||
uint32_t blendcfg, stride;
|
||||
uint64_t cursor_addr;
|
||||
|
|
@ -758,7 +760,7 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
|
|||
if (!cursor_bo)
|
||||
return -ENOENT;
|
||||
|
||||
ret = msm_gem_get_iova(cursor_bo, mdp5_kms->id, &cursor_addr);
|
||||
ret = msm_gem_get_iova(cursor_bo, kms->aspace, &cursor_addr);
|
||||
if (ret)
|
||||
return -EINVAL;
|
||||
|
||||
|
|
|
|||
|
|
@ -163,7 +163,7 @@ static void mdp5_set_encoder_mode(struct msm_kms *kms,
|
|||
static void mdp5_kms_destroy(struct msm_kms *kms)
|
||||
{
|
||||
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
|
||||
struct msm_gem_address_space *aspace = mdp5_kms->aspace;
|
||||
struct msm_gem_address_space *aspace = kms->aspace;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < mdp5_kms->num_hwmixers; i++)
|
||||
|
|
@ -663,7 +663,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
|
|||
goto fail;
|
||||
}
|
||||
|
||||
mdp5_kms->aspace = aspace;
|
||||
kms->aspace = aspace;
|
||||
|
||||
ret = aspace->mmu->funcs->attach(aspace->mmu, iommu_ports,
|
||||
ARRAY_SIZE(iommu_ports));
|
||||
|
|
@ -678,13 +678,6 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
|
|||
aspace = NULL;;
|
||||
}
|
||||
|
||||
mdp5_kms->id = msm_register_address_space(dev, aspace);
|
||||
if (mdp5_kms->id < 0) {
|
||||
ret = mdp5_kms->id;
|
||||
dev_err(&pdev->dev, "failed to register mdp5 iommu: %d\n", ret);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
ret = modeset_init(mdp5_kms);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "modeset_init failed: %d\n", ret);
|
||||
|
|
|
|||
|
|
@ -55,10 +55,6 @@ struct mdp5_kms {
|
|||
struct mdp5_state *state;
|
||||
struct drm_modeset_lock state_lock;
|
||||
|
||||
/* mapper-id used to request GEM buffer mapped for scanout: */
|
||||
int id;
|
||||
struct msm_gem_address_space *aspace;
|
||||
|
||||
struct mdp5_smp *smp;
|
||||
struct mdp5_ctl_manager *ctlm;
|
||||
|
||||
|
|
|
|||
|
|
@ -22,8 +22,6 @@
|
|||
struct mdp5_plane {
|
||||
struct drm_plane base;
|
||||
|
||||
spinlock_t pipe_lock; /* protect REG_MDP5_PIPE_* registers */
|
||||
|
||||
uint32_t nformats;
|
||||
uint32_t formats[32];
|
||||
};
|
||||
|
|
@ -274,26 +272,28 @@ static int mdp5_plane_prepare_fb(struct drm_plane *plane,
|
|||
struct drm_plane_state *new_state)
|
||||
{
|
||||
struct mdp5_kms *mdp5_kms = get_kms(plane);
|
||||
struct msm_kms *kms = &mdp5_kms->base.base;
|
||||
struct drm_framebuffer *fb = new_state->fb;
|
||||
|
||||
if (!new_state->fb)
|
||||
return 0;
|
||||
|
||||
DBG("%s: prepare: FB[%u]", plane->name, fb->base.id);
|
||||
return msm_framebuffer_prepare(fb, mdp5_kms->id);
|
||||
return msm_framebuffer_prepare(fb, kms->aspace);
|
||||
}
|
||||
|
||||
static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
|
||||
struct drm_plane_state *old_state)
|
||||
{
|
||||
struct mdp5_kms *mdp5_kms = get_kms(plane);
|
||||
struct msm_kms *kms = &mdp5_kms->base.base;
|
||||
struct drm_framebuffer *fb = old_state->fb;
|
||||
|
||||
if (!fb)
|
||||
return;
|
||||
|
||||
DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id);
|
||||
msm_framebuffer_cleanup(fb, mdp5_kms->id);
|
||||
msm_framebuffer_cleanup(fb, kms->aspace);
|
||||
}
|
||||
|
||||
#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
|
||||
|
|
@ -500,6 +500,8 @@ static void set_scanout_locked(struct mdp5_kms *mdp5_kms,
|
|||
enum mdp5_pipe pipe,
|
||||
struct drm_framebuffer *fb)
|
||||
{
|
||||
struct msm_kms *kms = &mdp5_kms->base.base;
|
||||
|
||||
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),
|
||||
MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
|
||||
MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
|
||||
|
|
@ -509,13 +511,13 @@ static void set_scanout_locked(struct mdp5_kms *mdp5_kms,
|
|||
MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
|
||||
|
||||
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe),
|
||||
msm_framebuffer_iova(fb, mdp5_kms->id, 0));
|
||||
msm_framebuffer_iova(fb, kms->aspace, 0));
|
||||
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe),
|
||||
msm_framebuffer_iova(fb, mdp5_kms->id, 1));
|
||||
msm_framebuffer_iova(fb, kms->aspace, 1));
|
||||
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
|
||||
msm_framebuffer_iova(fb, mdp5_kms->id, 2));
|
||||
msm_framebuffer_iova(fb, kms->aspace, 2));
|
||||
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
|
||||
msm_framebuffer_iova(fb, mdp5_kms->id, 3));
|
||||
msm_framebuffer_iova(fb, kms->aspace, 3));
|
||||
}
|
||||
|
||||
/* Note: mdp5_plane->pipe_lock must be locked */
|
||||
|
|
@ -881,7 +883,6 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
|
|||
struct drm_crtc *crtc, struct drm_framebuffer *fb,
|
||||
struct drm_rect *src, struct drm_rect *dest)
|
||||
{
|
||||
struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
|
||||
struct drm_plane_state *pstate = plane->state;
|
||||
struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe;
|
||||
struct mdp5_kms *mdp5_kms = get_kms(plane);
|
||||
|
|
@ -902,7 +903,6 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
|
|||
uint32_t src_img_w, src_img_h;
|
||||
uint32_t src_x_r;
|
||||
int crtc_x_r;
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
nplanes = fb->format->num_planes;
|
||||
|
|
@ -981,8 +981,6 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
|
|||
hflip = !!(rotation & DRM_MODE_REFLECT_X);
|
||||
vflip = !!(rotation & DRM_MODE_REFLECT_Y);
|
||||
|
||||
spin_lock_irqsave(&mdp5_plane->pipe_lock, flags);
|
||||
|
||||
mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe,
|
||||
config, hdecm, vdecm, hflip, vflip,
|
||||
crtc_x, crtc_y, crtc_w, crtc_h,
|
||||
|
|
@ -995,8 +993,6 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
|
|||
src_img_w, src_img_h,
|
||||
src_x_r, src_y, src_w, src_h);
|
||||
|
||||
spin_unlock_irqrestore(&mdp5_plane->pipe_lock, flags);
|
||||
|
||||
plane->fb = fb;
|
||||
|
||||
return ret;
|
||||
|
|
@ -1139,8 +1135,6 @@ struct drm_plane *mdp5_plane_init(struct drm_device *dev,
|
|||
mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
|
||||
ARRAY_SIZE(mdp5_plane->formats), false);
|
||||
|
||||
spin_lock_init(&mdp5_plane->pipe_lock);
|
||||
|
||||
if (type == DRM_PLANE_TYPE_CURSOR)
|
||||
ret = drm_universal_plane_init(dev, plane, 0xff,
|
||||
&mdp5_cursor_plane_funcs,
|
||||
|
|
|
|||
|
|
@ -8,19 +8,19 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
|
|||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
|
|
|||
|
|
@ -51,19 +51,6 @@ static const struct drm_mode_config_funcs mode_config_funcs = {
|
|||
.atomic_state_free = msm_atomic_state_free,
|
||||
};
|
||||
|
||||
int msm_register_address_space(struct drm_device *dev,
|
||||
struct msm_gem_address_space *aspace)
|
||||
{
|
||||
struct msm_drm_private *priv = dev->dev_private;
|
||||
|
||||
if (WARN_ON(priv->num_aspaces >= ARRAY_SIZE(priv->aspace)))
|
||||
return -EINVAL;
|
||||
|
||||
priv->aspace[priv->num_aspaces] = aspace;
|
||||
|
||||
return priv->num_aspaces++;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
|
||||
static bool reglog = false;
|
||||
MODULE_PARM_DESC(reglog, "Enable register read/write logging");
|
||||
|
|
@ -349,6 +336,7 @@ static int msm_init_vram(struct drm_device *dev)
|
|||
priv->vram.size = size;
|
||||
|
||||
drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
|
||||
spin_lock_init(&priv->vram.lock);
|
||||
|
||||
attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
|
||||
attrs |= DMA_ATTR_WRITE_COMBINE;
|
||||
|
|
@ -699,6 +687,17 @@ static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int msm_ioctl_gem_info_iova(struct drm_device *dev,
|
||||
struct drm_gem_object *obj, uint64_t *iova)
|
||||
{
|
||||
struct msm_drm_private *priv = dev->dev_private;
|
||||
|
||||
if (!priv->gpu)
|
||||
return -EINVAL;
|
||||
|
||||
return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
|
||||
}
|
||||
|
||||
static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
|
||||
struct drm_file *file)
|
||||
{
|
||||
|
|
@ -706,14 +705,22 @@ static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
|
|||
struct drm_gem_object *obj;
|
||||
int ret = 0;
|
||||
|
||||
if (args->pad)
|
||||
if (args->flags & ~MSM_INFO_FLAGS)
|
||||
return -EINVAL;
|
||||
|
||||
obj = drm_gem_object_lookup(file, args->handle);
|
||||
if (!obj)
|
||||
return -ENOENT;
|
||||
|
||||
args->offset = msm_gem_mmap_offset(obj);
|
||||
if (args->flags & MSM_INFO_IOVA) {
|
||||
uint64_t iova;
|
||||
|
||||
ret = msm_ioctl_gem_info_iova(dev, obj, &iova);
|
||||
if (!ret)
|
||||
args->offset = iova;
|
||||
} else {
|
||||
args->offset = msm_gem_mmap_offset(obj);
|
||||
}
|
||||
|
||||
drm_gem_object_unreference_unlocked(obj);
|
||||
|
||||
|
|
@ -842,7 +849,7 @@ static struct drm_driver msm_driver = {
|
|||
.debugfs_init = msm_debugfs_init,
|
||||
#endif
|
||||
.ioctls = msm_ioctls,
|
||||
.num_ioctls = DRM_MSM_NUM_IOCTLS,
|
||||
.num_ioctls = ARRAY_SIZE(msm_ioctls),
|
||||
.fops = &fops,
|
||||
.name = "msm",
|
||||
.desc = "MSM Snapdragon DRM",
|
||||
|
|
|
|||
|
|
@ -123,14 +123,6 @@ struct msm_drm_private {
|
|||
uint32_t pending_crtcs;
|
||||
wait_queue_head_t pending_crtcs_event;
|
||||
|
||||
/* Registered address spaces.. currently this is fixed per # of
|
||||
* iommu's. Ie. one for display block and one for gpu block.
|
||||
* Eventually, to do per-process gpu pagetables, we'll want one
|
||||
* of these per-process.
|
||||
*/
|
||||
unsigned int num_aspaces;
|
||||
struct msm_gem_address_space *aspace[NUM_DOMAINS];
|
||||
|
||||
unsigned int num_planes;
|
||||
struct drm_plane *planes[16];
|
||||
|
||||
|
|
@ -157,6 +149,7 @@ struct msm_drm_private {
|
|||
* and position mm_node->start is in # of pages:
|
||||
*/
|
||||
struct drm_mm mm;
|
||||
spinlock_t lock; /* Protects drm_mm node allocation/removal */
|
||||
} vram;
|
||||
|
||||
struct notifier_block vmap_notifier;
|
||||
|
|
@ -183,9 +176,6 @@ struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
|
|||
void msm_atomic_state_clear(struct drm_atomic_state *state);
|
||||
void msm_atomic_state_free(struct drm_atomic_state *state);
|
||||
|
||||
int msm_register_address_space(struct drm_device *dev,
|
||||
struct msm_gem_address_space *aspace);
|
||||
|
||||
void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
|
||||
struct msm_gem_vma *vma, struct sg_table *sgt);
|
||||
int msm_gem_map_vma(struct msm_gem_address_space *aspace,
|
||||
|
|
@ -209,13 +199,14 @@ int msm_gem_mmap_obj(struct drm_gem_object *obj,
|
|||
int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
|
||||
int msm_gem_fault(struct vm_fault *vmf);
|
||||
uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
|
||||
int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
|
||||
uint64_t *iova);
|
||||
int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint64_t *iova);
|
||||
uint64_t msm_gem_iova(struct drm_gem_object *obj, int id);
|
||||
int msm_gem_get_iova(struct drm_gem_object *obj,
|
||||
struct msm_gem_address_space *aspace, uint64_t *iova);
|
||||
uint64_t msm_gem_iova(struct drm_gem_object *obj,
|
||||
struct msm_gem_address_space *aspace);
|
||||
struct page **msm_gem_get_pages(struct drm_gem_object *obj);
|
||||
void msm_gem_put_pages(struct drm_gem_object *obj);
|
||||
void msm_gem_put_iova(struct drm_gem_object *obj, int id);
|
||||
void msm_gem_put_iova(struct drm_gem_object *obj,
|
||||
struct msm_gem_address_space *aspace);
|
||||
int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
|
||||
struct drm_mode_create_dumb *args);
|
||||
int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
|
||||
|
|
@ -229,13 +220,9 @@ struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
|
|||
struct dma_buf_attachment *attach, struct sg_table *sg);
|
||||
int msm_gem_prime_pin(struct drm_gem_object *obj);
|
||||
void msm_gem_prime_unpin(struct drm_gem_object *obj);
|
||||
void *msm_gem_get_vaddr_locked(struct drm_gem_object *obj);
|
||||
void *msm_gem_get_vaddr(struct drm_gem_object *obj);
|
||||
void msm_gem_put_vaddr_locked(struct drm_gem_object *obj);
|
||||
void msm_gem_put_vaddr(struct drm_gem_object *obj);
|
||||
int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
|
||||
void msm_gem_purge(struct drm_gem_object *obj);
|
||||
void msm_gem_vunmap(struct drm_gem_object *obj);
|
||||
int msm_gem_sync_object(struct drm_gem_object *obj,
|
||||
struct msm_fence_context *fctx, bool exclusive);
|
||||
void msm_gem_move_to_active(struct drm_gem_object *obj,
|
||||
|
|
@ -248,12 +235,17 @@ int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
|
|||
uint32_t size, uint32_t flags, uint32_t *handle);
|
||||
struct drm_gem_object *msm_gem_new(struct drm_device *dev,
|
||||
uint32_t size, uint32_t flags);
|
||||
struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev,
|
||||
uint32_t size, uint32_t flags);
|
||||
struct drm_gem_object *msm_gem_import(struct drm_device *dev,
|
||||
struct dma_buf *dmabuf, struct sg_table *sgt);
|
||||
|
||||
int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id);
|
||||
void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id);
|
||||
uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane);
|
||||
int msm_framebuffer_prepare(struct drm_framebuffer *fb,
|
||||
struct msm_gem_address_space *aspace);
|
||||
void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
|
||||
struct msm_gem_address_space *aspace);
|
||||
uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
|
||||
struct msm_gem_address_space *aspace, int plane);
|
||||
struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
|
||||
const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
|
||||
struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
|
||||
|
|
|
|||
|
|
@ -84,14 +84,15 @@ void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m)
|
|||
* should be fine, since only the scanout (mdpN) side of things needs
|
||||
* this, the gpu doesn't care about fb's.
|
||||
*/
|
||||
int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id)
|
||||
int msm_framebuffer_prepare(struct drm_framebuffer *fb,
|
||||
struct msm_gem_address_space *aspace)
|
||||
{
|
||||
struct msm_framebuffer *msm_fb = to_msm_framebuffer(fb);
|
||||
int ret, i, n = fb->format->num_planes;
|
||||
uint64_t iova;
|
||||
|
||||
for (i = 0; i < n; i++) {
|
||||
ret = msm_gem_get_iova(msm_fb->planes[i], id, &iova);
|
||||
ret = msm_gem_get_iova(msm_fb->planes[i], aspace, &iova);
|
||||
DBG("FB[%u]: iova[%d]: %08llx (%d)", fb->base.id, i, iova, ret);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
@ -100,21 +101,23 @@ int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id)
|
||||
void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
|
||||
struct msm_gem_address_space *aspace)
|
||||
{
|
||||
struct msm_framebuffer *msm_fb = to_msm_framebuffer(fb);
|
||||
int i, n = fb->format->num_planes;
|
||||
|
||||
for (i = 0; i < n; i++)
|
||||
msm_gem_put_iova(msm_fb->planes[i], id);
|
||||
msm_gem_put_iova(msm_fb->planes[i], aspace);
|
||||
}
|
||||
|
||||
uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane)
|
||||
uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
|
||||
struct msm_gem_address_space *aspace, int plane)
|
||||
{
|
||||
struct msm_framebuffer *msm_fb = to_msm_framebuffer(fb);
|
||||
if (!msm_fb->planes[plane])
|
||||
return 0;
|
||||
return msm_gem_iova(msm_fb->planes[plane], id) + fb->offsets[plane];
|
||||
return msm_gem_iova(msm_fb->planes[plane], aspace) + fb->offsets[plane];
|
||||
}
|
||||
|
||||
struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane)
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
|
||||
#include "msm_drv.h"
|
||||
#include "msm_gem.h"
|
||||
#include "msm_kms.h"
|
||||
|
||||
extern int msm_gem_mmap_obj(struct drm_gem_object *obj,
|
||||
struct vm_area_struct *vma);
|
||||
|
|
@ -73,6 +74,7 @@ static int msm_fbdev_create(struct drm_fb_helper *helper,
|
|||
{
|
||||
struct msm_fbdev *fbdev = to_msm_fbdev(helper);
|
||||
struct drm_device *dev = helper->dev;
|
||||
struct msm_drm_private *priv = dev->dev_private;
|
||||
struct drm_framebuffer *fb = NULL;
|
||||
struct fb_info *fbi = NULL;
|
||||
struct drm_mode_fb_cmd2 mode_cmd = {0};
|
||||
|
|
@ -95,10 +97,8 @@ static int msm_fbdev_create(struct drm_fb_helper *helper,
|
|||
/* allocate backing bo */
|
||||
size = mode_cmd.pitches[0] * mode_cmd.height;
|
||||
DBG("allocating %d bytes for fb %d", size, dev->primary->index);
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
fbdev->bo = msm_gem_new(dev, size, MSM_BO_SCANOUT |
|
||||
MSM_BO_WC | MSM_BO_STOLEN);
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
if (IS_ERR(fbdev->bo)) {
|
||||
ret = PTR_ERR(fbdev->bo);
|
||||
fbdev->bo = NULL;
|
||||
|
|
@ -124,7 +124,7 @@ static int msm_fbdev_create(struct drm_fb_helper *helper,
|
|||
* in panic (ie. lock-safe, etc) we could avoid pinning the
|
||||
* buffer now:
|
||||
*/
|
||||
ret = msm_gem_get_iova_locked(fbdev->bo, 0, &paddr);
|
||||
ret = msm_gem_get_iova(fbdev->bo, priv->kms->aspace, &paddr);
|
||||
if (ret) {
|
||||
dev_err(dev->dev, "failed to get buffer obj iova: %d\n", ret);
|
||||
goto fail_unlock;
|
||||
|
|
@ -153,7 +153,7 @@ static int msm_fbdev_create(struct drm_fb_helper *helper,
|
|||
|
||||
dev->mode_config.fb_base = paddr;
|
||||
|
||||
fbi->screen_base = msm_gem_get_vaddr_locked(fbdev->bo);
|
||||
fbi->screen_base = msm_gem_get_vaddr(fbdev->bo);
|
||||
if (IS_ERR(fbi->screen_base)) {
|
||||
ret = PTR_ERR(fbi->screen_base);
|
||||
goto fail_unlock;
|
||||
|
|
|
|||
|
|
@ -26,6 +26,9 @@
|
|||
#include "msm_gpu.h"
|
||||
#include "msm_mmu.h"
|
||||
|
||||
static void msm_gem_vunmap_locked(struct drm_gem_object *obj);
|
||||
|
||||
|
||||
static dma_addr_t physaddr(struct drm_gem_object *obj)
|
||||
{
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
|
|
@ -41,8 +44,7 @@ static bool use_pages(struct drm_gem_object *obj)
|
|||
}
|
||||
|
||||
/* allocate pages from VRAM carveout, used when no IOMMU: */
|
||||
static struct page **get_pages_vram(struct drm_gem_object *obj,
|
||||
int npages)
|
||||
static struct page **get_pages_vram(struct drm_gem_object *obj, int npages)
|
||||
{
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
struct msm_drm_private *priv = obj->dev->dev_private;
|
||||
|
|
@ -54,7 +56,9 @@ static struct page **get_pages_vram(struct drm_gem_object *obj,
|
|||
if (!p)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
spin_lock(&priv->vram.lock);
|
||||
ret = drm_mm_insert_node(&priv->vram.mm, msm_obj->vram_node, npages);
|
||||
spin_unlock(&priv->vram.lock);
|
||||
if (ret) {
|
||||
kvfree(p);
|
||||
return ERR_PTR(ret);
|
||||
|
|
@ -69,7 +73,6 @@ static struct page **get_pages_vram(struct drm_gem_object *obj,
|
|||
return p;
|
||||
}
|
||||
|
||||
/* called with dev->struct_mutex held */
|
||||
static struct page **get_pages(struct drm_gem_object *obj)
|
||||
{
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
|
|
@ -109,6 +112,18 @@ static struct page **get_pages(struct drm_gem_object *obj)
|
|||
return msm_obj->pages;
|
||||
}
|
||||
|
||||
static void put_pages_vram(struct drm_gem_object *obj)
|
||||
{
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
struct msm_drm_private *priv = obj->dev->dev_private;
|
||||
|
||||
spin_lock(&priv->vram.lock);
|
||||
drm_mm_remove_node(msm_obj->vram_node);
|
||||
spin_unlock(&priv->vram.lock);
|
||||
|
||||
kvfree(msm_obj->pages);
|
||||
}
|
||||
|
||||
static void put_pages(struct drm_gem_object *obj)
|
||||
{
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
|
|
@ -125,10 +140,8 @@ static void put_pages(struct drm_gem_object *obj)
|
|||
|
||||
if (use_pages(obj))
|
||||
drm_gem_put_pages(obj, msm_obj->pages, true, false);
|
||||
else {
|
||||
drm_mm_remove_node(msm_obj->vram_node);
|
||||
kvfree(msm_obj->pages);
|
||||
}
|
||||
else
|
||||
put_pages_vram(obj);
|
||||
|
||||
msm_obj->pages = NULL;
|
||||
}
|
||||
|
|
@ -136,11 +149,18 @@ static void put_pages(struct drm_gem_object *obj)
|
|||
|
||||
struct page **msm_gem_get_pages(struct drm_gem_object *obj)
|
||||
{
|
||||
struct drm_device *dev = obj->dev;
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
struct page **p;
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
|
||||
mutex_lock(&msm_obj->lock);
|
||||
|
||||
if (WARN_ON(msm_obj->madv != MSM_MADV_WILLNEED)) {
|
||||
mutex_unlock(&msm_obj->lock);
|
||||
return ERR_PTR(-EBUSY);
|
||||
}
|
||||
|
||||
p = get_pages(obj);
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
mutex_unlock(&msm_obj->lock);
|
||||
return p;
|
||||
}
|
||||
|
||||
|
|
@ -195,28 +215,25 @@ int msm_gem_fault(struct vm_fault *vmf)
|
|||
{
|
||||
struct vm_area_struct *vma = vmf->vma;
|
||||
struct drm_gem_object *obj = vma->vm_private_data;
|
||||
struct drm_device *dev = obj->dev;
|
||||
struct msm_drm_private *priv = dev->dev_private;
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
struct page **pages;
|
||||
unsigned long pfn;
|
||||
pgoff_t pgoff;
|
||||
int ret;
|
||||
|
||||
/* This should only happen if userspace tries to pass a mmap'd
|
||||
* but unfaulted gem bo vaddr into submit ioctl, triggering
|
||||
* a page fault while struct_mutex is already held. This is
|
||||
* not a valid use-case so just bail.
|
||||
/*
|
||||
* vm_ops.open/drm_gem_mmap_obj and close get and put
|
||||
* a reference on obj. So, we dont need to hold one here.
|
||||
*/
|
||||
if (priv->struct_mutex_task == current)
|
||||
return VM_FAULT_SIGBUS;
|
||||
|
||||
/* Make sure we don't parallel update on a fault, nor move or remove
|
||||
* something from beneath our feet
|
||||
*/
|
||||
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
||||
ret = mutex_lock_interruptible(&msm_obj->lock);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
if (WARN_ON(msm_obj->madv != MSM_MADV_WILLNEED)) {
|
||||
mutex_unlock(&msm_obj->lock);
|
||||
return VM_FAULT_SIGBUS;
|
||||
}
|
||||
|
||||
/* make sure we have pages attached now */
|
||||
pages = get_pages(obj);
|
||||
if (IS_ERR(pages)) {
|
||||
|
|
@ -235,7 +252,7 @@ int msm_gem_fault(struct vm_fault *vmf)
|
|||
ret = vm_insert_mixed(vma, vmf->address, __pfn_to_pfn_t(pfn, PFN_DEV));
|
||||
|
||||
out_unlock:
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
mutex_unlock(&msm_obj->lock);
|
||||
out:
|
||||
switch (ret) {
|
||||
case -EAGAIN:
|
||||
|
|
@ -259,9 +276,10 @@ int msm_gem_fault(struct vm_fault *vmf)
|
|||
static uint64_t mmap_offset(struct drm_gem_object *obj)
|
||||
{
|
||||
struct drm_device *dev = obj->dev;
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
int ret;
|
||||
|
||||
WARN_ON(!mutex_is_locked(&dev->struct_mutex));
|
||||
WARN_ON(!mutex_is_locked(&msm_obj->lock));
|
||||
|
||||
/* Make it mmapable */
|
||||
ret = drm_gem_create_mmap_offset(obj);
|
||||
|
|
@ -277,95 +295,140 @@ static uint64_t mmap_offset(struct drm_gem_object *obj)
|
|||
uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj)
|
||||
{
|
||||
uint64_t offset;
|
||||
mutex_lock(&obj->dev->struct_mutex);
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
|
||||
mutex_lock(&msm_obj->lock);
|
||||
offset = mmap_offset(obj);
|
||||
mutex_unlock(&obj->dev->struct_mutex);
|
||||
mutex_unlock(&msm_obj->lock);
|
||||
return offset;
|
||||
}
|
||||
|
||||
static struct msm_gem_vma *add_vma(struct drm_gem_object *obj,
|
||||
struct msm_gem_address_space *aspace)
|
||||
{
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
struct msm_gem_vma *vma;
|
||||
|
||||
WARN_ON(!mutex_is_locked(&msm_obj->lock));
|
||||
|
||||
vma = kzalloc(sizeof(*vma), GFP_KERNEL);
|
||||
if (!vma)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
vma->aspace = aspace;
|
||||
|
||||
list_add_tail(&vma->list, &msm_obj->vmas);
|
||||
|
||||
return vma;
|
||||
}
|
||||
|
||||
static struct msm_gem_vma *lookup_vma(struct drm_gem_object *obj,
|
||||
struct msm_gem_address_space *aspace)
|
||||
{
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
struct msm_gem_vma *vma;
|
||||
|
||||
WARN_ON(!mutex_is_locked(&msm_obj->lock));
|
||||
|
||||
list_for_each_entry(vma, &msm_obj->vmas, list) {
|
||||
if (vma->aspace == aspace)
|
||||
return vma;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void del_vma(struct msm_gem_vma *vma)
|
||||
{
|
||||
if (!vma)
|
||||
return;
|
||||
|
||||
list_del(&vma->list);
|
||||
kfree(vma);
|
||||
}
|
||||
|
||||
/* Called with msm_obj->lock locked */
|
||||
static void
|
||||
put_iova(struct drm_gem_object *obj)
|
||||
{
|
||||
struct drm_device *dev = obj->dev;
|
||||
struct msm_drm_private *priv = obj->dev->dev_private;
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
int id;
|
||||
struct msm_gem_vma *vma, *tmp;
|
||||
|
||||
WARN_ON(!mutex_is_locked(&dev->struct_mutex));
|
||||
WARN_ON(!mutex_is_locked(&msm_obj->lock));
|
||||
|
||||
for (id = 0; id < ARRAY_SIZE(msm_obj->domain); id++) {
|
||||
if (!priv->aspace[id])
|
||||
continue;
|
||||
msm_gem_unmap_vma(priv->aspace[id],
|
||||
&msm_obj->domain[id], msm_obj->sgt);
|
||||
list_for_each_entry_safe(vma, tmp, &msm_obj->vmas, list) {
|
||||
msm_gem_unmap_vma(vma->aspace, vma, msm_obj->sgt);
|
||||
del_vma(vma);
|
||||
}
|
||||
}
|
||||
|
||||
/* should be called under struct_mutex.. although it can be called
|
||||
* from atomic context without struct_mutex to acquire an extra
|
||||
* iova ref if you know one is already held.
|
||||
*
|
||||
* That means when I do eventually need to add support for unpinning
|
||||
* the refcnt counter needs to be atomic_t.
|
||||
*/
|
||||
int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
|
||||
uint64_t *iova)
|
||||
{
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
int ret = 0;
|
||||
|
||||
if (!msm_obj->domain[id].iova) {
|
||||
struct msm_drm_private *priv = obj->dev->dev_private;
|
||||
struct page **pages = get_pages(obj);
|
||||
|
||||
if (IS_ERR(pages))
|
||||
return PTR_ERR(pages);
|
||||
|
||||
if (iommu_present(&platform_bus_type)) {
|
||||
ret = msm_gem_map_vma(priv->aspace[id], &msm_obj->domain[id],
|
||||
msm_obj->sgt, obj->size >> PAGE_SHIFT);
|
||||
} else {
|
||||
msm_obj->domain[id].iova = physaddr(obj);
|
||||
}
|
||||
}
|
||||
|
||||
if (!ret)
|
||||
*iova = msm_obj->domain[id].iova;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* get iova, taking a reference. Should have a matching put */
|
||||
int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint64_t *iova)
|
||||
int msm_gem_get_iova(struct drm_gem_object *obj,
|
||||
struct msm_gem_address_space *aspace, uint64_t *iova)
|
||||
{
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
int ret;
|
||||
struct msm_gem_vma *vma;
|
||||
int ret = 0;
|
||||
|
||||
/* this is safe right now because we don't unmap until the
|
||||
* bo is deleted:
|
||||
*/
|
||||
if (msm_obj->domain[id].iova) {
|
||||
*iova = msm_obj->domain[id].iova;
|
||||
return 0;
|
||||
mutex_lock(&msm_obj->lock);
|
||||
|
||||
if (WARN_ON(msm_obj->madv != MSM_MADV_WILLNEED)) {
|
||||
mutex_unlock(&msm_obj->lock);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
mutex_lock(&obj->dev->struct_mutex);
|
||||
ret = msm_gem_get_iova_locked(obj, id, iova);
|
||||
mutex_unlock(&obj->dev->struct_mutex);
|
||||
vma = lookup_vma(obj, aspace);
|
||||
|
||||
if (!vma) {
|
||||
struct page **pages;
|
||||
|
||||
vma = add_vma(obj, aspace);
|
||||
if (IS_ERR(vma))
|
||||
return PTR_ERR(vma);
|
||||
|
||||
pages = get_pages(obj);
|
||||
if (IS_ERR(pages)) {
|
||||
ret = PTR_ERR(pages);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
ret = msm_gem_map_vma(aspace, vma, msm_obj->sgt,
|
||||
obj->size >> PAGE_SHIFT);
|
||||
if (ret)
|
||||
goto fail;
|
||||
}
|
||||
|
||||
*iova = vma->iova;
|
||||
|
||||
mutex_unlock(&msm_obj->lock);
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
del_vma(vma);
|
||||
|
||||
mutex_unlock(&msm_obj->lock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* get iova without taking a reference, used in places where you have
|
||||
* already done a 'msm_gem_get_iova()'.
|
||||
*/
|
||||
uint64_t msm_gem_iova(struct drm_gem_object *obj, int id)
|
||||
uint64_t msm_gem_iova(struct drm_gem_object *obj,
|
||||
struct msm_gem_address_space *aspace)
|
||||
{
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
WARN_ON(!msm_obj->domain[id].iova);
|
||||
return msm_obj->domain[id].iova;
|
||||
struct msm_gem_vma *vma;
|
||||
|
||||
mutex_lock(&msm_obj->lock);
|
||||
vma = lookup_vma(obj, aspace);
|
||||
mutex_unlock(&msm_obj->lock);
|
||||
WARN_ON(!vma);
|
||||
|
||||
return vma ? vma->iova : 0;
|
||||
}
|
||||
|
||||
void msm_gem_put_iova(struct drm_gem_object *obj, int id)
|
||||
void msm_gem_put_iova(struct drm_gem_object *obj,
|
||||
struct msm_gem_address_space *aspace)
|
||||
{
|
||||
// XXX TODO ..
|
||||
// NOTE: probably don't need a _locked() version.. we wouldn't
|
||||
|
|
@ -405,45 +468,57 @@ int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
|
|||
return ret;
|
||||
}
|
||||
|
||||
void *msm_gem_get_vaddr_locked(struct drm_gem_object *obj)
|
||||
{
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
WARN_ON(!mutex_is_locked(&obj->dev->struct_mutex));
|
||||
if (!msm_obj->vaddr) {
|
||||
struct page **pages = get_pages(obj);
|
||||
if (IS_ERR(pages))
|
||||
return ERR_CAST(pages);
|
||||
msm_obj->vaddr = vmap(pages, obj->size >> PAGE_SHIFT,
|
||||
VM_MAP, pgprot_writecombine(PAGE_KERNEL));
|
||||
if (msm_obj->vaddr == NULL)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
msm_obj->vmap_count++;
|
||||
return msm_obj->vaddr;
|
||||
}
|
||||
|
||||
void *msm_gem_get_vaddr(struct drm_gem_object *obj)
|
||||
{
|
||||
void *ret;
|
||||
mutex_lock(&obj->dev->struct_mutex);
|
||||
ret = msm_gem_get_vaddr_locked(obj);
|
||||
mutex_unlock(&obj->dev->struct_mutex);
|
||||
return ret;
|
||||
}
|
||||
|
||||
void msm_gem_put_vaddr_locked(struct drm_gem_object *obj)
|
||||
{
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
WARN_ON(!mutex_is_locked(&obj->dev->struct_mutex));
|
||||
WARN_ON(msm_obj->vmap_count < 1);
|
||||
int ret = 0;
|
||||
|
||||
mutex_lock(&msm_obj->lock);
|
||||
|
||||
if (WARN_ON(msm_obj->madv != MSM_MADV_WILLNEED)) {
|
||||
mutex_unlock(&msm_obj->lock);
|
||||
return ERR_PTR(-EBUSY);
|
||||
}
|
||||
|
||||
/* increment vmap_count *before* vmap() call, so shrinker can
|
||||
* check vmap_count (is_vunmapable()) outside of msm_obj->lock.
|
||||
* This guarantees that we won't try to msm_gem_vunmap() this
|
||||
* same object from within the vmap() call (while we already
|
||||
* hold msm_obj->lock)
|
||||
*/
|
||||
msm_obj->vmap_count++;
|
||||
|
||||
if (!msm_obj->vaddr) {
|
||||
struct page **pages = get_pages(obj);
|
||||
if (IS_ERR(pages)) {
|
||||
ret = PTR_ERR(pages);
|
||||
goto fail;
|
||||
}
|
||||
msm_obj->vaddr = vmap(pages, obj->size >> PAGE_SHIFT,
|
||||
VM_MAP, pgprot_writecombine(PAGE_KERNEL));
|
||||
if (msm_obj->vaddr == NULL) {
|
||||
ret = -ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
|
||||
mutex_unlock(&msm_obj->lock);
|
||||
return msm_obj->vaddr;
|
||||
|
||||
fail:
|
||||
msm_obj->vmap_count--;
|
||||
mutex_unlock(&msm_obj->lock);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
void msm_gem_put_vaddr(struct drm_gem_object *obj)
|
||||
{
|
||||
mutex_lock(&obj->dev->struct_mutex);
|
||||
msm_gem_put_vaddr_locked(obj);
|
||||
mutex_unlock(&obj->dev->struct_mutex);
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
|
||||
mutex_lock(&msm_obj->lock);
|
||||
WARN_ON(msm_obj->vmap_count < 1);
|
||||
msm_obj->vmap_count--;
|
||||
mutex_unlock(&msm_obj->lock);
|
||||
}
|
||||
|
||||
/* Update madvise status, returns true if not purged, else
|
||||
|
|
@ -453,15 +528,21 @@ int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv)
|
|||
{
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
|
||||
mutex_lock(&msm_obj->lock);
|
||||
|
||||
WARN_ON(!mutex_is_locked(&obj->dev->struct_mutex));
|
||||
|
||||
if (msm_obj->madv != __MSM_MADV_PURGED)
|
||||
msm_obj->madv = madv;
|
||||
|
||||
return (msm_obj->madv != __MSM_MADV_PURGED);
|
||||
madv = msm_obj->madv;
|
||||
|
||||
mutex_unlock(&msm_obj->lock);
|
||||
|
||||
return (madv != __MSM_MADV_PURGED);
|
||||
}
|
||||
|
||||
void msm_gem_purge(struct drm_gem_object *obj)
|
||||
void msm_gem_purge(struct drm_gem_object *obj, enum msm_gem_lock subclass)
|
||||
{
|
||||
struct drm_device *dev = obj->dev;
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
|
|
@ -470,9 +551,11 @@ void msm_gem_purge(struct drm_gem_object *obj)
|
|||
WARN_ON(!is_purgeable(msm_obj));
|
||||
WARN_ON(obj->import_attach);
|
||||
|
||||
mutex_lock_nested(&msm_obj->lock, subclass);
|
||||
|
||||
put_iova(obj);
|
||||
|
||||
msm_gem_vunmap(obj);
|
||||
msm_gem_vunmap_locked(obj);
|
||||
|
||||
put_pages(obj);
|
||||
|
||||
|
|
@ -490,12 +573,16 @@ void msm_gem_purge(struct drm_gem_object *obj)
|
|||
|
||||
invalidate_mapping_pages(file_inode(obj->filp)->i_mapping,
|
||||
0, (loff_t)-1);
|
||||
|
||||
mutex_unlock(&msm_obj->lock);
|
||||
}
|
||||
|
||||
void msm_gem_vunmap(struct drm_gem_object *obj)
|
||||
static void msm_gem_vunmap_locked(struct drm_gem_object *obj)
|
||||
{
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
|
||||
WARN_ON(!mutex_is_locked(&msm_obj->lock));
|
||||
|
||||
if (!msm_obj->vaddr || WARN_ON(!is_vunmapable(msm_obj)))
|
||||
return;
|
||||
|
||||
|
|
@ -503,6 +590,15 @@ void msm_gem_vunmap(struct drm_gem_object *obj)
|
|||
msm_obj->vaddr = NULL;
|
||||
}
|
||||
|
||||
void msm_gem_vunmap(struct drm_gem_object *obj, enum msm_gem_lock subclass)
|
||||
{
|
||||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
|
||||
mutex_lock_nested(&msm_obj->lock, subclass);
|
||||
msm_gem_vunmap_locked(obj);
|
||||
mutex_unlock(&msm_obj->lock);
|
||||
}
|
||||
|
||||
/* must be called before _move_to_active().. */
|
||||
int msm_gem_sync_object(struct drm_gem_object *obj,
|
||||
struct msm_fence_context *fctx, bool exclusive)
|
||||
|
|
@ -619,13 +715,12 @@ void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m)
|
|||
struct msm_gem_object *msm_obj = to_msm_bo(obj);
|
||||
struct reservation_object *robj = msm_obj->resv;
|
||||
struct reservation_object_list *fobj;
|
||||
struct msm_drm_private *priv = obj->dev->dev_private;
|
||||
struct dma_fence *fence;
|
||||
struct msm_gem_vma *vma;
|
||||
uint64_t off = drm_vma_node_start(&obj->vma_node);
|
||||
const char *madv;
|
||||
unsigned id;
|
||||
|
||||
WARN_ON(!mutex_is_locked(&obj->dev->struct_mutex));
|
||||
mutex_lock(&msm_obj->lock);
|
||||
|
||||
switch (msm_obj->madv) {
|
||||
case __MSM_MADV_PURGED:
|
||||
|
|
@ -645,8 +740,9 @@ void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m)
|
|||
obj->name, kref_read(&obj->refcount),
|
||||
off, msm_obj->vaddr);
|
||||
|
||||
for (id = 0; id < priv->num_aspaces; id++)
|
||||
seq_printf(m, " %08llx", msm_obj->domain[id].iova);
|
||||
/* FIXME: we need to print the address space here too */
|
||||
list_for_each_entry(vma, &msm_obj->vmas, list)
|
||||
seq_printf(m, " %08llx", vma->iova);
|
||||
|
||||
seq_printf(m, " %zu%s\n", obj->size, madv);
|
||||
|
||||
|
|
@ -665,6 +761,8 @@ void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m)
|
|||
if (fence)
|
||||
describe_fence(fence, "Exclusive", m);
|
||||
rcu_read_unlock();
|
||||
|
||||
mutex_unlock(&msm_obj->lock);
|
||||
}
|
||||
|
||||
void msm_gem_describe_objects(struct list_head *list, struct seq_file *m)
|
||||
|
|
@ -697,6 +795,8 @@ void msm_gem_free_object(struct drm_gem_object *obj)
|
|||
|
||||
list_del(&msm_obj->mm_list);
|
||||
|
||||
mutex_lock(&msm_obj->lock);
|
||||
|
||||
put_iova(obj);
|
||||
|
||||
if (obj->import_attach) {
|
||||
|
|
@ -711,7 +811,7 @@ void msm_gem_free_object(struct drm_gem_object *obj)
|
|||
|
||||
drm_prime_gem_destroy(obj, msm_obj->sgt);
|
||||
} else {
|
||||
msm_gem_vunmap(obj);
|
||||
msm_gem_vunmap_locked(obj);
|
||||
put_pages(obj);
|
||||
}
|
||||
|
||||
|
|
@ -720,6 +820,7 @@ void msm_gem_free_object(struct drm_gem_object *obj)
|
|||
|
||||
drm_gem_object_release(obj);
|
||||
|
||||
mutex_unlock(&msm_obj->lock);
|
||||
kfree(msm_obj);
|
||||
}
|
||||
|
||||
|
|
@ -730,14 +831,8 @@ int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
|
|||
struct drm_gem_object *obj;
|
||||
int ret;
|
||||
|
||||
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
obj = msm_gem_new(dev, size, flags);
|
||||
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
|
||||
if (IS_ERR(obj))
|
||||
return PTR_ERR(obj);
|
||||
|
||||
|
|
@ -752,13 +847,11 @@ int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
|
|||
static int msm_gem_new_impl(struct drm_device *dev,
|
||||
uint32_t size, uint32_t flags,
|
||||
struct reservation_object *resv,
|
||||
struct drm_gem_object **obj)
|
||||
struct drm_gem_object **obj,
|
||||
bool struct_mutex_locked)
|
||||
{
|
||||
struct msm_drm_private *priv = dev->dev_private;
|
||||
struct msm_gem_object *msm_obj;
|
||||
bool use_vram = false;
|
||||
|
||||
WARN_ON(!mutex_is_locked(&dev->struct_mutex));
|
||||
|
||||
switch (flags & MSM_BO_CACHE_MASK) {
|
||||
case MSM_BO_UNCACHED:
|
||||
|
|
@ -771,20 +864,11 @@ static int msm_gem_new_impl(struct drm_device *dev,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!iommu_present(&platform_bus_type))
|
||||
use_vram = true;
|
||||
else if ((flags & MSM_BO_STOLEN) && priv->vram.size)
|
||||
use_vram = true;
|
||||
|
||||
if (WARN_ON(use_vram && !priv->vram.size))
|
||||
return -EINVAL;
|
||||
|
||||
msm_obj = kzalloc(sizeof(*msm_obj), GFP_KERNEL);
|
||||
if (!msm_obj)
|
||||
return -ENOMEM;
|
||||
|
||||
if (use_vram)
|
||||
msm_obj->vram_node = &msm_obj->domain[0].node;
|
||||
mutex_init(&msm_obj->lock);
|
||||
|
||||
msm_obj->flags = flags;
|
||||
msm_obj->madv = MSM_MADV_WILLNEED;
|
||||
|
|
@ -797,48 +881,96 @@ static int msm_gem_new_impl(struct drm_device *dev,
|
|||
}
|
||||
|
||||
INIT_LIST_HEAD(&msm_obj->submit_entry);
|
||||
list_add_tail(&msm_obj->mm_list, &priv->inactive_list);
|
||||
INIT_LIST_HEAD(&msm_obj->vmas);
|
||||
|
||||
if (struct_mutex_locked) {
|
||||
WARN_ON(!mutex_is_locked(&dev->struct_mutex));
|
||||
list_add_tail(&msm_obj->mm_list, &priv->inactive_list);
|
||||
} else {
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
list_add_tail(&msm_obj->mm_list, &priv->inactive_list);
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
}
|
||||
|
||||
*obj = &msm_obj->base;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct drm_gem_object *msm_gem_new(struct drm_device *dev,
|
||||
uint32_t size, uint32_t flags)
|
||||
static struct drm_gem_object *_msm_gem_new(struct drm_device *dev,
|
||||
uint32_t size, uint32_t flags, bool struct_mutex_locked)
|
||||
{
|
||||
struct msm_drm_private *priv = dev->dev_private;
|
||||
struct drm_gem_object *obj = NULL;
|
||||
bool use_vram = false;
|
||||
int ret;
|
||||
|
||||
WARN_ON(!mutex_is_locked(&dev->struct_mutex));
|
||||
|
||||
size = PAGE_ALIGN(size);
|
||||
|
||||
if (!iommu_present(&platform_bus_type))
|
||||
use_vram = true;
|
||||
else if ((flags & MSM_BO_STOLEN) && priv->vram.size)
|
||||
use_vram = true;
|
||||
|
||||
if (WARN_ON(use_vram && !priv->vram.size))
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
/* Disallow zero sized objects as they make the underlying
|
||||
* infrastructure grumpy
|
||||
*/
|
||||
if (size == 0)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
ret = msm_gem_new_impl(dev, size, flags, NULL, &obj);
|
||||
ret = msm_gem_new_impl(dev, size, flags, NULL, &obj, struct_mutex_locked);
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
if (use_pages(obj)) {
|
||||
if (use_vram) {
|
||||
struct msm_gem_vma *vma;
|
||||
struct page **pages;
|
||||
|
||||
vma = add_vma(obj, NULL);
|
||||
if (IS_ERR(vma)) {
|
||||
ret = PTR_ERR(vma);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
to_msm_bo(obj)->vram_node = &vma->node;
|
||||
|
||||
drm_gem_private_object_init(dev, obj, size);
|
||||
|
||||
pages = get_pages(obj);
|
||||
if (IS_ERR(pages)) {
|
||||
ret = PTR_ERR(pages);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
vma->iova = physaddr(obj);
|
||||
} else {
|
||||
ret = drm_gem_object_init(dev, obj, size);
|
||||
if (ret)
|
||||
goto fail;
|
||||
} else {
|
||||
drm_gem_private_object_init(dev, obj, size);
|
||||
}
|
||||
|
||||
return obj;
|
||||
|
||||
fail:
|
||||
drm_gem_object_unreference(obj);
|
||||
drm_gem_object_unreference_unlocked(obj);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev,
|
||||
uint32_t size, uint32_t flags)
|
||||
{
|
||||
return _msm_gem_new(dev, size, flags, true);
|
||||
}
|
||||
|
||||
struct drm_gem_object *msm_gem_new(struct drm_device *dev,
|
||||
uint32_t size, uint32_t flags)
|
||||
{
|
||||
return _msm_gem_new(dev, size, flags, false);
|
||||
}
|
||||
|
||||
struct drm_gem_object *msm_gem_import(struct drm_device *dev,
|
||||
struct dma_buf *dmabuf, struct sg_table *sgt)
|
||||
{
|
||||
|
|
@ -855,11 +987,7 @@ struct drm_gem_object *msm_gem_import(struct drm_device *dev,
|
|||
|
||||
size = PAGE_ALIGN(dmabuf->size);
|
||||
|
||||
/* Take mutex so we can modify the inactive list in msm_gem_new_impl */
|
||||
mutex_lock(&dev->struct_mutex);
|
||||
ret = msm_gem_new_impl(dev, size, MSM_BO_WC, dmabuf->resv, &obj);
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
|
||||
ret = msm_gem_new_impl(dev, size, MSM_BO_WC, dmabuf->resv, &obj, false);
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
|
|
@ -868,17 +996,22 @@ struct drm_gem_object *msm_gem_import(struct drm_device *dev,
|
|||
npages = size / PAGE_SIZE;
|
||||
|
||||
msm_obj = to_msm_bo(obj);
|
||||
mutex_lock(&msm_obj->lock);
|
||||
msm_obj->sgt = sgt;
|
||||
msm_obj->pages = kvmalloc_array(npages, sizeof(struct page *), GFP_KERNEL);
|
||||
if (!msm_obj->pages) {
|
||||
mutex_unlock(&msm_obj->lock);
|
||||
ret = -ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
ret = drm_prime_sg_to_page_addr_arrays(sgt, msm_obj->pages, NULL, npages);
|
||||
if (ret)
|
||||
if (ret) {
|
||||
mutex_unlock(&msm_obj->lock);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
mutex_unlock(&msm_obj->lock);
|
||||
return obj;
|
||||
|
||||
fail:
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@ struct msm_gem_address_space {
|
|||
* and position mm_node->start is in # of pages:
|
||||
*/
|
||||
struct drm_mm mm;
|
||||
spinlock_t lock; /* Protects drm_mm node allocation/removal */
|
||||
struct msm_mmu *mmu;
|
||||
struct kref kref;
|
||||
};
|
||||
|
|
@ -38,6 +39,8 @@ struct msm_gem_address_space {
|
|||
struct msm_gem_vma {
|
||||
struct drm_mm_node node;
|
||||
uint64_t iova;
|
||||
struct msm_gem_address_space *aspace;
|
||||
struct list_head list; /* node in msm_gem_object::vmas */
|
||||
};
|
||||
|
||||
struct msm_gem_object {
|
||||
|
|
@ -77,7 +80,7 @@ struct msm_gem_object {
|
|||
struct sg_table *sgt;
|
||||
void *vaddr;
|
||||
|
||||
struct msm_gem_vma domain[NUM_DOMAINS];
|
||||
struct list_head vmas; /* list of msm_gem_vma */
|
||||
|
||||
/* normally (resv == &_resv) except for imported bo's */
|
||||
struct reservation_object *resv;
|
||||
|
|
@ -87,6 +90,7 @@ struct msm_gem_object {
|
|||
* an IOMMU. Also used for stolen/splashscreen buffer.
|
||||
*/
|
||||
struct drm_mm_node *vram_node;
|
||||
struct mutex lock; /* Protects resources associated with bo */
|
||||
};
|
||||
#define to_msm_bo(x) container_of(x, struct msm_gem_object, base)
|
||||
|
||||
|
|
@ -97,6 +101,7 @@ static inline bool is_active(struct msm_gem_object *msm_obj)
|
|||
|
||||
static inline bool is_purgeable(struct msm_gem_object *msm_obj)
|
||||
{
|
||||
WARN_ON(!mutex_is_locked(&msm_obj->base.dev->struct_mutex));
|
||||
return (msm_obj->madv == MSM_MADV_DONTNEED) && msm_obj->sgt &&
|
||||
!msm_obj->base.dma_buf && !msm_obj->base.import_attach;
|
||||
}
|
||||
|
|
@ -106,6 +111,25 @@ static inline bool is_vunmapable(struct msm_gem_object *msm_obj)
|
|||
return (msm_obj->vmap_count == 0) && msm_obj->vaddr;
|
||||
}
|
||||
|
||||
/* The shrinker can be triggered while we hold objA->lock, and need
|
||||
* to grab objB->lock to purge it. Lockdep just sees these as a single
|
||||
* class of lock, so we use subclasses to teach it the difference.
|
||||
*
|
||||
* OBJ_LOCK_NORMAL is implicit (ie. normal mutex_lock() call), and
|
||||
* OBJ_LOCK_SHRINKER is used by shrinker.
|
||||
*
|
||||
* It is *essential* that we never go down paths that could trigger the
|
||||
* shrinker for a purgable object. This is ensured by checking that
|
||||
* msm_obj->madv == MSM_MADV_WILLNEED.
|
||||
*/
|
||||
enum msm_gem_lock {
|
||||
OBJ_LOCK_NORMAL,
|
||||
OBJ_LOCK_SHRINKER,
|
||||
};
|
||||
|
||||
void msm_gem_purge(struct drm_gem_object *obj, enum msm_gem_lock subclass);
|
||||
void msm_gem_vunmap(struct drm_gem_object *obj, enum msm_gem_lock subclass);
|
||||
|
||||
/* Created per submit-ioctl, to track bo's and cmdstream bufs, etc,
|
||||
* associated with the cmdstream submission for synchronization (and
|
||||
* make it easier to unwind when things go wrong, etc). This only
|
||||
|
|
|
|||
|
|
@ -20,6 +20,18 @@
|
|||
|
||||
static bool msm_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
|
||||
{
|
||||
/* NOTE: we are *closer* to being able to get rid of
|
||||
* mutex_trylock_recursive().. the msm_gem code itself does
|
||||
* not need struct_mutex, although codepaths that can trigger
|
||||
* shrinker are still called in code-paths that hold the
|
||||
* struct_mutex.
|
||||
*
|
||||
* Also, msm_obj->madv is protected by struct_mutex.
|
||||
*
|
||||
* The next step is probably split out a seperate lock for
|
||||
* protecting inactive_list, so that shrinker does not need
|
||||
* struct_mutex.
|
||||
*/
|
||||
switch (mutex_trylock_recursive(&dev->struct_mutex)) {
|
||||
case MUTEX_TRYLOCK_FAILED:
|
||||
return false;
|
||||
|
|
@ -77,7 +89,7 @@ msm_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
|
|||
if (freed >= sc->nr_to_scan)
|
||||
break;
|
||||
if (is_purgeable(msm_obj)) {
|
||||
msm_gem_purge(&msm_obj->base);
|
||||
msm_gem_purge(&msm_obj->base, OBJ_LOCK_SHRINKER);
|
||||
freed += msm_obj->base.size >> PAGE_SHIFT;
|
||||
}
|
||||
}
|
||||
|
|
@ -106,7 +118,7 @@ msm_gem_shrinker_vmap(struct notifier_block *nb, unsigned long event, void *ptr)
|
|||
|
||||
list_for_each_entry(msm_obj, &priv->inactive_list, mm_list) {
|
||||
if (is_vunmapable(msm_obj)) {
|
||||
msm_gem_vunmap(&msm_obj->base);
|
||||
msm_gem_vunmap(&msm_obj->base, OBJ_LOCK_SHRINKER);
|
||||
/* since we don't know any better, lets bail after a few
|
||||
* and if necessary the shrinker will be invoked again.
|
||||
* Seems better than unmapping *everything*
|
||||
|
|
|
|||
|
|
@ -31,11 +31,14 @@
|
|||
#define BO_PINNED 0x2000
|
||||
|
||||
static struct msm_gem_submit *submit_create(struct drm_device *dev,
|
||||
struct msm_gpu *gpu, int nr_bos, int nr_cmds)
|
||||
struct msm_gpu *gpu, uint32_t nr_bos, uint32_t nr_cmds)
|
||||
{
|
||||
struct msm_gem_submit *submit;
|
||||
int sz = sizeof(*submit) + (nr_bos * sizeof(submit->bos[0])) +
|
||||
(nr_cmds * sizeof(*submit->cmd));
|
||||
uint64_t sz = sizeof(*submit) + (nr_bos * sizeof(submit->bos[0])) +
|
||||
(nr_cmds * sizeof(submit->cmd[0]));
|
||||
|
||||
if (sz > SIZE_MAX)
|
||||
return NULL;
|
||||
|
||||
submit = kmalloc(sz, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
|
||||
if (!submit)
|
||||
|
|
@ -158,7 +161,7 @@ static void submit_unlock_unpin_bo(struct msm_gem_submit *submit, int i)
|
|||
struct msm_gem_object *msm_obj = submit->bos[i].obj;
|
||||
|
||||
if (submit->bos[i].flags & BO_PINNED)
|
||||
msm_gem_put_iova(&msm_obj->base, submit->gpu->id);
|
||||
msm_gem_put_iova(&msm_obj->base, submit->gpu->aspace);
|
||||
|
||||
if (submit->bos[i].flags & BO_LOCKED)
|
||||
ww_mutex_unlock(&msm_obj->resv->lock);
|
||||
|
|
@ -245,8 +248,8 @@ static int submit_pin_objects(struct msm_gem_submit *submit)
|
|||
uint64_t iova;
|
||||
|
||||
/* if locking succeeded, pin bo: */
|
||||
ret = msm_gem_get_iova_locked(&msm_obj->base,
|
||||
submit->gpu->id, &iova);
|
||||
ret = msm_gem_get_iova(&msm_obj->base,
|
||||
submit->gpu->aspace, &iova);
|
||||
|
||||
if (ret)
|
||||
break;
|
||||
|
|
@ -301,7 +304,7 @@ static int submit_reloc(struct msm_gem_submit *submit, struct msm_gem_object *ob
|
|||
/* For now, just map the entire thing. Eventually we probably
|
||||
* to do it page-by-page, w/ kmap() if not vmap()d..
|
||||
*/
|
||||
ptr = msm_gem_get_vaddr_locked(&obj->base);
|
||||
ptr = msm_gem_get_vaddr(&obj->base);
|
||||
|
||||
if (IS_ERR(ptr)) {
|
||||
ret = PTR_ERR(ptr);
|
||||
|
|
@ -359,7 +362,7 @@ static int submit_reloc(struct msm_gem_submit *submit, struct msm_gem_object *ob
|
|||
}
|
||||
|
||||
out:
|
||||
msm_gem_put_vaddr_locked(&obj->base);
|
||||
msm_gem_put_vaddr(&obj->base);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -50,7 +50,9 @@ msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
|
|||
aspace->mmu->funcs->unmap(aspace->mmu, vma->iova, sgt, size);
|
||||
}
|
||||
|
||||
spin_lock(&aspace->lock);
|
||||
drm_mm_remove_node(&vma->node);
|
||||
spin_unlock(&aspace->lock);
|
||||
|
||||
vma->iova = 0;
|
||||
|
||||
|
|
@ -63,10 +65,15 @@ msm_gem_map_vma(struct msm_gem_address_space *aspace,
|
|||
{
|
||||
int ret;
|
||||
|
||||
if (WARN_ON(drm_mm_node_allocated(&vma->node)))
|
||||
spin_lock(&aspace->lock);
|
||||
if (WARN_ON(drm_mm_node_allocated(&vma->node))) {
|
||||
spin_unlock(&aspace->lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
ret = drm_mm_insert_node(&aspace->mm, &vma->node, npages);
|
||||
spin_unlock(&aspace->lock);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -94,6 +101,7 @@ msm_gem_address_space_create(struct device *dev, struct iommu_domain *domain,
|
|||
if (!aspace)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
spin_lock_init(&aspace->lock);
|
||||
aspace->name = name;
|
||||
aspace->mmu = msm_iommu_new(dev, domain);
|
||||
|
||||
|
|
|
|||
|
|
@ -203,6 +203,8 @@ int msm_gpu_hw_init(struct msm_gpu *gpu)
|
|||
{
|
||||
int ret;
|
||||
|
||||
WARN_ON(!mutex_is_locked(&gpu->dev->struct_mutex));
|
||||
|
||||
if (!gpu->needs_hw_init)
|
||||
return 0;
|
||||
|
||||
|
|
@ -414,7 +416,7 @@ static void retire_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
|
|||
struct msm_gem_object *msm_obj = submit->bos[i].obj;
|
||||
/* move to inactive: */
|
||||
msm_gem_move_to_inactive(&msm_obj->base);
|
||||
msm_gem_put_iova(&msm_obj->base, gpu->id);
|
||||
msm_gem_put_iova(&msm_obj->base, gpu->aspace);
|
||||
drm_gem_object_unreference(&msm_obj->base);
|
||||
}
|
||||
|
||||
|
|
@ -495,8 +497,8 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
|
|||
|
||||
/* submit takes a reference to the bo and iova until retired: */
|
||||
drm_gem_object_reference(&msm_obj->base);
|
||||
msm_gem_get_iova_locked(&msm_obj->base,
|
||||
submit->gpu->id, &iova);
|
||||
msm_gem_get_iova(&msm_obj->base,
|
||||
submit->gpu->aspace, &iova);
|
||||
|
||||
if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE)
|
||||
msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence);
|
||||
|
|
@ -562,7 +564,7 @@ static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
|
|||
|
||||
int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
|
||||
struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
|
||||
const char *name, const char *ioname, const char *irqname, int ringsz)
|
||||
const char *name, struct msm_gpu_config *config)
|
||||
{
|
||||
struct iommu_domain *iommu;
|
||||
int ret;
|
||||
|
|
@ -593,14 +595,14 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
|
|||
|
||||
|
||||
/* Map registers: */
|
||||
gpu->mmio = msm_ioremap(pdev, ioname, name);
|
||||
gpu->mmio = msm_ioremap(pdev, config->ioname, name);
|
||||
if (IS_ERR(gpu->mmio)) {
|
||||
ret = PTR_ERR(gpu->mmio);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/* Get Interrupt: */
|
||||
gpu->irq = platform_get_irq_byname(pdev, irqname);
|
||||
gpu->irq = platform_get_irq_byname(pdev, config->irqname);
|
||||
if (gpu->irq < 0) {
|
||||
ret = gpu->irq;
|
||||
dev_err(drm->dev, "failed to get irq: %d\n", ret);
|
||||
|
|
@ -640,9 +642,8 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
|
|||
*/
|
||||
iommu = iommu_domain_alloc(&platform_bus_type);
|
||||
if (iommu) {
|
||||
/* TODO 32b vs 64b address space.. */
|
||||
iommu->geometry.aperture_start = SZ_16M;
|
||||
iommu->geometry.aperture_end = 0xffffffff;
|
||||
iommu->geometry.aperture_start = config->va_start;
|
||||
iommu->geometry.aperture_end = config->va_end;
|
||||
|
||||
dev_info(drm->dev, "%s: using IOMMU\n", name);
|
||||
gpu->aspace = msm_gem_address_space_create(&pdev->dev,
|
||||
|
|
@ -658,13 +659,9 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
|
|||
} else {
|
||||
dev_info(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name);
|
||||
}
|
||||
gpu->id = msm_register_address_space(drm, gpu->aspace);
|
||||
|
||||
|
||||
/* Create ringbuffer: */
|
||||
mutex_lock(&drm->struct_mutex);
|
||||
gpu->rb = msm_ringbuffer_new(gpu, ringsz);
|
||||
mutex_unlock(&drm->struct_mutex);
|
||||
gpu->rb = msm_ringbuffer_new(gpu, config->ringsz);
|
||||
if (IS_ERR(gpu->rb)) {
|
||||
ret = PTR_ERR(gpu->rb);
|
||||
gpu->rb = NULL;
|
||||
|
|
@ -693,7 +690,7 @@ void msm_gpu_cleanup(struct msm_gpu *gpu)
|
|||
|
||||
if (gpu->rb) {
|
||||
if (gpu->rb_iova)
|
||||
msm_gem_put_iova(gpu->rb->bo, gpu->id);
|
||||
msm_gem_put_iova(gpu->rb->bo, gpu->aspace);
|
||||
msm_ringbuffer_destroy(gpu->rb);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -28,6 +28,14 @@
|
|||
struct msm_gem_submit;
|
||||
struct msm_gpu_perfcntr;
|
||||
|
||||
struct msm_gpu_config {
|
||||
const char *ioname;
|
||||
const char *irqname;
|
||||
uint64_t va_start;
|
||||
uint64_t va_end;
|
||||
unsigned int ringsz;
|
||||
};
|
||||
|
||||
/* So far, with hardware that I've seen to date, we can have:
|
||||
* + zero, one, or two z180 2d cores
|
||||
* + a3xx or a2xx 3d core, which share a common CP (the firmware
|
||||
|
|
@ -50,7 +58,6 @@ struct msm_gpu_funcs {
|
|||
void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
|
||||
struct msm_file_private *ctx);
|
||||
void (*flush)(struct msm_gpu *gpu);
|
||||
bool (*idle)(struct msm_gpu *gpu);
|
||||
irqreturn_t (*irq)(struct msm_gpu *irq);
|
||||
uint32_t (*last_fence)(struct msm_gpu *gpu);
|
||||
void (*recover)(struct msm_gpu *gpu);
|
||||
|
|
@ -99,7 +106,6 @@ struct msm_gpu {
|
|||
int irq;
|
||||
|
||||
struct msm_gem_address_space *aspace;
|
||||
int id;
|
||||
|
||||
/* Power Control: */
|
||||
struct regulator *gpu_reg, *gpu_cx;
|
||||
|
|
@ -209,7 +215,8 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
|
|||
|
||||
int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
|
||||
struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
|
||||
const char *name, const char *ioname, const char *irqname, int ringsz);
|
||||
const char *name, struct msm_gpu_config *config);
|
||||
|
||||
void msm_gpu_cleanup(struct msm_gpu *gpu);
|
||||
|
||||
struct msm_gpu *adreno_load_gpu(struct drm_device *dev);
|
||||
|
|
|
|||
|
|
@ -72,6 +72,9 @@ struct msm_kms {
|
|||
|
||||
/* irq number to be passed on to drm_irq_install */
|
||||
int irq;
|
||||
|
||||
/* mapper-id used to request GEM buffer mapped for scanout: */
|
||||
struct msm_gem_address_space *aspace;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -268,7 +268,7 @@ static void snapshot_buf(struct msm_rd_state *rd,
|
|||
struct msm_gem_object *obj = submit->bos[idx].obj;
|
||||
const char *buf;
|
||||
|
||||
buf = msm_gem_get_vaddr_locked(&obj->base);
|
||||
buf = msm_gem_get_vaddr(&obj->base);
|
||||
if (IS_ERR(buf))
|
||||
return;
|
||||
|
||||
|
|
@ -283,7 +283,7 @@ static void snapshot_buf(struct msm_rd_state *rd,
|
|||
(uint32_t[3]){ iova, size, iova >> 32 }, 12);
|
||||
rd_write_section(rd, RD_BUFFER_CONTENTS, buf, size);
|
||||
|
||||
msm_gem_put_vaddr_locked(&obj->base);
|
||||
msm_gem_put_vaddr(&obj->base);
|
||||
}
|
||||
|
||||
/* called under struct_mutex */
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int size)
|
|||
goto fail;
|
||||
}
|
||||
|
||||
ring->start = msm_gem_get_vaddr_locked(ring->bo);
|
||||
ring->start = msm_gem_get_vaddr(ring->bo);
|
||||
if (IS_ERR(ring->start)) {
|
||||
ret = PTR_ERR(ring->start);
|
||||
goto fail;
|
||||
|
|
|
|||
|
|
@ -104,10 +104,14 @@ struct drm_msm_gem_new {
|
|||
__u32 handle; /* out */
|
||||
};
|
||||
|
||||
#define MSM_INFO_IOVA 0x01
|
||||
|
||||
#define MSM_INFO_FLAGS (MSM_INFO_IOVA)
|
||||
|
||||
struct drm_msm_gem_info {
|
||||
__u32 handle; /* in */
|
||||
__u32 pad;
|
||||
__u64 offset; /* out, offset to pass to mmap() */
|
||||
__u32 flags; /* in - combination of MSM_INFO_* flags */
|
||||
__u64 offset; /* out, mmap() offset or iova */
|
||||
};
|
||||
|
||||
#define MSM_PREP_READ 0x01
|
||||
|
|
@ -261,7 +265,6 @@ struct drm_msm_gem_madvise {
|
|||
#define DRM_MSM_GEM_SUBMIT 0x06
|
||||
#define DRM_MSM_WAIT_FENCE 0x07
|
||||
#define DRM_MSM_GEM_MADVISE 0x08
|
||||
#define DRM_MSM_NUM_IOCTLS 0x09
|
||||
|
||||
#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
|
||||
#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
|
||||
|
|
|
|||
Loading…
Reference in a new issue