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https://github.com/torvalds/linux
synced 2024-09-28 07:20:56 +00:00
sparc64: Fully support both performance counters.
Add the rest of the conflict detection and resolution logic necessary to support more than one counter at a time on sparc64. The structure and implementation closely mimicks that of powerpc. Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
parent
4f6dbe4ac0
commit
e7bef6b04c
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@ -55,16 +55,49 @@
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#define PIC_UPPER_INDEX 0
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#define PIC_LOWER_INDEX 1
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#define PIC_NO_INDEX -1
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struct cpu_hw_events {
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struct perf_event *events[MAX_HWEVENTS];
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unsigned long used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
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unsigned long active_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
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/* Number of events currently scheduled onto this cpu.
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* This tells how many entries in the arrays below
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* are valid.
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*/
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int n_events;
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/* Number of new events added since the last hw_perf_disable().
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* This works because the perf event layer always adds new
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* events inside of a perf_{disable,enable}() sequence.
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*/
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int n_added;
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/* Array of events current scheduled on this cpu. */
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struct perf_event *event[MAX_HWEVENTS];
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/* Array of encoded longs, specifying the %pcr register
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* encoding and the mask of PIC counters this even can
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* be scheduled on. See perf_event_encode() et al.
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*/
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unsigned long events[MAX_HWEVENTS];
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/* The current counter index assigned to an event. When the
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* event hasn't been programmed into the cpu yet, this will
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* hold PIC_NO_INDEX. The event->hw.idx value tells us where
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* we ought to schedule the event.
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*/
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int current_idx[MAX_HWEVENTS];
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/* Software copy of %pcr register on this cpu. */
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u64 pcr;
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/* Enabled/disable state. */
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int enabled;
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};
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DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, };
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/* An event map describes the characteristics of a performance
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* counter event. In particular it gives the encoding as well as
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* a mask telling which counters the event can be measured on.
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*/
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struct perf_event_map {
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u16 encoding;
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u8 pic_mask;
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@ -73,15 +106,20 @@ struct perf_event_map {
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#define PIC_LOWER 0x02
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};
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/* Encode a perf_event_map entry into a long. */
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static unsigned long perf_event_encode(const struct perf_event_map *pmap)
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{
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return ((unsigned long) pmap->encoding << 16) | pmap->pic_mask;
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}
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static void perf_event_decode(unsigned long val, u16 *enc, u8 *msk)
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static u8 perf_event_get_msk(unsigned long val)
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{
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*msk = val & 0xff;
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*enc = val >> 16;
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return val & 0xff;
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}
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static u64 perf_event_get_enc(unsigned long val)
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{
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return val >> 16;
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}
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#define C(x) PERF_COUNT_HW_CACHE_##x
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@ -495,53 +533,6 @@ static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw
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pcr_ops->write(cpuc->pcr);
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}
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void hw_perf_enable(void)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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u64 val;
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int i;
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if (cpuc->enabled)
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return;
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cpuc->enabled = 1;
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barrier();
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val = cpuc->pcr;
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for (i = 0; i < MAX_HWEVENTS; i++) {
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struct perf_event *cp = cpuc->events[i];
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struct hw_perf_event *hwc;
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if (!cp)
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continue;
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hwc = &cp->hw;
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val |= hwc->config_base;
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}
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cpuc->pcr = val;
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pcr_ops->write(cpuc->pcr);
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}
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void hw_perf_disable(void)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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u64 val;
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if (!cpuc->enabled)
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return;
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cpuc->enabled = 0;
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val = cpuc->pcr;
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val &= ~(PCR_UTRACE | PCR_STRACE |
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sparc_pmu->hv_bit | sparc_pmu->irq_bit);
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cpuc->pcr = val;
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pcr_ops->write(cpuc->pcr);
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}
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static u32 read_pmc(int idx)
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{
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u64 val;
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@ -570,6 +561,30 @@ static void write_pmc(int idx, u64 val)
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write_pic(pic);
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}
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static u64 sparc_perf_event_update(struct perf_event *event,
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struct hw_perf_event *hwc, int idx)
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{
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int shift = 64 - 32;
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u64 prev_raw_count, new_raw_count;
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s64 delta;
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again:
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prev_raw_count = atomic64_read(&hwc->prev_count);
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new_raw_count = read_pmc(idx);
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if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
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new_raw_count) != prev_raw_count)
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goto again;
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delta = (new_raw_count << shift) - (prev_raw_count << shift);
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delta >>= shift;
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atomic64_add(delta, &event->count);
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atomic64_sub(delta, &hwc->period_left);
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return new_raw_count;
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}
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static int sparc_perf_event_set_period(struct perf_event *event,
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struct hw_perf_event *hwc, int idx)
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{
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@ -602,81 +617,166 @@ static int sparc_perf_event_set_period(struct perf_event *event,
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return ret;
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}
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static int sparc_pmu_enable(struct perf_event *event)
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/* If performance event entries have been added, move existing
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* events around (if necessary) and then assign new entries to
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* counters.
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*/
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static u64 maybe_change_configuration(struct cpu_hw_events *cpuc, u64 pcr)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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int i;
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if (test_and_set_bit(idx, cpuc->used_mask))
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return -EAGAIN;
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if (!cpuc->n_added)
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goto out;
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sparc_pmu_disable_event(cpuc, hwc, idx);
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/* Read in the counters which are moving. */
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for (i = 0; i < cpuc->n_events; i++) {
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struct perf_event *cp = cpuc->event[i];
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cpuc->events[idx] = event;
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set_bit(idx, cpuc->active_mask);
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if (cpuc->current_idx[i] != PIC_NO_INDEX &&
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cpuc->current_idx[i] != cp->hw.idx) {
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sparc_perf_event_update(cp, &cp->hw,
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cpuc->current_idx[i]);
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cpuc->current_idx[i] = PIC_NO_INDEX;
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}
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}
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sparc_perf_event_set_period(event, hwc, idx);
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sparc_pmu_enable_event(cpuc, hwc, idx);
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perf_event_update_userpage(event);
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return 0;
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/* Assign to counters all unassigned events. */
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for (i = 0; i < cpuc->n_events; i++) {
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struct perf_event *cp = cpuc->event[i];
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struct hw_perf_event *hwc = &cp->hw;
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int idx = hwc->idx;
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u64 enc;
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if (cpuc->current_idx[i] != PIC_NO_INDEX)
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continue;
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sparc_perf_event_set_period(cp, hwc, idx);
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cpuc->current_idx[i] = idx;
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enc = perf_event_get_enc(cpuc->events[i]);
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pcr |= event_encoding(enc, idx);
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}
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out:
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return pcr;
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}
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static u64 sparc_perf_event_update(struct perf_event *event,
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struct hw_perf_event *hwc, int idx)
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void hw_perf_enable(void)
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{
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int shift = 64 - 32;
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u64 prev_raw_count, new_raw_count;
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s64 delta;
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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u64 pcr;
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again:
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prev_raw_count = atomic64_read(&hwc->prev_count);
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new_raw_count = read_pmc(idx);
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if (cpuc->enabled)
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return;
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if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
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new_raw_count) != prev_raw_count)
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goto again;
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cpuc->enabled = 1;
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barrier();
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delta = (new_raw_count << shift) - (prev_raw_count << shift);
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delta >>= shift;
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pcr = cpuc->pcr;
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if (!cpuc->n_events) {
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pcr = 0;
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} else {
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pcr = maybe_change_configuration(cpuc, pcr);
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atomic64_add(delta, &event->count);
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atomic64_sub(delta, &hwc->period_left);
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/* We require that all of the events have the same
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* configuration, so just fetch the settings from the
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* first entry.
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*/
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cpuc->pcr = pcr | cpuc->event[0]->hw.config_base;
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}
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return new_raw_count;
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pcr_ops->write(cpuc->pcr);
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}
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void hw_perf_disable(void)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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u64 val;
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if (!cpuc->enabled)
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return;
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cpuc->enabled = 0;
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cpuc->n_added = 0;
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val = cpuc->pcr;
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val &= ~(PCR_UTRACE | PCR_STRACE |
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sparc_pmu->hv_bit | sparc_pmu->irq_bit);
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cpuc->pcr = val;
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pcr_ops->write(cpuc->pcr);
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}
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static void sparc_pmu_disable(struct perf_event *event)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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unsigned long flags;
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int i;
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clear_bit(idx, cpuc->active_mask);
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sparc_pmu_disable_event(cpuc, hwc, idx);
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local_irq_save(flags);
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perf_disable();
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barrier();
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for (i = 0; i < cpuc->n_events; i++) {
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if (event == cpuc->event[i]) {
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int idx = cpuc->current_idx[i];
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sparc_perf_event_update(event, hwc, idx);
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cpuc->events[idx] = NULL;
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clear_bit(idx, cpuc->used_mask);
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/* Shift remaining entries down into
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* the existing slot.
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*/
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while (++i < cpuc->n_events) {
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cpuc->event[i - 1] = cpuc->event[i];
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cpuc->events[i - 1] = cpuc->events[i];
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cpuc->current_idx[i - 1] =
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cpuc->current_idx[i];
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}
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perf_event_update_userpage(event);
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/* Absorb the final count and turn off the
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* event.
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*/
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sparc_pmu_disable_event(cpuc, hwc, idx);
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barrier();
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sparc_perf_event_update(event, hwc, idx);
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perf_event_update_userpage(event);
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cpuc->n_events--;
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break;
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}
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}
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perf_enable();
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local_irq_restore(flags);
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}
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static int active_event_index(struct cpu_hw_events *cpuc,
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struct perf_event *event)
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{
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int i;
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for (i = 0; i < cpuc->n_events; i++) {
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if (cpuc->event[i] == event)
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break;
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}
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BUG_ON(i == cpuc->n_events);
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return cpuc->current_idx[i];
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}
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static void sparc_pmu_read(struct perf_event *event)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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int idx = active_event_index(cpuc, event);
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struct hw_perf_event *hwc = &event->hw;
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sparc_perf_event_update(event, hwc, hwc->idx);
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sparc_perf_event_update(event, hwc, idx);
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}
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static void sparc_pmu_unthrottle(struct perf_event *event)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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int idx = active_event_index(cpuc, event);
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struct hw_perf_event *hwc = &event->hw;
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sparc_pmu_enable_event(cpuc, hwc, hwc->idx);
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sparc_pmu_enable_event(cpuc, hwc, idx);
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}
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static atomic_t active_events = ATOMIC_INIT(0);
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@ -754,43 +854,75 @@ static void hw_perf_event_destroy(struct perf_event *event)
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/* Make sure all events can be scheduled into the hardware at
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* the same time. This is simplified by the fact that we only
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* need to support 2 simultaneous HW events.
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*
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* As a side effect, the evts[]->hw.idx values will be assigned
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* on success. These are pending indexes. When the events are
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* actually programmed into the chip, these values will propagate
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* to the per-cpu cpuc->current_idx[] slots, see the code in
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* maybe_change_configuration() for details.
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*/
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static int sparc_check_constraints(unsigned long *events, int n_ev)
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static int sparc_check_constraints(struct perf_event **evts,
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unsigned long *events, int n_ev)
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{
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if (n_ev <= perf_max_events) {
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u8 msk1, msk2;
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u16 dummy;
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u8 msk0 = 0, msk1 = 0;
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int idx0 = 0;
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if (n_ev == 1)
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return 0;
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BUG_ON(n_ev != 2);
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perf_event_decode(events[0], &dummy, &msk1);
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perf_event_decode(events[1], &dummy, &msk2);
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/* This case is possible when we are invoked from
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* hw_perf_group_sched_in().
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*/
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if (!n_ev)
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return 0;
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/* If both events can go on any counter, OK. */
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if (msk1 == (PIC_UPPER | PIC_LOWER) &&
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msk2 == (PIC_UPPER | PIC_LOWER))
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return 0;
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if (n_ev > perf_max_events)
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return -1;
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/* If one event is limited to a specific counter,
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* and the other can go on both, OK.
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*/
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if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) &&
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msk2 == (PIC_UPPER | PIC_LOWER))
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return 0;
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if ((msk2 == PIC_UPPER || msk2 == PIC_LOWER) &&
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msk1 == (PIC_UPPER | PIC_LOWER))
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return 0;
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msk0 = perf_event_get_msk(events[0]);
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if (n_ev == 1) {
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if (msk0 & PIC_LOWER)
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idx0 = 1;
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goto success;
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}
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BUG_ON(n_ev != 2);
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msk1 = perf_event_get_msk(events[1]);
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/* If the events are fixed to different counters, OK. */
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if ((msk1 == PIC_UPPER && msk2 == PIC_LOWER) ||
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(msk1 == PIC_LOWER && msk2 == PIC_UPPER))
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return 0;
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/* If both events can go on any counter, OK. */
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if (msk0 == (PIC_UPPER | PIC_LOWER) &&
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msk1 == (PIC_UPPER | PIC_LOWER))
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goto success;
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/* Otherwise, there is a conflict. */
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/* If one event is limited to a specific counter,
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* and the other can go on both, OK.
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*/
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if ((msk0 == PIC_UPPER || msk0 == PIC_LOWER) &&
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msk1 == (PIC_UPPER | PIC_LOWER)) {
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if (msk0 & PIC_LOWER)
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idx0 = 1;
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goto success;
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}
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if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) &&
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msk0 == (PIC_UPPER | PIC_LOWER)) {
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if (msk1 & PIC_UPPER)
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idx0 = 1;
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goto success;
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}
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/* If the events are fixed to different counters, OK. */
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if ((msk0 == PIC_UPPER && msk1 == PIC_LOWER) ||
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(msk0 == PIC_LOWER && msk1 == PIC_UPPER)) {
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if (msk0 & PIC_LOWER)
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idx0 = 1;
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goto success;
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}
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/* Otherwise, there is a conflict. */
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return -1;
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success:
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evts[0]->hw.idx = idx0;
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if (n_ev == 2)
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evts[1]->hw.idx = idx0 ^ 1;
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return 0;
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||||
}
|
||||
|
||||
static int check_excludes(struct perf_event **evts, int n_prev, int n_new)
|
||||
|
|
@ -822,7 +954,8 @@ static int check_excludes(struct perf_event **evts, int n_prev, int n_new)
|
|||
}
|
||||
|
||||
static int collect_events(struct perf_event *group, int max_count,
|
||||
struct perf_event *evts[], unsigned long *events)
|
||||
struct perf_event *evts[], unsigned long *events,
|
||||
int *current_idx)
|
||||
{
|
||||
struct perf_event *event;
|
||||
int n = 0;
|
||||
|
|
@ -831,7 +964,8 @@ static int collect_events(struct perf_event *group, int max_count,
|
|||
if (n >= max_count)
|
||||
return -1;
|
||||
evts[n] = group;
|
||||
events[n++] = group->hw.event_base;
|
||||
events[n] = group->hw.event_base;
|
||||
current_idx[n++] = PIC_NO_INDEX;
|
||||
}
|
||||
list_for_each_entry(event, &group->sibling_list, group_entry) {
|
||||
if (!is_software_event(event) &&
|
||||
|
|
@ -839,20 +973,100 @@ static int collect_events(struct perf_event *group, int max_count,
|
|||
if (n >= max_count)
|
||||
return -1;
|
||||
evts[n] = event;
|
||||
events[n++] = event->hw.event_base;
|
||||
events[n] = event->hw.event_base;
|
||||
current_idx[n++] = PIC_NO_INDEX;
|
||||
}
|
||||
}
|
||||
return n;
|
||||
}
|
||||
|
||||
static void event_sched_in(struct perf_event *event, int cpu)
|
||||
{
|
||||
event->state = PERF_EVENT_STATE_ACTIVE;
|
||||
event->oncpu = cpu;
|
||||
event->tstamp_running += event->ctx->time - event->tstamp_stopped;
|
||||
if (is_software_event(event))
|
||||
event->pmu->enable(event);
|
||||
}
|
||||
|
||||
int hw_perf_group_sched_in(struct perf_event *group_leader,
|
||||
struct perf_cpu_context *cpuctx,
|
||||
struct perf_event_context *ctx, int cpu)
|
||||
{
|
||||
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
||||
struct perf_event *sub;
|
||||
int n0, n;
|
||||
|
||||
if (!sparc_pmu)
|
||||
return 0;
|
||||
|
||||
n0 = cpuc->n_events;
|
||||
n = collect_events(group_leader, perf_max_events - n0,
|
||||
&cpuc->event[n0], &cpuc->events[n0],
|
||||
&cpuc->current_idx[n0]);
|
||||
if (n < 0)
|
||||
return -EAGAIN;
|
||||
if (check_excludes(cpuc->event, n0, n))
|
||||
return -EINVAL;
|
||||
if (sparc_check_constraints(cpuc->event, cpuc->events, n + n0))
|
||||
return -EAGAIN;
|
||||
cpuc->n_events = n0 + n;
|
||||
cpuc->n_added += n;
|
||||
|
||||
cpuctx->active_oncpu += n;
|
||||
n = 1;
|
||||
event_sched_in(group_leader, cpu);
|
||||
list_for_each_entry(sub, &group_leader->sibling_list, group_entry) {
|
||||
if (sub->state != PERF_EVENT_STATE_OFF) {
|
||||
event_sched_in(sub, cpu);
|
||||
n++;
|
||||
}
|
||||
}
|
||||
ctx->nr_active += n;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int sparc_pmu_enable(struct perf_event *event)
|
||||
{
|
||||
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
||||
int n0, ret = -EAGAIN;
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
perf_disable();
|
||||
|
||||
n0 = cpuc->n_events;
|
||||
if (n0 >= perf_max_events)
|
||||
goto out;
|
||||
|
||||
cpuc->event[n0] = event;
|
||||
cpuc->events[n0] = event->hw.event_base;
|
||||
cpuc->current_idx[n0] = PIC_NO_INDEX;
|
||||
|
||||
if (check_excludes(cpuc->event, n0, 1))
|
||||
goto out;
|
||||
if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1))
|
||||
goto out;
|
||||
|
||||
cpuc->n_events++;
|
||||
cpuc->n_added++;
|
||||
|
||||
ret = 0;
|
||||
out:
|
||||
perf_enable();
|
||||
local_irq_restore(flags);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __hw_perf_event_init(struct perf_event *event)
|
||||
{
|
||||
struct perf_event_attr *attr = &event->attr;
|
||||
struct perf_event *evts[MAX_HWEVENTS];
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
unsigned long events[MAX_HWEVENTS];
|
||||
int current_idx_dmy[MAX_HWEVENTS];
|
||||
const struct perf_event_map *pmap;
|
||||
u64 enc;
|
||||
int n;
|
||||
|
||||
if (atomic_read(&nmi_active) < 0)
|
||||
|
|
@ -869,10 +1083,7 @@ static int __hw_perf_event_init(struct perf_event *event)
|
|||
} else
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
/* We save the enable bits in the config_base. So to
|
||||
* turn off sampling just write 'config', and to enable
|
||||
* things write 'config | config_base'.
|
||||
*/
|
||||
/* We save the enable bits in the config_base. */
|
||||
hwc->config_base = sparc_pmu->irq_bit;
|
||||
if (!attr->exclude_user)
|
||||
hwc->config_base |= PCR_UTRACE;
|
||||
|
|
@ -883,13 +1094,11 @@ static int __hw_perf_event_init(struct perf_event *event)
|
|||
|
||||
hwc->event_base = perf_event_encode(pmap);
|
||||
|
||||
enc = pmap->encoding;
|
||||
|
||||
n = 0;
|
||||
if (event->group_leader != event) {
|
||||
n = collect_events(event->group_leader,
|
||||
perf_max_events - 1,
|
||||
evts, events);
|
||||
evts, events, current_idx_dmy);
|
||||
if (n < 0)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
@ -899,9 +1108,11 @@ static int __hw_perf_event_init(struct perf_event *event)
|
|||
if (check_excludes(evts, n, 1))
|
||||
return -EINVAL;
|
||||
|
||||
if (sparc_check_constraints(events, n + 1))
|
||||
if (sparc_check_constraints(evts, events, n + 1))
|
||||
return -EINVAL;
|
||||
|
||||
hwc->idx = PIC_NO_INDEX;
|
||||
|
||||
/* Try to do all error checking before this point, as unwinding
|
||||
* state after grabbing the PMC is difficult.
|
||||
*/
|
||||
|
|
@ -914,15 +1125,6 @@ static int __hw_perf_event_init(struct perf_event *event)
|
|||
atomic64_set(&hwc->period_left, hwc->sample_period);
|
||||
}
|
||||
|
||||
if (pmap->pic_mask & PIC_UPPER) {
|
||||
hwc->idx = PIC_UPPER_INDEX;
|
||||
enc <<= sparc_pmu->upper_shift;
|
||||
} else {
|
||||
hwc->idx = PIC_LOWER_INDEX;
|
||||
enc <<= sparc_pmu->lower_shift;
|
||||
}
|
||||
|
||||
hwc->config |= enc;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -972,7 +1174,7 @@ static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
|
|||
struct perf_sample_data data;
|
||||
struct cpu_hw_events *cpuc;
|
||||
struct pt_regs *regs;
|
||||
int idx;
|
||||
int i;
|
||||
|
||||
if (!atomic_read(&active_events))
|
||||
return NOTIFY_DONE;
|
||||
|
|
@ -1001,13 +1203,12 @@ static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
|
|||
if (sparc_pmu->irq_bit)
|
||||
pcr_ops->write(cpuc->pcr);
|
||||
|
||||
for (idx = 0; idx < MAX_HWEVENTS; idx++) {
|
||||
struct perf_event *event = cpuc->events[idx];
|
||||
for (i = 0; i < cpuc->n_events; i++) {
|
||||
struct perf_event *event = cpuc->event[i];
|
||||
int idx = cpuc->current_idx[i];
|
||||
struct hw_perf_event *hwc;
|
||||
u64 val;
|
||||
|
||||
if (!test_bit(idx, cpuc->active_mask))
|
||||
continue;
|
||||
hwc = &event->hw;
|
||||
val = sparc_perf_event_update(event, hwc, idx);
|
||||
if (val & (1ULL << 31))
|
||||
|
|
@ -1059,10 +1260,8 @@ void __init init_hw_perf_events(void)
|
|||
|
||||
pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type);
|
||||
|
||||
/* All sparc64 PMUs currently have 2 events. But this simple
|
||||
* driver only supports one active event at a time.
|
||||
*/
|
||||
perf_max_events = 1;
|
||||
/* All sparc64 PMUs currently have 2 events. */
|
||||
perf_max_events = 2;
|
||||
|
||||
register_die_notifier(&perf_event_nmi_notifier);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue