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MIPS: perf: Reorganize contents of perf support files.
The contents of arch/mips/kernel/perf_event.c and arch/mips/kernel/perf_event_mipsxx.c were divided in a seemingly ad hoc manner, with the first including the second. I moved all the hardware counter support code to perf_event_mipsxx.c and removed the gating #ifdefs to the Kconfig and Makefile. Now perf_event.c contains only the callchain support, everything else is in perf_event_mipsxx.c There are no code changes, only moving of functions from one file to the other, or removing empty unneeded functions. Signed-off-by: David Daney <david.daney@cavium.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Dezhong Diao <dediao@cisco.com> Cc: Gabor Juhos <juhosg@openwrt.org> Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2791/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
parent
4409af37b8
commit
e5dcb58aa5
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@ -2101,7 +2101,7 @@ config NODES_SHIFT
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config HW_PERF_EVENTS
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bool "Enable hardware performance counter support for perf events"
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depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && CPU_MIPS32
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depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1)
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default y
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help
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Enable hardware performance counter support for perf events. If
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@ -11,6 +11,8 @@ obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
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ifdef CONFIG_FUNCTION_TRACER
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CFLAGS_REMOVE_ftrace.o = -pg
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CFLAGS_REMOVE_early_printk.o = -pg
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CFLAGS_REMOVE_perf_event.o = -pg
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CFLAGS_REMOVE_perf_event_mipsxx.o = -pg
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endif
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obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o
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@ -106,7 +108,8 @@ obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT) += 8250-platform.o
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obj-$(CONFIG_MIPS_CPUFREQ) += cpufreq/
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obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
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obj-$(CONFIG_PERF_EVENTS) += perf_event.o
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obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o
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obj-$(CONFIG_JUMP_LABEL) += jump_label.o
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@ -14,529 +14,16 @@
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* published by the Free Software Foundation.
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*/
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#include <linux/cpumask.h>
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#include <linux/interrupt.h>
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#include <linux/smp.h>
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#include <linux/kernel.h>
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#include <linux/perf_event.h>
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#include <linux/uaccess.h>
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#include <asm/irq.h>
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#include <asm/irq_regs.h>
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#include <asm/stacktrace.h>
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#include <asm/time.h> /* For perf_irq */
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/* These are for 32bit counters. For 64bit ones, define them accordingly. */
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#define MAX_PERIOD ((1ULL << 32) - 1)
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#define VALID_COUNT 0x7fffffff
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#define TOTAL_BITS 32
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#define HIGHEST_BIT 31
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#define MIPS_MAX_HWEVENTS 4
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struct cpu_hw_events {
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/* Array of events on this cpu. */
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struct perf_event *events[MIPS_MAX_HWEVENTS];
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/*
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* Set the bit (indexed by the counter number) when the counter
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* is used for an event.
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*/
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unsigned long used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
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/*
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* The borrowed MSB for the performance counter. A MIPS performance
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* counter uses its bit 31 (for 32bit counters) or bit 63 (for 64bit
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* counters) as a factor of determining whether a counter overflow
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* should be signaled. So here we use a separate MSB for each
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* counter to make things easy.
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*/
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unsigned long msbs[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
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/*
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* Software copy of the control register for each performance counter.
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* MIPS CPUs vary in performance counters. They use this differently,
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* and even may not use it.
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*/
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unsigned int saved_ctrl[MIPS_MAX_HWEVENTS];
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};
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DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
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.saved_ctrl = {0},
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};
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/* The description of MIPS performance events. */
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struct mips_perf_event {
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unsigned int event_id;
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/*
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* MIPS performance counters are indexed starting from 0.
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* CNTR_EVEN indicates the indexes of the counters to be used are
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* even numbers.
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*/
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unsigned int cntr_mask;
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#define CNTR_EVEN 0x55555555
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#define CNTR_ODD 0xaaaaaaaa
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#ifdef CONFIG_MIPS_MT_SMP
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enum {
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T = 0,
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V = 1,
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P = 2,
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} range;
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#else
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#define T
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#define V
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#define P
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#endif
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};
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static struct mips_perf_event raw_event;
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static DEFINE_MUTEX(raw_event_mutex);
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#define UNSUPPORTED_PERF_EVENT_ID 0xffffffff
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#define C(x) PERF_COUNT_HW_CACHE_##x
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struct mips_pmu {
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const char *name;
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int irq;
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irqreturn_t (*handle_irq)(int irq, void *dev);
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int (*handle_shared_irq)(void);
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void (*start)(void);
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void (*stop)(void);
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int (*alloc_counter)(struct cpu_hw_events *cpuc,
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struct hw_perf_event *hwc);
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u64 (*read_counter)(unsigned int idx);
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void (*write_counter)(unsigned int idx, u64 val);
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void (*enable_event)(struct hw_perf_event *evt, int idx);
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void (*disable_event)(int idx);
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const struct mips_perf_event *(*map_raw_event)(u64 config);
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const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX];
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const struct mips_perf_event (*cache_event_map)
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX];
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unsigned int num_counters;
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};
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static const struct mips_pmu *mipspmu;
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static int mipspmu_event_set_period(struct perf_event *event,
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struct hw_perf_event *hwc,
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int idx)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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s64 left = local64_read(&hwc->period_left);
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s64 period = hwc->sample_period;
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int ret = 0;
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u64 uleft;
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unsigned long flags;
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if (unlikely(left <= -period)) {
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left = period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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ret = 1;
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}
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if (unlikely(left <= 0)) {
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left += period;
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local64_set(&hwc->period_left, left);
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hwc->last_period = period;
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ret = 1;
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}
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if (left > (s64)MAX_PERIOD)
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left = MAX_PERIOD;
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local64_set(&hwc->prev_count, (u64)-left);
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local_irq_save(flags);
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uleft = (u64)(-left) & MAX_PERIOD;
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uleft > VALID_COUNT ?
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set_bit(idx, cpuc->msbs) : clear_bit(idx, cpuc->msbs);
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mipspmu->write_counter(idx, (u64)(-left) & VALID_COUNT);
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local_irq_restore(flags);
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perf_event_update_userpage(event);
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return ret;
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}
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static void mipspmu_event_update(struct perf_event *event,
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struct hw_perf_event *hwc,
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int idx)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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unsigned long flags;
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int shift = 64 - TOTAL_BITS;
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s64 prev_raw_count, new_raw_count;
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u64 delta;
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again:
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prev_raw_count = local64_read(&hwc->prev_count);
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local_irq_save(flags);
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/* Make the counter value be a "real" one. */
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new_raw_count = mipspmu->read_counter(idx);
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if (new_raw_count & (test_bit(idx, cpuc->msbs) << HIGHEST_BIT)) {
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new_raw_count &= VALID_COUNT;
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clear_bit(idx, cpuc->msbs);
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} else
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new_raw_count |= (test_bit(idx, cpuc->msbs) << HIGHEST_BIT);
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local_irq_restore(flags);
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if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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new_raw_count) != prev_raw_count)
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goto again;
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delta = (new_raw_count << shift) - (prev_raw_count << shift);
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delta >>= shift;
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local64_add(delta, &event->count);
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local64_sub(delta, &hwc->period_left);
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}
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static void mipspmu_start(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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if (!mipspmu)
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return;
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if (flags & PERF_EF_RELOAD)
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WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
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hwc->state = 0;
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/* Set the period for the event. */
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mipspmu_event_set_period(event, hwc, hwc->idx);
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/* Enable the event. */
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mipspmu->enable_event(hwc, hwc->idx);
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}
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static void mipspmu_stop(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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if (!mipspmu)
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return;
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if (!(hwc->state & PERF_HES_STOPPED)) {
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/* We are working on a local event. */
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mipspmu->disable_event(hwc->idx);
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barrier();
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mipspmu_event_update(event, hwc, hwc->idx);
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hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
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}
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}
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static int mipspmu_add(struct perf_event *event, int flags)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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int idx;
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int err = 0;
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perf_pmu_disable(event->pmu);
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/* To look for a free counter for this event. */
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idx = mipspmu->alloc_counter(cpuc, hwc);
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if (idx < 0) {
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err = idx;
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goto out;
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}
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/*
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* If there is an event in the counter we are going to use then
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* make sure it is disabled.
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*/
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event->hw.idx = idx;
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mipspmu->disable_event(idx);
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cpuc->events[idx] = event;
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hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
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if (flags & PERF_EF_START)
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mipspmu_start(event, PERF_EF_RELOAD);
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/* Propagate our changes to the userspace mapping. */
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perf_event_update_userpage(event);
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out:
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perf_pmu_enable(event->pmu);
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return err;
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}
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static void mipspmu_del(struct perf_event *event, int flags)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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WARN_ON(idx < 0 || idx >= mipspmu->num_counters);
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mipspmu_stop(event, PERF_EF_UPDATE);
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cpuc->events[idx] = NULL;
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clear_bit(idx, cpuc->used_mask);
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perf_event_update_userpage(event);
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}
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static void mipspmu_read(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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/* Don't read disabled counters! */
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if (hwc->idx < 0)
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return;
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mipspmu_event_update(event, hwc, hwc->idx);
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}
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static void mipspmu_enable(struct pmu *pmu)
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{
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if (mipspmu)
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mipspmu->start();
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}
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static void mipspmu_disable(struct pmu *pmu)
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{
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if (mipspmu)
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mipspmu->stop();
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}
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static atomic_t active_events = ATOMIC_INIT(0);
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static DEFINE_MUTEX(pmu_reserve_mutex);
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static int (*save_perf_irq)(void);
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static int mipspmu_get_irq(void)
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{
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int err;
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if (mipspmu->irq >= 0) {
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/* Request my own irq handler. */
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err = request_irq(mipspmu->irq, mipspmu->handle_irq,
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IRQF_DISABLED | IRQF_NOBALANCING,
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"mips_perf_pmu", NULL);
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if (err) {
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pr_warning("Unable to request IRQ%d for MIPS "
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"performance counters!\n", mipspmu->irq);
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}
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} else if (cp0_perfcount_irq < 0) {
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/*
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* We are sharing the irq number with the timer interrupt.
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*/
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save_perf_irq = perf_irq;
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perf_irq = mipspmu->handle_shared_irq;
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err = 0;
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} else {
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pr_warning("The platform hasn't properly defined its "
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"interrupt controller.\n");
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err = -ENOENT;
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}
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return err;
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}
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static void mipspmu_free_irq(void)
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{
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if (mipspmu->irq >= 0)
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free_irq(mipspmu->irq, NULL);
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else if (cp0_perfcount_irq < 0)
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perf_irq = save_perf_irq;
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}
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/*
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* mipsxx/rm9000/loongson2 have different performance counters, they have
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* specific low-level init routines.
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*/
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static void reset_counters(void *arg);
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static int __hw_perf_event_init(struct perf_event *event);
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static void hw_perf_event_destroy(struct perf_event *event)
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{
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if (atomic_dec_and_mutex_lock(&active_events,
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&pmu_reserve_mutex)) {
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/*
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* We must not call the destroy function with interrupts
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* disabled.
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*/
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on_each_cpu(reset_counters,
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(void *)(long)mipspmu->num_counters, 1);
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mipspmu_free_irq();
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mutex_unlock(&pmu_reserve_mutex);
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}
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}
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static int mipspmu_event_init(struct perf_event *event)
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{
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int err = 0;
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switch (event->attr.type) {
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case PERF_TYPE_RAW:
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case PERF_TYPE_HARDWARE:
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case PERF_TYPE_HW_CACHE:
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break;
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default:
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return -ENOENT;
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}
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if (!mipspmu || event->cpu >= nr_cpumask_bits ||
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(event->cpu >= 0 && !cpu_online(event->cpu)))
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return -ENODEV;
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if (!atomic_inc_not_zero(&active_events)) {
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if (atomic_read(&active_events) > MIPS_MAX_HWEVENTS) {
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atomic_dec(&active_events);
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return -ENOSPC;
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}
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mutex_lock(&pmu_reserve_mutex);
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if (atomic_read(&active_events) == 0)
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err = mipspmu_get_irq();
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if (!err)
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atomic_inc(&active_events);
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mutex_unlock(&pmu_reserve_mutex);
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}
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if (err)
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return err;
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err = __hw_perf_event_init(event);
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if (err)
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hw_perf_event_destroy(event);
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return err;
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}
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static struct pmu pmu = {
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.pmu_enable = mipspmu_enable,
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.pmu_disable = mipspmu_disable,
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.event_init = mipspmu_event_init,
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.add = mipspmu_add,
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.del = mipspmu_del,
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.start = mipspmu_start,
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.stop = mipspmu_stop,
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.read = mipspmu_read,
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};
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static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev)
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{
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/*
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* Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for
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* event_id.
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*/
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#ifdef CONFIG_MIPS_MT_SMP
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return ((unsigned int)pev->range << 24) |
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(pev->cntr_mask & 0xffff00) |
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(pev->event_id & 0xff);
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#else
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return (pev->cntr_mask & 0xffff00) |
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(pev->event_id & 0xff);
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#endif
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}
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static const struct mips_perf_event *mipspmu_map_general_event(int idx)
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{
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const struct mips_perf_event *pev;
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|
||||
pev = ((*mipspmu->general_event_map)[idx].event_id ==
|
||||
UNSUPPORTED_PERF_EVENT_ID ? ERR_PTR(-EOPNOTSUPP) :
|
||||
&(*mipspmu->general_event_map)[idx]);
|
||||
|
||||
return pev;
|
||||
}
|
||||
|
||||
static const struct mips_perf_event *mipspmu_map_cache_event(u64 config)
|
||||
{
|
||||
unsigned int cache_type, cache_op, cache_result;
|
||||
const struct mips_perf_event *pev;
|
||||
|
||||
cache_type = (config >> 0) & 0xff;
|
||||
if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
cache_op = (config >> 8) & 0xff;
|
||||
if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
cache_result = (config >> 16) & 0xff;
|
||||
if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
pev = &((*mipspmu->cache_event_map)
|
||||
[cache_type]
|
||||
[cache_op]
|
||||
[cache_result]);
|
||||
|
||||
if (pev->event_id == UNSUPPORTED_PERF_EVENT_ID)
|
||||
return ERR_PTR(-EOPNOTSUPP);
|
||||
|
||||
return pev;
|
||||
|
||||
}
|
||||
|
||||
static int validate_event(struct cpu_hw_events *cpuc,
|
||||
struct perf_event *event)
|
||||
{
|
||||
struct hw_perf_event fake_hwc = event->hw;
|
||||
|
||||
/* Allow mixed event group. So return 1 to pass validation. */
|
||||
if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF)
|
||||
return 1;
|
||||
|
||||
return mipspmu->alloc_counter(cpuc, &fake_hwc) >= 0;
|
||||
}
|
||||
|
||||
static int validate_group(struct perf_event *event)
|
||||
{
|
||||
struct perf_event *sibling, *leader = event->group_leader;
|
||||
struct cpu_hw_events fake_cpuc;
|
||||
|
||||
memset(&fake_cpuc, 0, sizeof(fake_cpuc));
|
||||
|
||||
if (!validate_event(&fake_cpuc, leader))
|
||||
return -ENOSPC;
|
||||
|
||||
list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
|
||||
if (!validate_event(&fake_cpuc, sibling))
|
||||
return -ENOSPC;
|
||||
}
|
||||
|
||||
if (!validate_event(&fake_cpuc, event))
|
||||
return -ENOSPC;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* This is needed by specific irq handlers in perf_event_*.c */
|
||||
static void handle_associated_event(struct cpu_hw_events *cpuc,
|
||||
int idx, struct perf_sample_data *data,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
struct perf_event *event = cpuc->events[idx];
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
|
||||
mipspmu_event_update(event, hwc, idx);
|
||||
data->period = event->hw.last_period;
|
||||
if (!mipspmu_event_set_period(event, hwc, idx))
|
||||
return;
|
||||
|
||||
if (perf_event_overflow(event, data, regs))
|
||||
mipspmu->disable_event(idx);
|
||||
}
|
||||
|
||||
#include "perf_event_mipsxx.c"
|
||||
|
||||
/* Callchain handling code. */
|
||||
|
||||
/*
|
||||
* Leave userspace callchain empty for now. When we find a way to trace
|
||||
* the user stack callchains, we add here.
|
||||
* the user stack callchains, we will add it here.
|
||||
*/
|
||||
void perf_callchain_user(struct perf_callchain_entry *entry,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
}
|
||||
|
||||
static void save_raw_perf_callchain(struct perf_callchain_entry *entry,
|
||||
unsigned long reg29)
|
||||
|
|
|
@ -1,5 +1,529 @@
|
|||
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) || \
|
||||
defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_SB1)
|
||||
/*
|
||||
* Linux performance counter support for MIPS.
|
||||
*
|
||||
* Copyright (C) 2010 MIPS Technologies, Inc.
|
||||
* Author: Deng-Cheng Zhu
|
||||
*
|
||||
* This code is based on the implementation for ARM, which is in turn
|
||||
* based on the sparc64 perf event code and the x86 code. Performance
|
||||
* counter access is based on the MIPS Oprofile code. And the callchain
|
||||
* support references the code of MIPS stacktrace.c.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/cpumask.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/perf_event.h>
|
||||
#include <linux/uaccess.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/irq_regs.h>
|
||||
#include <asm/stacktrace.h>
|
||||
#include <asm/time.h> /* For perf_irq */
|
||||
|
||||
/* These are for 32bit counters. For 64bit ones, define them accordingly. */
|
||||
#define MAX_PERIOD ((1ULL << 32) - 1)
|
||||
#define VALID_COUNT 0x7fffffff
|
||||
#define TOTAL_BITS 32
|
||||
#define HIGHEST_BIT 31
|
||||
|
||||
#define MIPS_MAX_HWEVENTS 4
|
||||
|
||||
struct cpu_hw_events {
|
||||
/* Array of events on this cpu. */
|
||||
struct perf_event *events[MIPS_MAX_HWEVENTS];
|
||||
|
||||
/*
|
||||
* Set the bit (indexed by the counter number) when the counter
|
||||
* is used for an event.
|
||||
*/
|
||||
unsigned long used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
|
||||
|
||||
/*
|
||||
* The borrowed MSB for the performance counter. A MIPS performance
|
||||
* counter uses its bit 31 (for 32bit counters) or bit 63 (for 64bit
|
||||
* counters) as a factor of determining whether a counter overflow
|
||||
* should be signaled. So here we use a separate MSB for each
|
||||
* counter to make things easy.
|
||||
*/
|
||||
unsigned long msbs[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
|
||||
|
||||
/*
|
||||
* Software copy of the control register for each performance counter.
|
||||
* MIPS CPUs vary in performance counters. They use this differently,
|
||||
* and even may not use it.
|
||||
*/
|
||||
unsigned int saved_ctrl[MIPS_MAX_HWEVENTS];
|
||||
};
|
||||
DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
|
||||
.saved_ctrl = {0},
|
||||
};
|
||||
|
||||
/* The description of MIPS performance events. */
|
||||
struct mips_perf_event {
|
||||
unsigned int event_id;
|
||||
/*
|
||||
* MIPS performance counters are indexed starting from 0.
|
||||
* CNTR_EVEN indicates the indexes of the counters to be used are
|
||||
* even numbers.
|
||||
*/
|
||||
unsigned int cntr_mask;
|
||||
#define CNTR_EVEN 0x55555555
|
||||
#define CNTR_ODD 0xaaaaaaaa
|
||||
#ifdef CONFIG_MIPS_MT_SMP
|
||||
enum {
|
||||
T = 0,
|
||||
V = 1,
|
||||
P = 2,
|
||||
} range;
|
||||
#else
|
||||
#define T
|
||||
#define V
|
||||
#define P
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct mips_perf_event raw_event;
|
||||
static DEFINE_MUTEX(raw_event_mutex);
|
||||
|
||||
#define UNSUPPORTED_PERF_EVENT_ID 0xffffffff
|
||||
#define C(x) PERF_COUNT_HW_CACHE_##x
|
||||
|
||||
struct mips_pmu {
|
||||
const char *name;
|
||||
int irq;
|
||||
irqreturn_t (*handle_irq)(int irq, void *dev);
|
||||
int (*handle_shared_irq)(void);
|
||||
void (*start)(void);
|
||||
void (*stop)(void);
|
||||
int (*alloc_counter)(struct cpu_hw_events *cpuc,
|
||||
struct hw_perf_event *hwc);
|
||||
u64 (*read_counter)(unsigned int idx);
|
||||
void (*write_counter)(unsigned int idx, u64 val);
|
||||
void (*enable_event)(struct hw_perf_event *evt, int idx);
|
||||
void (*disable_event)(int idx);
|
||||
const struct mips_perf_event *(*map_raw_event)(u64 config);
|
||||
const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX];
|
||||
const struct mips_perf_event (*cache_event_map)
|
||||
[PERF_COUNT_HW_CACHE_MAX]
|
||||
[PERF_COUNT_HW_CACHE_OP_MAX]
|
||||
[PERF_COUNT_HW_CACHE_RESULT_MAX];
|
||||
unsigned int num_counters;
|
||||
};
|
||||
|
||||
static const struct mips_pmu *mipspmu;
|
||||
|
||||
static int mipspmu_event_set_period(struct perf_event *event,
|
||||
struct hw_perf_event *hwc,
|
||||
int idx)
|
||||
{
|
||||
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
||||
s64 left = local64_read(&hwc->period_left);
|
||||
s64 period = hwc->sample_period;
|
||||
int ret = 0;
|
||||
u64 uleft;
|
||||
unsigned long flags;
|
||||
|
||||
if (unlikely(left <= -period)) {
|
||||
left = period;
|
||||
local64_set(&hwc->period_left, left);
|
||||
hwc->last_period = period;
|
||||
ret = 1;
|
||||
}
|
||||
|
||||
if (unlikely(left <= 0)) {
|
||||
left += period;
|
||||
local64_set(&hwc->period_left, left);
|
||||
hwc->last_period = period;
|
||||
ret = 1;
|
||||
}
|
||||
|
||||
if (left > (s64)MAX_PERIOD)
|
||||
left = MAX_PERIOD;
|
||||
|
||||
local64_set(&hwc->prev_count, (u64)-left);
|
||||
|
||||
local_irq_save(flags);
|
||||
uleft = (u64)(-left) & MAX_PERIOD;
|
||||
uleft > VALID_COUNT ?
|
||||
set_bit(idx, cpuc->msbs) : clear_bit(idx, cpuc->msbs);
|
||||
mipspmu->write_counter(idx, (u64)(-left) & VALID_COUNT);
|
||||
local_irq_restore(flags);
|
||||
|
||||
perf_event_update_userpage(event);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mipspmu_event_update(struct perf_event *event,
|
||||
struct hw_perf_event *hwc,
|
||||
int idx)
|
||||
{
|
||||
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
||||
unsigned long flags;
|
||||
int shift = 64 - TOTAL_BITS;
|
||||
s64 prev_raw_count, new_raw_count;
|
||||
u64 delta;
|
||||
|
||||
again:
|
||||
prev_raw_count = local64_read(&hwc->prev_count);
|
||||
local_irq_save(flags);
|
||||
/* Make the counter value be a "real" one. */
|
||||
new_raw_count = mipspmu->read_counter(idx);
|
||||
if (new_raw_count & (test_bit(idx, cpuc->msbs) << HIGHEST_BIT)) {
|
||||
new_raw_count &= VALID_COUNT;
|
||||
clear_bit(idx, cpuc->msbs);
|
||||
} else
|
||||
new_raw_count |= (test_bit(idx, cpuc->msbs) << HIGHEST_BIT);
|
||||
local_irq_restore(flags);
|
||||
|
||||
if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
|
||||
new_raw_count) != prev_raw_count)
|
||||
goto again;
|
||||
|
||||
delta = (new_raw_count << shift) - (prev_raw_count << shift);
|
||||
delta >>= shift;
|
||||
|
||||
local64_add(delta, &event->count);
|
||||
local64_sub(delta, &hwc->period_left);
|
||||
}
|
||||
|
||||
static void mipspmu_start(struct perf_event *event, int flags)
|
||||
{
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
|
||||
if (!mipspmu)
|
||||
return;
|
||||
|
||||
if (flags & PERF_EF_RELOAD)
|
||||
WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
|
||||
|
||||
hwc->state = 0;
|
||||
|
||||
/* Set the period for the event. */
|
||||
mipspmu_event_set_period(event, hwc, hwc->idx);
|
||||
|
||||
/* Enable the event. */
|
||||
mipspmu->enable_event(hwc, hwc->idx);
|
||||
}
|
||||
|
||||
static void mipspmu_stop(struct perf_event *event, int flags)
|
||||
{
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
|
||||
if (!mipspmu)
|
||||
return;
|
||||
|
||||
if (!(hwc->state & PERF_HES_STOPPED)) {
|
||||
/* We are working on a local event. */
|
||||
mipspmu->disable_event(hwc->idx);
|
||||
barrier();
|
||||
mipspmu_event_update(event, hwc, hwc->idx);
|
||||
hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
|
||||
}
|
||||
}
|
||||
|
||||
static int mipspmu_add(struct perf_event *event, int flags)
|
||||
{
|
||||
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
int idx;
|
||||
int err = 0;
|
||||
|
||||
perf_pmu_disable(event->pmu);
|
||||
|
||||
/* To look for a free counter for this event. */
|
||||
idx = mipspmu->alloc_counter(cpuc, hwc);
|
||||
if (idx < 0) {
|
||||
err = idx;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* If there is an event in the counter we are going to use then
|
||||
* make sure it is disabled.
|
||||
*/
|
||||
event->hw.idx = idx;
|
||||
mipspmu->disable_event(idx);
|
||||
cpuc->events[idx] = event;
|
||||
|
||||
hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
|
||||
if (flags & PERF_EF_START)
|
||||
mipspmu_start(event, PERF_EF_RELOAD);
|
||||
|
||||
/* Propagate our changes to the userspace mapping. */
|
||||
perf_event_update_userpage(event);
|
||||
|
||||
out:
|
||||
perf_pmu_enable(event->pmu);
|
||||
return err;
|
||||
}
|
||||
|
||||
static void mipspmu_del(struct perf_event *event, int flags)
|
||||
{
|
||||
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
int idx = hwc->idx;
|
||||
|
||||
WARN_ON(idx < 0 || idx >= mipspmu->num_counters);
|
||||
|
||||
mipspmu_stop(event, PERF_EF_UPDATE);
|
||||
cpuc->events[idx] = NULL;
|
||||
clear_bit(idx, cpuc->used_mask);
|
||||
|
||||
perf_event_update_userpage(event);
|
||||
}
|
||||
|
||||
static void mipspmu_read(struct perf_event *event)
|
||||
{
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
|
||||
/* Don't read disabled counters! */
|
||||
if (hwc->idx < 0)
|
||||
return;
|
||||
|
||||
mipspmu_event_update(event, hwc, hwc->idx);
|
||||
}
|
||||
|
||||
static void mipspmu_enable(struct pmu *pmu)
|
||||
{
|
||||
if (mipspmu)
|
||||
mipspmu->start();
|
||||
}
|
||||
|
||||
static void mipspmu_disable(struct pmu *pmu)
|
||||
{
|
||||
if (mipspmu)
|
||||
mipspmu->stop();
|
||||
}
|
||||
|
||||
static atomic_t active_events = ATOMIC_INIT(0);
|
||||
static DEFINE_MUTEX(pmu_reserve_mutex);
|
||||
static int (*save_perf_irq)(void);
|
||||
|
||||
static int mipspmu_get_irq(void)
|
||||
{
|
||||
int err;
|
||||
|
||||
if (mipspmu->irq >= 0) {
|
||||
/* Request my own irq handler. */
|
||||
err = request_irq(mipspmu->irq, mipspmu->handle_irq,
|
||||
IRQF_DISABLED | IRQF_NOBALANCING,
|
||||
"mips_perf_pmu", NULL);
|
||||
if (err) {
|
||||
pr_warning("Unable to request IRQ%d for MIPS "
|
||||
"performance counters!\n", mipspmu->irq);
|
||||
}
|
||||
} else if (cp0_perfcount_irq < 0) {
|
||||
/*
|
||||
* We are sharing the irq number with the timer interrupt.
|
||||
*/
|
||||
save_perf_irq = perf_irq;
|
||||
perf_irq = mipspmu->handle_shared_irq;
|
||||
err = 0;
|
||||
} else {
|
||||
pr_warning("The platform hasn't properly defined its "
|
||||
"interrupt controller.\n");
|
||||
err = -ENOENT;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static void mipspmu_free_irq(void)
|
||||
{
|
||||
if (mipspmu->irq >= 0)
|
||||
free_irq(mipspmu->irq, NULL);
|
||||
else if (cp0_perfcount_irq < 0)
|
||||
perf_irq = save_perf_irq;
|
||||
}
|
||||
|
||||
/*
|
||||
* mipsxx/rm9000/loongson2 have different performance counters, they have
|
||||
* specific low-level init routines.
|
||||
*/
|
||||
static void reset_counters(void *arg);
|
||||
static int __hw_perf_event_init(struct perf_event *event);
|
||||
|
||||
static void hw_perf_event_destroy(struct perf_event *event)
|
||||
{
|
||||
if (atomic_dec_and_mutex_lock(&active_events,
|
||||
&pmu_reserve_mutex)) {
|
||||
/*
|
||||
* We must not call the destroy function with interrupts
|
||||
* disabled.
|
||||
*/
|
||||
on_each_cpu(reset_counters,
|
||||
(void *)(long)mipspmu->num_counters, 1);
|
||||
mipspmu_free_irq();
|
||||
mutex_unlock(&pmu_reserve_mutex);
|
||||
}
|
||||
}
|
||||
|
||||
static int mipspmu_event_init(struct perf_event *event)
|
||||
{
|
||||
int err = 0;
|
||||
|
||||
switch (event->attr.type) {
|
||||
case PERF_TYPE_RAW:
|
||||
case PERF_TYPE_HARDWARE:
|
||||
case PERF_TYPE_HW_CACHE:
|
||||
break;
|
||||
|
||||
default:
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
if (!mipspmu || event->cpu >= nr_cpumask_bits ||
|
||||
(event->cpu >= 0 && !cpu_online(event->cpu)))
|
||||
return -ENODEV;
|
||||
|
||||
if (!atomic_inc_not_zero(&active_events)) {
|
||||
if (atomic_read(&active_events) > MIPS_MAX_HWEVENTS) {
|
||||
atomic_dec(&active_events);
|
||||
return -ENOSPC;
|
||||
}
|
||||
|
||||
mutex_lock(&pmu_reserve_mutex);
|
||||
if (atomic_read(&active_events) == 0)
|
||||
err = mipspmu_get_irq();
|
||||
|
||||
if (!err)
|
||||
atomic_inc(&active_events);
|
||||
mutex_unlock(&pmu_reserve_mutex);
|
||||
}
|
||||
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = __hw_perf_event_init(event);
|
||||
if (err)
|
||||
hw_perf_event_destroy(event);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static struct pmu pmu = {
|
||||
.pmu_enable = mipspmu_enable,
|
||||
.pmu_disable = mipspmu_disable,
|
||||
.event_init = mipspmu_event_init,
|
||||
.add = mipspmu_add,
|
||||
.del = mipspmu_del,
|
||||
.start = mipspmu_start,
|
||||
.stop = mipspmu_stop,
|
||||
.read = mipspmu_read,
|
||||
};
|
||||
|
||||
static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev)
|
||||
{
|
||||
/*
|
||||
* Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for
|
||||
* event_id.
|
||||
*/
|
||||
#ifdef CONFIG_MIPS_MT_SMP
|
||||
return ((unsigned int)pev->range << 24) |
|
||||
(pev->cntr_mask & 0xffff00) |
|
||||
(pev->event_id & 0xff);
|
||||
#else
|
||||
return (pev->cntr_mask & 0xffff00) |
|
||||
(pev->event_id & 0xff);
|
||||
#endif
|
||||
}
|
||||
|
||||
static const struct mips_perf_event *mipspmu_map_general_event(int idx)
|
||||
{
|
||||
const struct mips_perf_event *pev;
|
||||
|
||||
pev = ((*mipspmu->general_event_map)[idx].event_id ==
|
||||
UNSUPPORTED_PERF_EVENT_ID ? ERR_PTR(-EOPNOTSUPP) :
|
||||
&(*mipspmu->general_event_map)[idx]);
|
||||
|
||||
return pev;
|
||||
}
|
||||
|
||||
static const struct mips_perf_event *mipspmu_map_cache_event(u64 config)
|
||||
{
|
||||
unsigned int cache_type, cache_op, cache_result;
|
||||
const struct mips_perf_event *pev;
|
||||
|
||||
cache_type = (config >> 0) & 0xff;
|
||||
if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
cache_op = (config >> 8) & 0xff;
|
||||
if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
cache_result = (config >> 16) & 0xff;
|
||||
if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
pev = &((*mipspmu->cache_event_map)
|
||||
[cache_type]
|
||||
[cache_op]
|
||||
[cache_result]);
|
||||
|
||||
if (pev->event_id == UNSUPPORTED_PERF_EVENT_ID)
|
||||
return ERR_PTR(-EOPNOTSUPP);
|
||||
|
||||
return pev;
|
||||
|
||||
}
|
||||
|
||||
static int validate_event(struct cpu_hw_events *cpuc,
|
||||
struct perf_event *event)
|
||||
{
|
||||
struct hw_perf_event fake_hwc = event->hw;
|
||||
|
||||
/* Allow mixed event group. So return 1 to pass validation. */
|
||||
if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF)
|
||||
return 1;
|
||||
|
||||
return mipspmu->alloc_counter(cpuc, &fake_hwc) >= 0;
|
||||
}
|
||||
|
||||
static int validate_group(struct perf_event *event)
|
||||
{
|
||||
struct perf_event *sibling, *leader = event->group_leader;
|
||||
struct cpu_hw_events fake_cpuc;
|
||||
|
||||
memset(&fake_cpuc, 0, sizeof(fake_cpuc));
|
||||
|
||||
if (!validate_event(&fake_cpuc, leader))
|
||||
return -ENOSPC;
|
||||
|
||||
list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
|
||||
if (!validate_event(&fake_cpuc, sibling))
|
||||
return -ENOSPC;
|
||||
}
|
||||
|
||||
if (!validate_event(&fake_cpuc, event))
|
||||
return -ENOSPC;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* This is needed by specific irq handlers in perf_event_*.c */
|
||||
static void handle_associated_event(struct cpu_hw_events *cpuc,
|
||||
int idx, struct perf_sample_data *data,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
struct perf_event *event = cpuc->events[idx];
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
|
||||
mipspmu_event_update(event, hwc, idx);
|
||||
data->period = event->hw.last_period;
|
||||
if (!mipspmu_event_set_period(event, hwc, idx))
|
||||
return;
|
||||
|
||||
if (perf_event_overflow(event, data, regs))
|
||||
mipspmu->disable_event(idx);
|
||||
}
|
||||
|
||||
#define M_CONFIG1_PC (1 << 4)
|
||||
|
||||
|
@ -1062,5 +1586,3 @@ init_hw_perf_events(void)
|
|||
return 0;
|
||||
}
|
||||
early_initcall(init_hw_perf_events);
|
||||
|
||||
#endif /* defined(CONFIG_CPU_MIPS32)... */
|
||||
|
|
Loading…
Reference in a new issue