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pwm: stm32: Replace write_ccrx with regmap_write

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The TIM_CCR1...4 registers are consecutive, so replace the switch
case with a simple calculation. Since ch is known to be in the 0...3
range (it is set to hwpwm < npwm <= 4), drop the unnecessary error
handling. The return value was not checked anyway. What remains does
not warrant keeping the write_ccrx() function around, so instead call
regmap_write() directly at the singular call site.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
This commit is contained in:
Philipp Zabel 2023-10-19 22:07:00 +02:00 committed by Thierry Reding
parent 7ee2273197
commit e495f47274
1 changed files with 1 additions and 16 deletions
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17
drivers/pwm/pwm-stm32.c
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@ -52,21 +52,6 @@ static u32 active_channels(struct stm32_pwm *dev)
return ccer & TIM_CCER_CCXE;
}
static int write_ccrx(struct stm32_pwm *dev, int ch, u32 value)
{
switch (ch) {
case 0:
return regmap_write(dev->regmap, TIM_CCR1, value);
case 1:
return regmap_write(dev->regmap, TIM_CCR2, value);
case 2:
return regmap_write(dev->regmap, TIM_CCR3, value);
case 3:
return regmap_write(dev->regmap, TIM_CCR4, value);
}
return -EINVAL;
}
#define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P)
#define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E)
#define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P)
@ -369,7 +354,7 @@ static int stm32_pwm_config(struct stm32_pwm *priv, int ch,
dty = prd * duty_ns;
do_div(dty, period_ns);
write_ccrx(priv, ch, dty);
regmap_write(priv->regmap, TIM_CCR1 + 4 * ch, dty);
/* Configure output mode */
shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;