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Blackfin arch: Some memory and code optimizations - Fix SYS_IRQS

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Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
This commit is contained in:
Michael Hennerich 2007-07-12 16:39:29 +08:00 committed by Bryan Wu
parent 34e0fc89bd
commit e3f2300036
2 changed files with 28 additions and 17 deletions
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2
arch/blackfin/mach-common/ints-priority-dc.c
View file

@ -396,7 +396,7 @@ int __init init_arch_irq(void)
bfin_write_EVT15(evt_system_call); bfin_write_EVT15(evt_system_call);
CSYNC(); CSYNC();
for (irq = 0; irq < SYS_IRQS; irq++) { for (irq = 0; irq <= SYS_IRQS; irq++) {
if (irq <= IRQ_CORETMR) if (irq <= IRQ_CORETMR)
set_irq_chip(irq, &bf561_core_irqchip); set_irq_chip(irq, &bf561_core_irqchip);
else else

43
arch/blackfin/mach-common/ints-priority-sc.c
View file

@ -434,6 +434,7 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq,
struct irq_desc *intb_desc) struct irq_desc *intb_desc)
{ {
u16 i; u16 i;
struct irq_desc *desc;
for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) { for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) {
int irq = IRQ_PF0 + i; int irq = IRQ_PF0 + i;
@ -443,7 +444,7 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq,
while (mask) { while (mask) {
if (mask & 1) { if (mask & 1) {
struct irq_desc *desc = irq_desc + irq; desc = irq_desc + irq;
desc->handle_irq(irq, desc); desc->handle_irq(irq, desc);
} }
irq++; irq++;
@ -464,7 +465,7 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq,
#define PINT_BIT(x) (1 << (PINT_2_BIT(x))) #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
static unsigned char irq2pint_lut[NR_PINTS]; static unsigned char irq2pint_lut[NR_PINTS];
static unsigned short pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS]; static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
struct pin_int_t { struct pin_int_t {
unsigned int mask_set; unsigned int mask_set;
@ -523,7 +524,7 @@ void init_pint_lut(void)
irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0); irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
bit_pos = bit + bank * NR_PINT_BITS; bit_pos = bit + bank * NR_PINT_BITS;
pint2irq_lut[bit_pos] = irq_base; pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
irq2pint_lut[irq_base - SYS_IRQS] = bit_pos; irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
} }
@ -545,9 +546,11 @@ static void bfin_gpio_ack_irq(unsigned int irq)
static void bfin_gpio_mask_ack_irq(unsigned int irq) static void bfin_gpio_mask_ack_irq(unsigned int irq)
{ {
u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
u32 pintbit = PINT_BIT(pint_val);
u8 bank = PINT_2_BANK(pint_val);
pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val); pint[bank]->request = pintbit;
pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val); pint[bank]->mask_clear = pintbit;
SSYNC(); SSYNC();
} }
@ -562,9 +565,11 @@ static void bfin_gpio_mask_irq(unsigned int irq)
static void bfin_gpio_unmask_irq(unsigned int irq) static void bfin_gpio_unmask_irq(unsigned int irq)
{ {
u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
u32 pintbit = PINT_BIT(pint_val);
u8 bank = PINT_2_BANK(pint_val);
pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val); pint[bank]->request = pintbit;
pint[PINT_2_BANK(pint_val)]->mask_set = PINT_BIT(pint_val); pint[bank]->mask_set = pintbit;
SSYNC(); SSYNC();
} }
@ -602,6 +607,8 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
unsigned int ret; unsigned int ret;
u16 gpionr = irq - IRQ_PA0; u16 gpionr = irq - IRQ_PA0;
u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
u32 pintbit = PINT_BIT(pint_val);
u8 bank = PINT_2_BANK(pint_val);
if (pint_val == IRQ_NOT_AVAIL) if (pint_val == IRQ_NOT_AVAIL)
return -ENODEV; return -ENODEV;
@ -630,20 +637,20 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
gpio_direction_input(gpionr); gpio_direction_input(gpionr);
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
pint[PINT_2_BANK(pint_val)]->edge_set = PINT_BIT(pint_val); pint[bank]->edge_set = pintbit;
} else { } else {
pint[PINT_2_BANK(pint_val)]->edge_clear = PINT_BIT(pint_val); pint[bank]->edge_clear = pintbit;
} }
if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
pint[PINT_2_BANK(pint_val)]->invert_set = PINT_BIT(pint_val); /* low or falling edge denoted by one */ pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
else else
pint[PINT_2_BANK(pint_val)]->invert_set = PINT_BIT(pint_val); /* high or rising edge denoted by zero */ pint[bank]->invert_set = pintbit; /* high or rising edge denoted by zero */
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
pint[PINT_2_BANK(pint_val)]->invert_set = PINT_BIT(pint_val); pint[bank]->invert_set = pintbit;
else else
pint[PINT_2_BANK(pint_val)]->invert_set = PINT_BIT(pint_val); pint[bank]->invert_set = pintbit;
SSYNC(); SSYNC();
@ -670,6 +677,7 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq,
{ {
u8 bank, pint_val; u8 bank, pint_val;
u32 request, irq; u32 request, irq;
struct irq_desc *desc;
switch (intb_irq) { switch (intb_irq) {
case IRQ_PINT0: case IRQ_PINT0:
@ -684,6 +692,8 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq,
case IRQ_PINT1: case IRQ_PINT1:
bank = 1; bank = 1;
break; break;
default:
return;
} }
pint_val = bank * NR_PINT_BITS; pint_val = bank * NR_PINT_BITS;
@ -692,8 +702,8 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq,
while (request) { while (request) {
if (request & 1) { if (request & 1) {
irq = pint2irq_lut[pint_val]; irq = pint2irq_lut[pint_val] + SYS_IRQS;
struct irq_desc *desc = irq_desc + irq; desc = irq_desc + irq;
desc->handle_irq(irq, desc); desc->handle_irq(irq, desc);
} }
pint_val++; pint_val++;
@ -868,7 +878,8 @@ void do_irq(int vec, struct pt_regs *fp)
sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0); sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0);
sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1); sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1);
sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2); sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2);
SSYNC();
for (;; ivg++) { for (;; ivg++) {
if (ivg >= ivg_stop) { if (ivg >= ivg_stop) {
atomic_inc(&num_spurious); atomic_inc(&num_spurious);