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- Fix two issues with MI300 address translation logic
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This commit is contained in:
Linus Torvalds
commit
e39388e430
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@ -224,7 +224,7 @@ int df_indirect_read_broadcast(u16 node, u8 func, u16 reg, u32 *lo);
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int get_df_system_info(void);
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int determine_node_id(struct addr_ctx *ctx, u8 socket_num, u8 die_num);
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int get_addr_hash_mi300(void);
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int get_umc_info_mi300(void);
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int get_address_map(struct addr_ctx *ctx);
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@ -127,7 +127,7 @@ static int df4_determine_df_rev(u32 reg)
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if (reg == DF_FUNC0_ID_MI300) {
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df_cfg.flags.heterogeneous = 1;
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if (get_addr_hash_mi300())
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if (get_umc_info_mi300())
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return -EINVAL;
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}
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@ -68,6 +68,8 @@ struct xor_bits {
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};
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#define NUM_BANK_BITS 4
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#define NUM_COL_BITS 5
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#define NUM_SID_BITS 2
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static struct {
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/* UMC::CH::AddrHashBank */
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@ -80,7 +82,22 @@ static struct {
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u8 bank_xor;
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} addr_hash;
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static struct {
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u8 bank[NUM_BANK_BITS];
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u8 col[NUM_COL_BITS];
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u8 sid[NUM_SID_BITS];
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u8 num_row_lo;
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u8 num_row_hi;
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u8 row_lo;
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u8 row_hi;
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u8 pc;
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} bit_shifts;
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#define MI300_UMC_CH_BASE 0x90000
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#define MI300_ADDR_CFG (MI300_UMC_CH_BASE + 0x30)
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#define MI300_ADDR_SEL (MI300_UMC_CH_BASE + 0x40)
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#define MI300_COL_SEL_LO (MI300_UMC_CH_BASE + 0x50)
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#define MI300_ADDR_SEL_2 (MI300_UMC_CH_BASE + 0xA4)
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#define MI300_ADDR_HASH_BANK0 (MI300_UMC_CH_BASE + 0xC8)
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#define MI300_ADDR_HASH_PC (MI300_UMC_CH_BASE + 0xE0)
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#define MI300_ADDR_HASH_PC2 (MI300_UMC_CH_BASE + 0xE4)
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@ -90,17 +107,42 @@ static struct {
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#define ADDR_HASH_ROW_XOR GENMASK(31, 14)
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#define ADDR_HASH_BANK_XOR GENMASK(5, 0)
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#define ADDR_CFG_NUM_ROW_LO GENMASK(11, 8)
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#define ADDR_CFG_NUM_ROW_HI GENMASK(15, 12)
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#define ADDR_SEL_BANK0 GENMASK(3, 0)
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#define ADDR_SEL_BANK1 GENMASK(7, 4)
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#define ADDR_SEL_BANK2 GENMASK(11, 8)
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#define ADDR_SEL_BANK3 GENMASK(15, 12)
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#define ADDR_SEL_BANK4 GENMASK(20, 16)
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#define ADDR_SEL_ROW_LO GENMASK(27, 24)
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#define ADDR_SEL_ROW_HI GENMASK(31, 28)
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#define COL_SEL_LO_COL0 GENMASK(3, 0)
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#define COL_SEL_LO_COL1 GENMASK(7, 4)
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#define COL_SEL_LO_COL2 GENMASK(11, 8)
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#define COL_SEL_LO_COL3 GENMASK(15, 12)
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#define COL_SEL_LO_COL4 GENMASK(19, 16)
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#define ADDR_SEL_2_BANK5 GENMASK(4, 0)
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#define ADDR_SEL_2_CHAN GENMASK(15, 12)
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/*
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* Read UMC::CH::AddrHash{Bank,PC,PC2} registers to get XOR bits used
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* for hashing. Do this during module init, since the values will not
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* change during run time.
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* for hashing.
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*
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* Also, read UMC::CH::Addr{Cfg,Sel,Sel2} and UMC::CH:ColSelLo registers to
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* get the values needed to reconstruct the normalized address. Apply additional
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* offsets to the raw register values, as needed.
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*
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* Do this during module init, since the values will not change during run time.
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*
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* These registers are instantiated for each UMC across each AMD Node.
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* However, they should be identically programmed due to the fixed hardware
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* design of MI300 systems. So read the values from Node 0 UMC 0 and keep a
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* single global structure for simplicity.
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*/
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int get_addr_hash_mi300(void)
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int get_umc_info_mi300(void)
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{
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u32 temp;
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int ret;
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@ -130,6 +172,44 @@ int get_addr_hash_mi300(void)
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addr_hash.bank_xor = FIELD_GET(ADDR_HASH_BANK_XOR, temp);
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ret = amd_smn_read(0, MI300_ADDR_CFG, &temp);
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if (ret)
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return ret;
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bit_shifts.num_row_hi = FIELD_GET(ADDR_CFG_NUM_ROW_HI, temp);
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bit_shifts.num_row_lo = 10 + FIELD_GET(ADDR_CFG_NUM_ROW_LO, temp);
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ret = amd_smn_read(0, MI300_ADDR_SEL, &temp);
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if (ret)
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return ret;
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bit_shifts.bank[0] = 5 + FIELD_GET(ADDR_SEL_BANK0, temp);
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bit_shifts.bank[1] = 5 + FIELD_GET(ADDR_SEL_BANK1, temp);
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bit_shifts.bank[2] = 5 + FIELD_GET(ADDR_SEL_BANK2, temp);
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bit_shifts.bank[3] = 5 + FIELD_GET(ADDR_SEL_BANK3, temp);
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/* Use BankBit4 for the SID0 position. */
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bit_shifts.sid[0] = 5 + FIELD_GET(ADDR_SEL_BANK4, temp);
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bit_shifts.row_lo = 12 + FIELD_GET(ADDR_SEL_ROW_LO, temp);
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bit_shifts.row_hi = 24 + FIELD_GET(ADDR_SEL_ROW_HI, temp);
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ret = amd_smn_read(0, MI300_COL_SEL_LO, &temp);
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if (ret)
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return ret;
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bit_shifts.col[0] = 2 + FIELD_GET(COL_SEL_LO_COL0, temp);
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bit_shifts.col[1] = 2 + FIELD_GET(COL_SEL_LO_COL1, temp);
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bit_shifts.col[2] = 2 + FIELD_GET(COL_SEL_LO_COL2, temp);
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bit_shifts.col[3] = 2 + FIELD_GET(COL_SEL_LO_COL3, temp);
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bit_shifts.col[4] = 2 + FIELD_GET(COL_SEL_LO_COL4, temp);
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ret = amd_smn_read(0, MI300_ADDR_SEL_2, &temp);
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if (ret)
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return ret;
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/* Use BankBit5 for the SID1 position. */
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bit_shifts.sid[1] = 5 + FIELD_GET(ADDR_SEL_2_BANK5, temp);
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bit_shifts.pc = 5 + FIELD_GET(ADDR_SEL_2_CHAN, temp);
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return 0;
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}
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@ -146,9 +226,6 @@ int get_addr_hash_mi300(void)
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* The MCA address format is as follows:
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* MCA_ADDR[27:0] = {S[1:0], P[0], R[14:0], B[3:0], C[4:0], Z[0]}
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*
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* The normalized address format is fixed in hardware and is as follows:
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* NA[30:0] = {S[1:0], R[13:0], C4, B[1:0], B[3:2], C[3:2], P, C[1:0], Z[4:0]}
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*
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* Additionally, the PC and Bank bits may be hashed. This must be accounted for before
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* reconstructing the normalized address.
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*/
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@ -158,18 +235,10 @@ int get_addr_hash_mi300(void)
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#define MI300_UMC_MCA_PC BIT(25)
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#define MI300_UMC_MCA_SID GENMASK(27, 26)
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#define MI300_NA_COL_1_0 GENMASK(6, 5)
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#define MI300_NA_PC BIT(7)
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#define MI300_NA_COL_3_2 GENMASK(9, 8)
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#define MI300_NA_BANK_3_2 GENMASK(11, 10)
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#define MI300_NA_BANK_1_0 GENMASK(13, 12)
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#define MI300_NA_COL_4 BIT(14)
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#define MI300_NA_ROW GENMASK(28, 15)
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#define MI300_NA_SID GENMASK(30, 29)
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static unsigned long convert_dram_to_norm_addr_mi300(unsigned long addr)
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{
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u16 i, col, row, bank, pc, sid, temp;
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u16 i, col, row, bank, pc, sid;
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u32 temp;
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col = FIELD_GET(MI300_UMC_MCA_COL, addr);
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bank = FIELD_GET(MI300_UMC_MCA_BANK, addr);
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@ -189,49 +258,48 @@ static unsigned long convert_dram_to_norm_addr_mi300(unsigned long addr)
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/* Calculate hash for PC bit. */
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if (addr_hash.pc.xor_enable) {
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/* Bits SID[1:0] act as Bank[6:5] for PC hash, so apply them here. */
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bank |= sid << 5;
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temp = bitwise_xor_bits(col & addr_hash.pc.col_xor);
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temp ^= bitwise_xor_bits(row & addr_hash.pc.row_xor);
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temp ^= bitwise_xor_bits(bank & addr_hash.bank_xor);
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/* Bits SID[1:0] act as Bank[5:4] for PC hash, so apply them here. */
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temp ^= bitwise_xor_bits((bank | sid << NUM_BANK_BITS) & addr_hash.bank_xor);
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pc ^= temp;
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/* Drop SID bits for the sake of debug printing later. */
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bank &= 0x1F;
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}
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/* Reconstruct the normalized address starting with NA[4:0] = 0 */
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addr = 0;
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/* NA[6:5] = Column[1:0] */
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temp = col & 0x3;
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addr |= FIELD_PREP(MI300_NA_COL_1_0, temp);
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/* Column bits */
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for (i = 0; i < NUM_COL_BITS; i++) {
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temp = (col >> i) & 0x1;
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addr |= temp << bit_shifts.col[i];
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}
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/* NA[7] = PC */
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addr |= FIELD_PREP(MI300_NA_PC, pc);
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/* Bank bits */
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for (i = 0; i < NUM_BANK_BITS; i++) {
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temp = (bank >> i) & 0x1;
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addr |= temp << bit_shifts.bank[i];
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}
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/* NA[9:8] = Column[3:2] */
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temp = (col >> 2) & 0x3;
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addr |= FIELD_PREP(MI300_NA_COL_3_2, temp);
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/* Row lo bits */
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for (i = 0; i < bit_shifts.num_row_lo; i++) {
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temp = (row >> i) & 0x1;
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addr |= temp << (i + bit_shifts.row_lo);
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}
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/* NA[11:10] = Bank[3:2] */
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temp = (bank >> 2) & 0x3;
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addr |= FIELD_PREP(MI300_NA_BANK_3_2, temp);
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/* Row hi bits */
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for (i = 0; i < bit_shifts.num_row_hi; i++) {
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temp = (row >> (i + bit_shifts.num_row_lo)) & 0x1;
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addr |= temp << (i + bit_shifts.row_hi);
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}
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/* NA[13:12] = Bank[1:0] */
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temp = bank & 0x3;
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addr |= FIELD_PREP(MI300_NA_BANK_1_0, temp);
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/* PC bit */
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addr |= pc << bit_shifts.pc;
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/* NA[14] = Column[4] */
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temp = (col >> 4) & 0x1;
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addr |= FIELD_PREP(MI300_NA_COL_4, temp);
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/* NA[28:15] = Row[13:0] */
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addr |= FIELD_PREP(MI300_NA_ROW, row);
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/* NA[30:29] = SID[1:0] */
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addr |= FIELD_PREP(MI300_NA_SID, sid);
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/* SID bits */
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for (i = 0; i < NUM_SID_BITS; i++) {
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temp = (sid >> i) & 0x1;
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addr |= temp << bit_shifts.sid[i];
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}
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pr_debug("Addr=0x%016lx", addr);
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pr_debug("Bank=%u Row=%u Column=%u PC=%u SID=%u", bank, row, col, pc, sid);
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