mirror of
https://github.com/torvalds/linux
synced 2024-09-21 19:47:35 +00:00
Merge branch 'sh/clkfwk' into sh-latest
This commit is contained in:
Paul Mundt
commit
e1eaf35452
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@ -14,6 +14,8 @@
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#include <linux/io.h>
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#include <linux/sh_clk.h>
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#define CPG_CKSTP_BIT BIT(8)
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static unsigned int sh_clk_read(struct clk *clk)
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{
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if (clk->flags & CLK_ENABLE_REG_8BIT)
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@ -66,71 +68,43 @@ int __init sh_clk_mstp_register(struct clk *clks, int nr)
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return ret;
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}
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/*
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* Div/mult table lookup helpers
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*/
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static inline struct clk_div_table *clk_to_div_table(struct clk *clk)
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{
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return clk->priv;
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}
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static inline struct clk_div_mult_table *clk_to_div_mult_table(struct clk *clk)
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{
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return clk_to_div_table(clk)->div_mult_table;
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}
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/*
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* Common div ops
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*/
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static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate)
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{
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return clk_rate_table_round(clk, clk->freq_table, rate);
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}
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static int sh_clk_div6_divisors[64] = {
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1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
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17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
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33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
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49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
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};
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static struct clk_div_mult_table sh_clk_div6_table = {
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.divisors = sh_clk_div6_divisors,
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.nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors),
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};
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static unsigned long sh_clk_div6_recalc(struct clk *clk)
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static unsigned long sh_clk_div_recalc(struct clk *clk)
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{
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struct clk_div_mult_table *table = &sh_clk_div6_table;
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struct clk_div_mult_table *table = clk_to_div_mult_table(clk);
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unsigned int idx;
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clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
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table, NULL);
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table, clk->arch_flags ? &clk->arch_flags : NULL);
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idx = sh_clk_read(clk) & 0x003f;
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idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask;
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return clk->freq_table[idx].frequency;
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}
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static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent)
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{
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struct clk_div_mult_table *table = &sh_clk_div6_table;
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u32 value;
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int ret, i;
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if (!clk->parent_table || !clk->parent_num)
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return -EINVAL;
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/* Search the parent */
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for (i = 0; i < clk->parent_num; i++)
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if (clk->parent_table[i] == parent)
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break;
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if (i == clk->parent_num)
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return -ENODEV;
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ret = clk_reparent(clk, parent);
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if (ret < 0)
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return ret;
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value = sh_clk_read(clk) &
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~(((1 << clk->src_width) - 1) << clk->src_shift);
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sh_clk_write(value | (i << clk->src_shift), clk);
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/* Rebuild the frequency table */
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clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
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table, NULL);
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return 0;
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}
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static int sh_clk_div6_set_rate(struct clk *clk, unsigned long rate)
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static int sh_clk_div_set_rate(struct clk *clk, unsigned long rate)
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{
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struct clk_div_table *dt = clk_to_div_table(clk);
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unsigned long value;
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int idx;
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@ -139,51 +113,53 @@ static int sh_clk_div6_set_rate(struct clk *clk, unsigned long rate)
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return idx;
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value = sh_clk_read(clk);
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value &= ~0x3f;
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value |= idx;
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value &= ~(clk->div_mask << clk->enable_bit);
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value |= (idx << clk->enable_bit);
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sh_clk_write(value, clk);
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/* XXX: Should use a post-change notifier */
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if (dt->kick)
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dt->kick(clk);
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return 0;
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}
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static int sh_clk_div6_enable(struct clk *clk)
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static int sh_clk_div_enable(struct clk *clk)
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{
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unsigned long value;
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int ret;
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ret = sh_clk_div6_set_rate(clk, clk->rate);
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if (ret == 0) {
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value = sh_clk_read(clk);
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value &= ~0x100; /* clear stop bit to enable clock */
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sh_clk_write(value, clk);
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}
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return ret;
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sh_clk_write(sh_clk_read(clk) & ~CPG_CKSTP_BIT, clk);
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return 0;
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}
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static void sh_clk_div6_disable(struct clk *clk)
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static void sh_clk_div_disable(struct clk *clk)
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{
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unsigned long value;
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unsigned int val;
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value = sh_clk_read(clk);
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value |= 0x100; /* stop clock */
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value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */
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sh_clk_write(value, clk);
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val = sh_clk_read(clk);
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val |= CPG_CKSTP_BIT;
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/*
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* div6 clocks require the divisor field to be non-zero or the
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* above CKSTP toggle silently fails. Ensure that the divisor
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* array is reset to its initial state on disable.
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*/
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if (clk->flags & CLK_MASK_DIV_ON_DISABLE)
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val |= clk->div_mask;
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sh_clk_write(val, clk);
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}
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static struct sh_clk_ops sh_clk_div6_clk_ops = {
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.recalc = sh_clk_div6_recalc,
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static struct sh_clk_ops sh_clk_div_clk_ops = {
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.recalc = sh_clk_div_recalc,
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.set_rate = sh_clk_div_set_rate,
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.round_rate = sh_clk_div_round_rate,
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.set_rate = sh_clk_div6_set_rate,
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.enable = sh_clk_div6_enable,
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.disable = sh_clk_div6_disable,
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};
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static struct sh_clk_ops sh_clk_div6_reparent_clk_ops = {
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.recalc = sh_clk_div6_recalc,
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static struct sh_clk_ops sh_clk_div_enable_clk_ops = {
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.recalc = sh_clk_div_recalc,
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.set_rate = sh_clk_div_set_rate,
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.round_rate = sh_clk_div_round_rate,
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.set_rate = sh_clk_div6_set_rate,
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.enable = sh_clk_div6_enable,
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.disable = sh_clk_div6_disable,
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.set_parent = sh_clk_div6_set_parent,
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.enable = sh_clk_div_enable,
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.disable = sh_clk_div_disable,
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};
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static int __init sh_clk_init_parent(struct clk *clk)
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@ -218,12 +194,12 @@ static int __init sh_clk_init_parent(struct clk *clk)
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return 0;
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}
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static int __init sh_clk_div6_register_ops(struct clk *clks, int nr,
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struct sh_clk_ops *ops)
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static int __init sh_clk_div_register_ops(struct clk *clks, int nr,
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struct clk_div_table *table, struct sh_clk_ops *ops)
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{
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struct clk *clkp;
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void *freq_table;
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int nr_divs = sh_clk_div6_table.nr_divisors;
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int nr_divs = table->div_mult_table->nr_divisors;
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int freq_table_size = sizeof(struct cpufreq_frequency_table);
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int ret = 0;
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int k;
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@ -231,7 +207,7 @@ static int __init sh_clk_div6_register_ops(struct clk *clks, int nr,
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freq_table_size *= (nr_divs + 1);
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freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
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if (!freq_table) {
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pr_err("sh_clk_div6_register: unable to alloc memory\n");
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pr_err("%s: unable to alloc memory\n", __func__);
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return -ENOMEM;
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}
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@ -239,47 +215,98 @@ static int __init sh_clk_div6_register_ops(struct clk *clks, int nr,
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clkp = clks + k;
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clkp->ops = ops;
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clkp->priv = table;
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clkp->freq_table = freq_table + (k * freq_table_size);
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clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
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ret = clk_register(clkp);
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if (ret < 0)
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break;
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ret = sh_clk_init_parent(clkp);
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ret = clk_register(clkp);
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if (ret == 0)
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ret = sh_clk_init_parent(clkp);
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}
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return ret;
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}
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/*
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* div6 support
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*/
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static int sh_clk_div6_divisors[64] = {
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1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
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17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
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33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
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49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
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};
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static struct clk_div_mult_table div6_div_mult_table = {
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.divisors = sh_clk_div6_divisors,
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.nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors),
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};
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static struct clk_div_table sh_clk_div6_table = {
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.div_mult_table = &div6_div_mult_table,
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};
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static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent)
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{
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struct clk_div_mult_table *table = clk_to_div_mult_table(clk);
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u32 value;
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int ret, i;
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if (!clk->parent_table || !clk->parent_num)
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return -EINVAL;
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/* Search the parent */
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for (i = 0; i < clk->parent_num; i++)
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if (clk->parent_table[i] == parent)
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break;
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if (i == clk->parent_num)
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return -ENODEV;
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ret = clk_reparent(clk, parent);
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if (ret < 0)
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return ret;
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value = sh_clk_read(clk) &
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~(((1 << clk->src_width) - 1) << clk->src_shift);
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sh_clk_write(value | (i << clk->src_shift), clk);
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/* Rebuild the frequency table */
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clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
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table, NULL);
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return 0;
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}
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static struct sh_clk_ops sh_clk_div6_reparent_clk_ops = {
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.recalc = sh_clk_div_recalc,
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.round_rate = sh_clk_div_round_rate,
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.set_rate = sh_clk_div_set_rate,
|
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.enable = sh_clk_div_enable,
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.disable = sh_clk_div_disable,
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.set_parent = sh_clk_div6_set_parent,
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};
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|
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int __init sh_clk_div6_register(struct clk *clks, int nr)
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{
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return sh_clk_div6_register_ops(clks, nr, &sh_clk_div6_clk_ops);
|
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return sh_clk_div_register_ops(clks, nr, &sh_clk_div6_table,
|
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&sh_clk_div_enable_clk_ops);
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}
|
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|
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int __init sh_clk_div6_reparent_register(struct clk *clks, int nr)
|
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{
|
||||
return sh_clk_div6_register_ops(clks, nr,
|
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&sh_clk_div6_reparent_clk_ops);
|
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}
|
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|
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static unsigned long sh_clk_div4_recalc(struct clk *clk)
|
||||
{
|
||||
struct clk_div4_table *d4t = clk->priv;
|
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struct clk_div_mult_table *table = d4t->div_mult_table;
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unsigned int idx;
|
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|
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clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
|
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table, &clk->arch_flags);
|
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|
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idx = (sh_clk_read(clk) >> clk->enable_bit) & 0x000f;
|
||||
|
||||
return clk->freq_table[idx].frequency;
|
||||
return sh_clk_div_register_ops(clks, nr, &sh_clk_div6_table,
|
||||
&sh_clk_div6_reparent_clk_ops);
|
||||
}
|
||||
|
||||
/*
|
||||
* div4 support
|
||||
*/
|
||||
static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
|
||||
{
|
||||
struct clk_div4_table *d4t = clk->priv;
|
||||
struct clk_div_mult_table *table = d4t->div_mult_table;
|
||||
struct clk_div_mult_table *table = clk_to_div_mult_table(clk);
|
||||
u32 value;
|
||||
int ret;
|
||||
|
||||
|
|
@ -306,107 +333,31 @@ static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
struct clk_div4_table *d4t = clk->priv;
|
||||
unsigned long value;
|
||||
int idx = clk_rate_table_find(clk, clk->freq_table, rate);
|
||||
if (idx < 0)
|
||||
return idx;
|
||||
|
||||
value = sh_clk_read(clk);
|
||||
value &= ~(0xf << clk->enable_bit);
|
||||
value |= (idx << clk->enable_bit);
|
||||
sh_clk_write(value, clk);
|
||||
|
||||
if (d4t->kick)
|
||||
d4t->kick(clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sh_clk_div4_enable(struct clk *clk)
|
||||
{
|
||||
sh_clk_write(sh_clk_read(clk) & ~(1 << 8), clk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sh_clk_div4_disable(struct clk *clk)
|
||||
{
|
||||
sh_clk_write(sh_clk_read(clk) | (1 << 8), clk);
|
||||
}
|
||||
|
||||
static struct sh_clk_ops sh_clk_div4_clk_ops = {
|
||||
.recalc = sh_clk_div4_recalc,
|
||||
.set_rate = sh_clk_div4_set_rate,
|
||||
.round_rate = sh_clk_div_round_rate,
|
||||
};
|
||||
|
||||
static struct sh_clk_ops sh_clk_div4_enable_clk_ops = {
|
||||
.recalc = sh_clk_div4_recalc,
|
||||
.set_rate = sh_clk_div4_set_rate,
|
||||
.round_rate = sh_clk_div_round_rate,
|
||||
.enable = sh_clk_div4_enable,
|
||||
.disable = sh_clk_div4_disable,
|
||||
};
|
||||
|
||||
static struct sh_clk_ops sh_clk_div4_reparent_clk_ops = {
|
||||
.recalc = sh_clk_div4_recalc,
|
||||
.set_rate = sh_clk_div4_set_rate,
|
||||
.recalc = sh_clk_div_recalc,
|
||||
.set_rate = sh_clk_div_set_rate,
|
||||
.round_rate = sh_clk_div_round_rate,
|
||||
.enable = sh_clk_div4_enable,
|
||||
.disable = sh_clk_div4_disable,
|
||||
.enable = sh_clk_div_enable,
|
||||
.disable = sh_clk_div_disable,
|
||||
.set_parent = sh_clk_div4_set_parent,
|
||||
};
|
||||
|
||||
static int __init sh_clk_div4_register_ops(struct clk *clks, int nr,
|
||||
struct clk_div4_table *table, struct sh_clk_ops *ops)
|
||||
{
|
||||
struct clk *clkp;
|
||||
void *freq_table;
|
||||
int nr_divs = table->div_mult_table->nr_divisors;
|
||||
int freq_table_size = sizeof(struct cpufreq_frequency_table);
|
||||
int ret = 0;
|
||||
int k;
|
||||
|
||||
freq_table_size *= (nr_divs + 1);
|
||||
freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
|
||||
if (!freq_table) {
|
||||
pr_err("sh_clk_div4_register: unable to alloc memory\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
for (k = 0; !ret && (k < nr); k++) {
|
||||
clkp = clks + k;
|
||||
|
||||
clkp->ops = ops;
|
||||
clkp->priv = table;
|
||||
|
||||
clkp->freq_table = freq_table + (k * freq_table_size);
|
||||
clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
|
||||
|
||||
ret = clk_register(clkp);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int __init sh_clk_div4_register(struct clk *clks, int nr,
|
||||
struct clk_div4_table *table)
|
||||
{
|
||||
return sh_clk_div4_register_ops(clks, nr, table, &sh_clk_div4_clk_ops);
|
||||
return sh_clk_div_register_ops(clks, nr, table, &sh_clk_div_clk_ops);
|
||||
}
|
||||
|
||||
int __init sh_clk_div4_enable_register(struct clk *clks, int nr,
|
||||
struct clk_div4_table *table)
|
||||
{
|
||||
return sh_clk_div4_register_ops(clks, nr, table,
|
||||
&sh_clk_div4_enable_clk_ops);
|
||||
return sh_clk_div_register_ops(clks, nr, table,
|
||||
&sh_clk_div_enable_clk_ops);
|
||||
}
|
||||
|
||||
int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
|
||||
struct clk_div4_table *table)
|
||||
{
|
||||
return sh_clk_div4_register_ops(clks, nr, table,
|
||||
&sh_clk_div4_reparent_clk_ops);
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||||
return sh_clk_div_register_ops(clks, nr, table,
|
||||
&sh_clk_div4_reparent_clk_ops);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -18,7 +18,6 @@ struct clk_mapping {
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|||
struct kref ref;
|
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};
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||||
|
||||
|
||||
struct sh_clk_ops {
|
||||
#ifdef CONFIG_SH_CLK_CPG_LEGACY
|
||||
void (*init)(struct clk *clk);
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||||
|
|
@ -31,6 +30,10 @@ struct sh_clk_ops {
|
|||
long (*round_rate)(struct clk *clk, unsigned long rate);
|
||||
};
|
||||
|
||||
#define SH_CLK_DIV_MSK(div) ((1 << (div)) - 1)
|
||||
#define SH_CLK_DIV4_MSK SH_CLK_DIV_MSK(4)
|
||||
#define SH_CLK_DIV6_MSK SH_CLK_DIV_MSK(6)
|
||||
|
||||
struct clk {
|
||||
struct list_head node;
|
||||
struct clk *parent;
|
||||
|
|
@ -52,6 +55,7 @@ struct clk {
|
|||
unsigned int enable_bit;
|
||||
void __iomem *mapped_reg;
|
||||
|
||||
unsigned int div_mask;
|
||||
unsigned long arch_flags;
|
||||
void *priv;
|
||||
struct clk_mapping *mapping;
|
||||
|
|
@ -65,6 +69,8 @@ struct clk {
|
|||
#define CLK_ENABLE_REG_16BIT BIT(2)
|
||||
#define CLK_ENABLE_REG_8BIT BIT(3)
|
||||
|
||||
#define CLK_MASK_DIV_ON_DISABLE BIT(4)
|
||||
|
||||
#define CLK_ENABLE_REG_MASK (CLK_ENABLE_REG_32BIT | \
|
||||
CLK_ENABLE_REG_16BIT | \
|
||||
CLK_ENABLE_REG_8BIT)
|
||||
|
|
@ -146,14 +152,17 @@ static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr)
|
|||
.enable_reg = (void __iomem *)_reg, \
|
||||
.enable_bit = _shift, \
|
||||
.arch_flags = _div_bitmap, \
|
||||
.div_mask = SH_CLK_DIV4_MSK, \
|
||||
.flags = _flags, \
|
||||
}
|
||||
|
||||
struct clk_div4_table {
|
||||
struct clk_div_table {
|
||||
struct clk_div_mult_table *div_mult_table;
|
||||
void (*kick)(struct clk *clk);
|
||||
};
|
||||
|
||||
#define clk_div4_table clk_div_table
|
||||
|
||||
int sh_clk_div4_register(struct clk *clks, int nr,
|
||||
struct clk_div4_table *table);
|
||||
int sh_clk_div4_enable_register(struct clk *clks, int nr,
|
||||
|
|
@ -165,7 +174,9 @@ int sh_clk_div4_reparent_register(struct clk *clks, int nr,
|
|||
_num_parents, _src_shift, _src_width) \
|
||||
{ \
|
||||
.enable_reg = (void __iomem *)_reg, \
|
||||
.flags = _flags, \
|
||||
.enable_bit = 0, /* unused */ \
|
||||
.flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
|
||||
.div_mask = SH_CLK_DIV6_MSK, \
|
||||
.parent_table = _parents, \
|
||||
.parent_num = _num_parents, \
|
||||
.src_shift = _src_shift, \
|
||||
|
|
@ -176,7 +187,9 @@ int sh_clk_div4_reparent_register(struct clk *clks, int nr,
|
|||
{ \
|
||||
.parent = _parent, \
|
||||
.enable_reg = (void __iomem *)_reg, \
|
||||
.flags = _flags, \
|
||||
.enable_bit = 0, /* unused */ \
|
||||
.div_mask = SH_CLK_DIV6_MSK, \
|
||||
.flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
|
||||
}
|
||||
|
||||
int sh_clk_div6_register(struct clk *clks, int nr);
|
||||
|
|
|
|||
Loading…
Reference in a new issue