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https://github.com/torvalds/linux
synced 2024-10-27 13:48:49 +00:00
iwlwifi: pcie: grab NIC access only once on RX init
When initializing RX we grab NIC access for every read and write. This is redundant - we can just grab access once. Signed-off-by: Sara Sharon <sara.sharon@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
This commit is contained in:
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1554ed2088
commit
dfcfeef96c
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@ -161,10 +161,11 @@ static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)
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return cpu_to_le32((u32)(dma_addr >> 8));
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return cpu_to_le32((u32)(dma_addr >> 8));
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}
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}
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static void iwl_pcie_write_prph_64(struct iwl_trans *trans, u64 ofs, u64 val)
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static void iwl_pcie_write_prph_64_no_grab(struct iwl_trans *trans, u64 ofs,
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u64 val)
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{
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{
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iwl_write_prph(trans, ofs, val & 0xffffffff);
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iwl_write_prph_no_grab(trans, ofs, val & 0xffffffff);
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iwl_write_prph(trans, ofs + 4, val >> 32);
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iwl_write_prph_no_grab(trans, ofs + 4, val >> 32);
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}
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}
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/*
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/*
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@ -698,6 +699,7 @@ static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
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{
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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u32 rb_size;
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u32 rb_size;
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unsigned long flags;
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const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
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const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
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switch (trans_pcie->rx_buf_size) {
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switch (trans_pcie->rx_buf_size) {
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@ -715,23 +717,26 @@ static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
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rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
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rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
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}
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}
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if (!iwl_trans_grab_nic_access(trans, &flags))
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return;
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/* Stop Rx DMA */
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/* Stop Rx DMA */
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iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
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iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
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/* reset and flush pointers */
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/* reset and flush pointers */
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iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
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iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
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iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
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iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
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iwl_write_direct32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
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iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
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/* Reset driver's Rx queue write index */
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/* Reset driver's Rx queue write index */
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iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
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iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
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/* Tell device where to find RBD circular buffer in DRAM */
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/* Tell device where to find RBD circular buffer in DRAM */
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iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
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iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
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(u32)(rxq->bd_dma >> 8));
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(u32)(rxq->bd_dma >> 8));
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/* Tell device where in DRAM to update its Rx status */
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/* Tell device where in DRAM to update its Rx status */
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iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
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iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
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rxq->rb_stts_dma >> 4);
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rxq->rb_stts_dma >> 4);
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/* Enable Rx DMA
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/* Enable Rx DMA
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* FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
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* FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
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@ -741,13 +746,15 @@ static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
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* RB timeout 0x10
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* RB timeout 0x10
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* 256 RBDs
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* 256 RBDs
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*/
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*/
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iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
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iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
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FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
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FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
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FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
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FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
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FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
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FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
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rb_size|
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rb_size |
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(RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
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(RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
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(rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
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(rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
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iwl_trans_release_nic_access(trans, &flags);
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/* Set interrupt coalescing timer to default (2048 usecs) */
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/* Set interrupt coalescing timer to default (2048 usecs) */
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iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
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iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
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@ -761,6 +768,7 @@ static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
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{
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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u32 rb_size, enabled = 0;
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u32 rb_size, enabled = 0;
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unsigned long flags;
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int i;
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int i;
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switch (trans_pcie->rx_buf_size) {
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switch (trans_pcie->rx_buf_size) {
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@ -778,25 +786,31 @@ static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
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rb_size = RFH_RXF_DMA_RB_SIZE_4K;
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rb_size = RFH_RXF_DMA_RB_SIZE_4K;
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}
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}
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if (!iwl_trans_grab_nic_access(trans, &flags))
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return;
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/* Stop Rx DMA */
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/* Stop Rx DMA */
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iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0);
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iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0);
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/* disable free amd used rx queue operation */
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/* disable free amd used rx queue operation */
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iwl_write_prph(trans, RFH_RXF_RXQ_ACTIVE, 0);
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iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0);
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for (i = 0; i < trans->num_rx_queues; i++) {
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for (i = 0; i < trans->num_rx_queues; i++) {
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/* Tell device where to find RBD free table in DRAM */
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/* Tell device where to find RBD free table in DRAM */
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iwl_pcie_write_prph_64(trans, RFH_Q_FRBDCB_BA_LSB(i),
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iwl_pcie_write_prph_64_no_grab(trans,
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(u64)(trans_pcie->rxq[i].bd_dma));
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RFH_Q_FRBDCB_BA_LSB(i),
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trans_pcie->rxq[i].bd_dma);
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/* Tell device where to find RBD used table in DRAM */
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/* Tell device where to find RBD used table in DRAM */
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iwl_pcie_write_prph_64(trans, RFH_Q_URBDCB_BA_LSB(i),
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iwl_pcie_write_prph_64_no_grab(trans,
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(u64)(trans_pcie->rxq[i].used_bd_dma));
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RFH_Q_URBDCB_BA_LSB(i),
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trans_pcie->rxq[i].used_bd_dma);
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/* Tell device where in DRAM to update its Rx status */
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/* Tell device where in DRAM to update its Rx status */
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iwl_pcie_write_prph_64(trans, RFH_Q_URBD_STTS_WPTR_LSB(i),
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iwl_pcie_write_prph_64_no_grab(trans,
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trans_pcie->rxq[i].rb_stts_dma);
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RFH_Q_URBD_STTS_WPTR_LSB(i),
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trans_pcie->rxq[i].rb_stts_dma);
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/* Reset device indice tables */
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/* Reset device indice tables */
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iwl_write_prph(trans, RFH_Q_FRBDCB_WIDX(i), 0);
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iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0);
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iwl_write_prph(trans, RFH_Q_FRBDCB_RIDX(i), 0);
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iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0);
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iwl_write_prph(trans, RFH_Q_URBDCB_WIDX(i), 0);
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iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0);
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enabled |= BIT(i) | BIT(i + 16);
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enabled |= BIT(i) | BIT(i + 16);
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}
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}
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@ -812,23 +826,26 @@ static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
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* Drop frames that exceed RB size
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* Drop frames that exceed RB size
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* 512 RBDs
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* 512 RBDs
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*/
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*/
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iwl_write_prph(trans, RFH_RXF_DMA_CFG,
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iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG,
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RFH_DMA_EN_ENABLE_VAL |
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RFH_DMA_EN_ENABLE_VAL |
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rb_size | RFH_RXF_DMA_SINGLE_FRAME_MASK |
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rb_size | RFH_RXF_DMA_SINGLE_FRAME_MASK |
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RFH_RXF_DMA_MIN_RB_4_8 |
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RFH_RXF_DMA_MIN_RB_4_8 |
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RFH_RXF_DMA_DROP_TOO_LARGE_MASK |
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RFH_RXF_DMA_DROP_TOO_LARGE_MASK |
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RFH_RXF_DMA_RBDCB_SIZE_512);
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RFH_RXF_DMA_RBDCB_SIZE_512);
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/*
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/*
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* Activate DMA snooping.
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* Activate DMA snooping.
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* Set RX DMA chunk size to 64B
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* Set RX DMA chunk size to 64B
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* Default queue is 0
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* Default queue is 0
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*/
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*/
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iwl_write_prph(trans, RFH_GEN_CFG, RFH_GEN_CFG_RFH_DMA_SNOOP |
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iwl_write_prph_no_grab(trans, RFH_GEN_CFG, RFH_GEN_CFG_RFH_DMA_SNOOP |
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(DEFAULT_RXQ_NUM << RFH_GEN_CFG_DEFAULT_RXQ_NUM_POS) |
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(DEFAULT_RXQ_NUM <<
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RFH_GEN_CFG_SERVICE_DMA_SNOOP);
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RFH_GEN_CFG_DEFAULT_RXQ_NUM_POS) |
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RFH_GEN_CFG_SERVICE_DMA_SNOOP);
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/* Enable the relevant rx queues */
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/* Enable the relevant rx queues */
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iwl_write_prph(trans, RFH_RXF_RXQ_ACTIVE, enabled);
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iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled);
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iwl_trans_release_nic_access(trans, &flags);
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/* Set interrupt coalescing timer to default (2048 usecs) */
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/* Set interrupt coalescing timer to default (2048 usecs) */
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iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
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iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
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