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arm64: dts: imx8mn: Enable cpu-idle driver
Enable i.MX8MN cpu-idle using generic ARM cpu-idle driver, 2 states are supported, details as below: root@imx8mnevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state0/name WFI root@imx8mnevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state0/usage 3098 root@imx8mnevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state1/name cpu-pd-wait root@imx8mnevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state1/usage 3078 Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -43,6 +43,19 @@ cpus {
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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#size-cells = <0>;
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idle-states {
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entry-method = "psci";
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cpu_pd_wait: cpu-pd-wait {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0010033>;
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local-timer-stop;
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entry-latency-us = <1000>;
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exit-latency-us = <700>;
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min-residency-us = <2700>;
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};
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};
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A53_0: cpu@0 {
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A53_0: cpu@0 {
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device_type = "cpu";
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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compatible = "arm,cortex-a53";
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@ -54,6 +67,7 @@ A53_0: cpu@0 {
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operating-points-v2 = <&a53_opp_table>;
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operating-points-v2 = <&a53_opp_table>;
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nvmem-cells = <&cpu_speed_grade>;
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nvmem-cells = <&cpu_speed_grade>;
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nvmem-cell-names = "speed_grade";
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nvmem-cell-names = "speed_grade";
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cpu-idle-states = <&cpu_pd_wait>;
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};
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};
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A53_1: cpu@1 {
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A53_1: cpu@1 {
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@ -65,6 +79,7 @@ A53_1: cpu@1 {
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enable-method = "psci";
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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next-level-cache = <&A53_L2>;
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operating-points-v2 = <&a53_opp_table>;
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operating-points-v2 = <&a53_opp_table>;
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cpu-idle-states = <&cpu_pd_wait>;
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};
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};
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A53_2: cpu@2 {
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A53_2: cpu@2 {
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@ -76,6 +91,7 @@ A53_2: cpu@2 {
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enable-method = "psci";
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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next-level-cache = <&A53_L2>;
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operating-points-v2 = <&a53_opp_table>;
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operating-points-v2 = <&a53_opp_table>;
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cpu-idle-states = <&cpu_pd_wait>;
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};
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};
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A53_3: cpu@3 {
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A53_3: cpu@3 {
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@ -87,6 +103,7 @@ A53_3: cpu@3 {
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enable-method = "psci";
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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next-level-cache = <&A53_L2>;
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operating-points-v2 = <&a53_opp_table>;
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operating-points-v2 = <&a53_opp_table>;
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cpu-idle-states = <&cpu_pd_wait>;
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};
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};
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A53_L2: l2-cache0 {
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A53_L2: l2-cache0 {
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