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ARM: dts: keystone: update reset node to work with reset driver

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The pll controller register set and device state control registers
include sets of registers with different purposes, so it's logically
to add syscon entry to be able to access them from appropriate places.

So added pll controller and device state control syscon entries.

The keystone driver requires the next additional properties:

"ti,syscon-pll" - phandle/offset pair. The phandle to syscon used to
		  access pll controller registers and the offset to use
		  reset control registers.

"ti,syscon-dev" - phandle/offset pair. The phandle to syscon used to
		  access device state control registers and the offset
		  in order to use mux block registers for all watchdogs.

"ti,wdt-list"	- option to declare what watchdogs are used to reboot
		  the SoC, so set "0" WDT as default.

Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
This commit is contained in:
Ivan Khoronzhuk 2014-05-23 16:34:55 -04:00 committed by Santosh Shilimkar
parent b7ae8bf7bf
commit ded79bebca
1 changed files with 13 additions and 1 deletions
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14
arch/arm/boot/dts/keystone.dtsi
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@ -67,9 +67,21 @@ soc {
interrupt-parent = <&gic>;
ranges = <0x0 0x0 0x0 0xc0000000>;
pllctrl: pll-controller@02310000 {
compatible = "ti,keystone-pllctrl", "syscon";
reg = <0x02310000 0x200>;
};
devctrl: device-state-control@02620000 {
compatible = "ti,keystone-devctrl", "syscon";
reg = <0x02620000 0x1000>;
};
rstctrl: reset-controller {
compatible = "ti,keystone-reset";
reg = <0x023100e8 4>; /* pll reset control reg */
ti,syscon-pll = <&pllctrl 0xe4>;
ti,syscon-dev = <&devctrl 0x328>;
ti,wdt-list = <0>;
};
/include/ "keystone-clocks.dtsi"