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https://github.com/torvalds/linux
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drm/radeon/kms: use drm_mode directly for panel modes
This reduces the number of mode format conversions needed and makes native panel mode support cleaner. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
parent
5a9bcacc0a
commit
de2103e452
7 changed files with 95 additions and 157 deletions
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@ -798,27 +798,29 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
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if (!lvds)
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return NULL;
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lvds->native_mode.dotclock =
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lvds->native_mode.clock =
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le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
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lvds->native_mode.panel_xres =
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lvds->native_mode.hdisplay =
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le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
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lvds->native_mode.panel_yres =
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lvds->native_mode.vdisplay =
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le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
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lvds->native_mode.hblank =
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le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
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lvds->native_mode.hoverplus =
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le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
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lvds->native_mode.hsync_width =
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le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
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lvds->native_mode.vblank =
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le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
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lvds->native_mode.voverplus =
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le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
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lvds->native_mode.vsync_width =
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le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
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lvds->native_mode.htotal = lvds->native_mode.hdisplay +
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le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
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lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
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le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
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lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
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le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
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lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
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le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
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lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
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le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
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lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
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le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
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lvds->panel_pwr_delay =
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le16_to_cpu(lvds_info->info.usOffDelayInMs);
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lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
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/* set crtc values */
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drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
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encoder->native_mode = lvds->native_mode;
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}
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@ -808,25 +808,25 @@ static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
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lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
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if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
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lvds->native_mode.panel_yres =
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lvds->native_mode.vdisplay =
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((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
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RADEON_VERT_PANEL_SHIFT) + 1;
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else
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lvds->native_mode.panel_yres =
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lvds->native_mode.vdisplay =
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(RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
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if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
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lvds->native_mode.panel_xres =
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lvds->native_mode.hdisplay =
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(((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
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RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
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else
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lvds->native_mode.panel_xres =
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lvds->native_mode.hdisplay =
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((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
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if ((lvds->native_mode.panel_xres < 640) ||
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(lvds->native_mode.panel_yres < 480)) {
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lvds->native_mode.panel_xres = 640;
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lvds->native_mode.panel_yres = 480;
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if ((lvds->native_mode.hdisplay < 640) ||
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(lvds->native_mode.vdisplay < 480)) {
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lvds->native_mode.hdisplay = 640;
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lvds->native_mode.vdisplay = 480;
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}
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ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
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@ -846,8 +846,8 @@ static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
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lvds->panel_vcc_delay = 200;
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DRM_INFO("Panel info derived from registers\n");
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DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.panel_xres,
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lvds->native_mode.panel_yres);
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DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
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lvds->native_mode.vdisplay);
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return lvds;
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}
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@ -882,11 +882,11 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
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DRM_INFO("Panel ID String: %s\n", stmp);
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lvds->native_mode.panel_xres = RBIOS16(lcd_info + 0x19);
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lvds->native_mode.panel_yres = RBIOS16(lcd_info + 0x1b);
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lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
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lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
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DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.panel_xres,
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lvds->native_mode.panel_yres);
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DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
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lvds->native_mode.vdisplay);
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lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
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if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0)
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@ -944,27 +944,25 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
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if (tmp == 0)
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break;
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if ((RBIOS16(tmp) == lvds->native_mode.panel_xres) &&
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if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
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(RBIOS16(tmp + 2) ==
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lvds->native_mode.panel_yres)) {
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lvds->native_mode.hblank =
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(RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
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lvds->native_mode.hoverplus =
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(RBIOS16(tmp + 21) - RBIOS16(tmp + 19) -
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1) * 8;
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lvds->native_mode.hsync_width =
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RBIOS8(tmp + 23) * 8;
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lvds->native_mode.vdisplay)) {
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lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
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lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
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lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
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RBIOS16(tmp + 21)) * 8;
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lvds->native_mode.vblank = (RBIOS16(tmp + 24) -
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RBIOS16(tmp + 26));
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lvds->native_mode.voverplus =
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((RBIOS16(tmp + 28) & 0x7ff) -
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RBIOS16(tmp + 26));
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lvds->native_mode.vsync_width =
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((RBIOS16(tmp + 28) & 0xf800) >> 11);
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lvds->native_mode.dotclock =
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RBIOS16(tmp + 9) * 10;
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lvds->native_mode.vtotal = RBIOS16(tmp + 24);
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lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
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lvds->native_mode.vsync_end =
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((RBIOS16(tmp + 28) & 0xf800) >> 11) +
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(RBIOS16(tmp + 28) & 0x7ff);
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lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
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lvds->native_mode.flags = 0;
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/* set crtc values */
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drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
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}
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}
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} else {
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@ -178,25 +178,13 @@ static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encode
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struct drm_device *dev = encoder->dev;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct drm_display_mode *mode = NULL;
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struct radeon_native_mode *native_mode = &radeon_encoder->native_mode;
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struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
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if (native_mode->panel_xres != 0 &&
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native_mode->panel_yres != 0 &&
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native_mode->dotclock != 0) {
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if (native_mode->hdisplay != 0 &&
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native_mode->vdisplay != 0 &&
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native_mode->clock != 0) {
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mode = drm_mode_create(dev);
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mode->hdisplay = native_mode->panel_xres;
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mode->vdisplay = native_mode->panel_yres;
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mode->htotal = mode->hdisplay + native_mode->hblank;
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mode->hsync_start = mode->hdisplay + native_mode->hoverplus;
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mode->hsync_end = mode->hsync_start + native_mode->hsync_width;
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mode->vtotal = mode->vdisplay + native_mode->vblank;
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mode->vsync_start = mode->vdisplay + native_mode->voverplus;
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mode->vsync_end = mode->vsync_start + native_mode->vsync_width;
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mode->clock = native_mode->dotclock;
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mode->flags = 0;
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*mode = *native_mode;
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mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
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drm_mode_set_name(mode);
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@ -210,7 +198,7 @@ static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_conn
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struct drm_device *dev = encoder->dev;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct drm_display_mode *mode = NULL;
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struct radeon_native_mode *native_mode = &radeon_encoder->native_mode;
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struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
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int i;
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struct mode_size {
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int w;
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@ -237,10 +225,10 @@ static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_conn
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for (i = 0; i < 17; i++) {
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if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
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if (common_modes[i].w > native_mode->panel_xres ||
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common_modes[i].h > native_mode->panel_yres ||
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(common_modes[i].w == native_mode->panel_xres &&
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common_modes[i].h == native_mode->panel_yres))
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if (common_modes[i].w > native_mode->hdisplay ||
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common_modes[i].h > native_mode->vdisplay ||
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(common_modes[i].w == native_mode->hdisplay &&
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common_modes[i].h == native_mode->vdisplay))
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continue;
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}
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if (common_modes[i].w < 320 || common_modes[i].h < 200)
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@ -344,28 +332,23 @@ static void radeon_fixup_lvds_native_mode(struct drm_encoder *encoder,
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struct drm_connector *connector)
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{
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_native_mode *native_mode = &radeon_encoder->native_mode;
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struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
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/* Try to get native mode details from EDID if necessary */
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if (!native_mode->dotclock) {
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if (!native_mode->clock) {
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struct drm_display_mode *t, *mode;
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list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
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if (mode->hdisplay == native_mode->panel_xres &&
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mode->vdisplay == native_mode->panel_yres) {
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native_mode->hblank = mode->htotal - mode->hdisplay;
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native_mode->hoverplus = mode->hsync_start - mode->hdisplay;
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native_mode->hsync_width = mode->hsync_end - mode->hsync_start;
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native_mode->vblank = mode->vtotal - mode->vdisplay;
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native_mode->voverplus = mode->vsync_start - mode->vdisplay;
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native_mode->vsync_width = mode->vsync_end - mode->vsync_start;
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native_mode->dotclock = mode->clock;
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if (mode->hdisplay == native_mode->hdisplay &&
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mode->vdisplay == native_mode->vdisplay) {
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*native_mode = *mode;
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drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
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DRM_INFO("Determined LVDS native mode details from EDID\n");
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break;
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}
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}
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}
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if (!native_mode->dotclock) {
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if (!native_mode->clock) {
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DRM_INFO("No LVDS native mode details, disabling RMX\n");
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radeon_encoder->rmx_type = RMX_OFF;
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}
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@ -420,10 +403,10 @@ static enum drm_connector_status radeon_lvds_detect(struct drm_connector *connec
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if (encoder) {
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_native_mode *native_mode = &radeon_encoder->native_mode;
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struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
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/* check if panel is valid */
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if (native_mode->panel_xres >= 320 && native_mode->panel_yres >= 240)
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if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
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ret = connector_status_connected;
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}
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@ -761,7 +761,7 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
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radeon_crtc->rmx_type = radeon_encoder->rmx_type;
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memcpy(&radeon_crtc->native_mode,
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&radeon_encoder->native_mode,
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sizeof(struct radeon_native_mode));
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sizeof(struct drm_display_mode));
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first = false;
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} else {
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if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
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@ -779,10 +779,10 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
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if (radeon_crtc->rmx_type != RMX_OFF) {
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fixed20_12 a, b;
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a.full = rfixed_const(crtc->mode.vdisplay);
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b.full = rfixed_const(radeon_crtc->native_mode.panel_xres);
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b.full = rfixed_const(radeon_crtc->native_mode.hdisplay);
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radeon_crtc->vsc.full = rfixed_div(a, b);
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a.full = rfixed_const(crtc->mode.hdisplay);
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b.full = rfixed_const(radeon_crtc->native_mode.panel_yres);
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b.full = rfixed_const(radeon_crtc->native_mode.vdisplay);
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radeon_crtc->hsc.full = rfixed_div(a, b);
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} else {
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radeon_crtc->vsc.full = rfixed_const(1);
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@ -171,49 +171,15 @@ void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_native_mode *native_mode = &radeon_encoder->native_mode;
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struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
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if (mode->hdisplay < native_mode->panel_xres ||
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mode->vdisplay < native_mode->panel_yres) {
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if (ASIC_IS_AVIVO(rdev)) {
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adjusted_mode->hdisplay = native_mode->panel_xres;
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adjusted_mode->vdisplay = native_mode->panel_yres;
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adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank;
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adjusted_mode->hsync_start = native_mode->panel_xres + native_mode->hoverplus;
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adjusted_mode->hsync_end = adjusted_mode->hsync_start + native_mode->hsync_width;
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adjusted_mode->vtotal = native_mode->panel_yres + native_mode->vblank;
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adjusted_mode->vsync_start = native_mode->panel_yres + native_mode->voverplus;
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adjusted_mode->vsync_end = adjusted_mode->vsync_start + native_mode->vsync_width;
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/* update crtc values */
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drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
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/* adjust crtc values */
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adjusted_mode->crtc_hdisplay = native_mode->panel_xres;
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adjusted_mode->crtc_vdisplay = native_mode->panel_yres;
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adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + native_mode->hblank;
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adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + native_mode->hoverplus;
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adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + native_mode->hsync_width;
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adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + native_mode->vblank;
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adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + native_mode->voverplus;
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adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + native_mode->vsync_width;
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} else {
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adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank;
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adjusted_mode->hsync_start = native_mode->panel_xres + native_mode->hoverplus;
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adjusted_mode->hsync_end = adjusted_mode->hsync_start + native_mode->hsync_width;
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adjusted_mode->vtotal = native_mode->panel_yres + native_mode->vblank;
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adjusted_mode->vsync_start = native_mode->panel_yres + native_mode->voverplus;
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adjusted_mode->vsync_end = adjusted_mode->vsync_start + native_mode->vsync_width;
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/* update crtc values */
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drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
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/* adjust crtc values */
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adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + native_mode->hblank;
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adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + native_mode->hoverplus;
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adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + native_mode->hsync_width;
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adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + native_mode->vblank;
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adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + native_mode->voverplus;
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adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + native_mode->vsync_width;
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if (mode->hdisplay < native_mode->hdisplay ||
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mode->vdisplay < native_mode->vdisplay) {
|
||||
*adjusted_mode = *native_mode;
|
||||
if (!ASIC_IS_AVIVO(rdev)) {
|
||||
adjusted_mode->hdisplay = mode->hdisplay;
|
||||
adjusted_mode->vdisplay = mode->vdisplay;
|
||||
}
|
||||
adjusted_mode->flags = native_mode->flags;
|
||||
adjusted_mode->clock = native_mode->dotclock;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
|
|||
u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
|
||||
u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
|
||||
u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
|
||||
struct radeon_native_mode *native_mode = &radeon_crtc->native_mode;
|
||||
struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
|
||||
|
||||
fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
|
||||
(RADEON_VERT_STRETCH_RESERVED |
|
||||
|
|
@ -95,19 +95,19 @@ static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
|
|||
|
||||
fp_horz_vert_active = 0;
|
||||
|
||||
if (native_mode->panel_xres == 0 ||
|
||||
native_mode->panel_yres == 0) {
|
||||
if (native_mode->hdisplay == 0 ||
|
||||
native_mode->vdisplay == 0) {
|
||||
hscale = false;
|
||||
vscale = false;
|
||||
} else {
|
||||
if (xres > native_mode->panel_xres)
|
||||
xres = native_mode->panel_xres;
|
||||
if (yres > native_mode->panel_yres)
|
||||
yres = native_mode->panel_yres;
|
||||
if (xres > native_mode->hdisplay)
|
||||
xres = native_mode->hdisplay;
|
||||
if (yres > native_mode->vdisplay)
|
||||
yres = native_mode->vdisplay;
|
||||
|
||||
if (xres == native_mode->panel_xres)
|
||||
if (xres == native_mode->hdisplay)
|
||||
hscale = false;
|
||||
if (yres == native_mode->panel_yres)
|
||||
if (yres == native_mode->vdisplay)
|
||||
vscale = false;
|
||||
}
|
||||
|
||||
|
|
@ -119,11 +119,11 @@ static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
|
|||
else {
|
||||
inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
|
||||
scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
|
||||
/ native_mode->panel_xres + 1;
|
||||
/ native_mode->hdisplay + 1;
|
||||
fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
|
||||
RADEON_HORZ_STRETCH_BLEND |
|
||||
RADEON_HORZ_STRETCH_ENABLE |
|
||||
((native_mode->panel_xres/8-1) << 16));
|
||||
((native_mode->hdisplay/8-1) << 16));
|
||||
}
|
||||
|
||||
if (!vscale)
|
||||
|
|
@ -131,11 +131,11 @@ static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
|
|||
else {
|
||||
inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
|
||||
scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
|
||||
/ native_mode->panel_yres + 1;
|
||||
/ native_mode->vdisplay + 1;
|
||||
fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
|
||||
RADEON_VERT_STRETCH_ENABLE |
|
||||
RADEON_VERT_STRETCH_BLEND |
|
||||
((native_mode->panel_yres-1) << 12));
|
||||
((native_mode->vdisplay-1) << 12));
|
||||
}
|
||||
break;
|
||||
case RMX_CENTER:
|
||||
|
|
@ -175,8 +175,8 @@ static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
|
|||
? RADEON_CRTC_V_SYNC_POL
|
||||
: 0)));
|
||||
|
||||
fp_horz_vert_active = (((native_mode->panel_yres) & 0xfff) |
|
||||
(((native_mode->panel_xres / 8) & 0x1ff) << 16));
|
||||
fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
|
||||
(((native_mode->hdisplay / 8) & 0x1ff) << 16));
|
||||
break;
|
||||
case RMX_OFF:
|
||||
default:
|
||||
|
|
|
|||
|
|
@ -186,17 +186,6 @@ struct radeon_mode_info {
|
|||
|
||||
};
|
||||
|
||||
struct radeon_native_mode {
|
||||
/* preferred mode */
|
||||
uint32_t panel_xres, panel_yres;
|
||||
uint32_t hoverplus, hsync_width;
|
||||
uint32_t hblank;
|
||||
uint32_t voverplus, vsync_width;
|
||||
uint32_t vblank;
|
||||
uint32_t dotclock;
|
||||
uint32_t flags;
|
||||
};
|
||||
|
||||
#define MAX_H_CODE_TIMING_LEN 32
|
||||
#define MAX_V_CODE_TIMING_LEN 32
|
||||
|
||||
|
|
@ -228,7 +217,7 @@ struct radeon_crtc {
|
|||
enum radeon_rmx_type rmx_type;
|
||||
fixed20_12 vsc;
|
||||
fixed20_12 hsc;
|
||||
struct radeon_native_mode native_mode;
|
||||
struct drm_display_mode native_mode;
|
||||
};
|
||||
|
||||
struct radeon_encoder_primary_dac {
|
||||
|
|
@ -248,7 +237,7 @@ struct radeon_encoder_lvds {
|
|||
bool use_bios_dividers;
|
||||
uint32_t lvds_gen_cntl;
|
||||
/* panel mode */
|
||||
struct radeon_native_mode native_mode;
|
||||
struct drm_display_mode native_mode;
|
||||
};
|
||||
|
||||
struct radeon_encoder_tv_dac {
|
||||
|
|
@ -279,7 +268,7 @@ struct radeon_encoder_atom_dig {
|
|||
uint32_t lvds_misc;
|
||||
uint16_t panel_pwr_delay;
|
||||
/* panel mode */
|
||||
struct radeon_native_mode native_mode;
|
||||
struct drm_display_mode native_mode;
|
||||
};
|
||||
|
||||
struct radeon_encoder_atom_dac {
|
||||
|
|
@ -294,7 +283,7 @@ struct radeon_encoder {
|
|||
uint32_t flags;
|
||||
uint32_t pixel_clock;
|
||||
enum radeon_rmx_type rmx_type;
|
||||
struct radeon_native_mode native_mode;
|
||||
struct drm_display_mode native_mode;
|
||||
void *enc_priv;
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue