mirror of
https://github.com/torvalds/linux
synced 2024-10-15 15:59:15 +00:00
KVM x86 APIC changes for 6.3:
- Remove a superfluous variables from apic_get_tmcct()
- Fix various edge cases in x2APIC MSR emulation
- Mark APIC timer as expired if its in one-shot mode and the count
underflows while the vCPU task was being migrated
- Reset xAPIC when userspace forces "impossible" x2APIC => xAPIC transition
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Merge tag 'kvm-x86-apic-6.3' of https://github.com/kvm-x86/linux into HEAD
KVM x86 APIC changes for 6.3:
- Remove a superfluous variables from apic_get_tmcct()
- Fix various edge cases in x2APIC MSR emulation
- Mark APIC timer as expired if its in one-shot mode and the count
underflows while the vCPU task was being migrated
- Reset xAPIC when userspace forces "impossible" x2APIC => xAPIC transition
This commit is contained in:
Paolo Bonzini
commit
ddad47bfb9
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@ -1487,7 +1487,6 @@ static u32 apic_get_tmcct(struct kvm_lapic *apic)
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{
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ktime_t remaining, now;
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s64 ns;
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u32 tmcct;
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ASSERT(apic != NULL);
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@ -1502,10 +1501,7 @@ static u32 apic_get_tmcct(struct kvm_lapic *apic)
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remaining = 0;
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ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
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tmcct = div64_u64(ns,
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(APIC_BUS_CYCLE_NS * apic->divide_count));
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return tmcct;
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return div64_u64(ns, (APIC_BUS_CYCLE_NS * apic->divide_count));
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}
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static void __report_tpr_access(struct kvm_lapic *apic, bool write)
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@ -1565,19 +1561,15 @@ static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
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#define APIC_REGS_MASK(first, count) \
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(APIC_REG_MASK(first) * ((1ull << (count)) - 1))
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static int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
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void *data)
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u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic)
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{
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unsigned char alignment = offset & 0xf;
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u32 result;
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/* this bitmask has a bit cleared for each reserved register */
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/* Leave bits '0' for reserved and write-only registers. */
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u64 valid_reg_mask =
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APIC_REG_MASK(APIC_ID) |
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APIC_REG_MASK(APIC_LVR) |
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APIC_REG_MASK(APIC_TASKPRI) |
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APIC_REG_MASK(APIC_PROCPRI) |
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APIC_REG_MASK(APIC_LDR) |
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APIC_REG_MASK(APIC_DFR) |
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APIC_REG_MASK(APIC_SPIV) |
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APIC_REGS_MASK(APIC_ISR, APIC_ISR_NR) |
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APIC_REGS_MASK(APIC_TMR, APIC_ISR_NR) |
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@ -1597,21 +1589,33 @@ static int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
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if (kvm_lapic_lvt_supported(apic, LVT_CMCI))
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valid_reg_mask |= APIC_REG_MASK(APIC_LVTCMCI);
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/*
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* ARBPRI and ICR2 are not valid in x2APIC mode. WARN if KVM reads ICR
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* in x2APIC mode as it's an 8-byte register in x2APIC and needs to be
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* manually handled by the caller.
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*/
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/* ARBPRI, DFR, and ICR2 are not valid in x2APIC mode. */
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if (!apic_x2apic_mode(apic))
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valid_reg_mask |= APIC_REG_MASK(APIC_ARBPRI) |
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APIC_REG_MASK(APIC_DFR) |
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APIC_REG_MASK(APIC_ICR2);
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else
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WARN_ON_ONCE(offset == APIC_ICR);
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return valid_reg_mask;
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}
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EXPORT_SYMBOL_GPL(kvm_lapic_readable_reg_mask);
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static int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
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void *data)
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{
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unsigned char alignment = offset & 0xf;
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u32 result;
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/*
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* WARN if KVM reads ICR in x2APIC mode, as it's an 8-byte register in
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* x2APIC and needs to be manually handled by the caller.
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*/
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WARN_ON_ONCE(apic_x2apic_mode(apic) && offset == APIC_ICR);
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if (alignment + len > 4)
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return 1;
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if (offset > 0x3f0 || !(valid_reg_mask & APIC_REG_MASK(offset)))
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if (offset > 0x3f0 ||
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!(kvm_lapic_readable_reg_mask(apic) & APIC_REG_MASK(offset)))
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return 1;
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result = __apic_read(apic, offset & ~0xf);
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@ -1964,8 +1968,12 @@ static bool set_target_expiration(struct kvm_lapic *apic, u32 count_reg)
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if (unlikely(count_reg != APIC_TMICT)) {
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deadline = tmict_to_ns(apic,
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kvm_lapic_get_reg(apic, count_reg));
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if (unlikely(deadline <= 0))
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deadline = apic->lapic_timer.period;
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if (unlikely(deadline <= 0)) {
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if (apic_lvtt_period(apic))
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deadline = apic->lapic_timer.period;
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else
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deadline = 0;
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}
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else if (unlikely(deadline > apic->lapic_timer.period)) {
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pr_info_ratelimited(
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"vcpu %i: requested lapic timer restore with "
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@ -2328,10 +2336,14 @@ static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
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break;
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case APIC_SELF_IPI:
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if (apic_x2apic_mode(apic))
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kvm_apic_send_ipi(apic, APIC_DEST_SELF | (val & APIC_VECTOR_MASK), 0);
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else
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/*
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* Self-IPI exists only when x2APIC is enabled. Bits 7:0 hold
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* the vector, everything else is reserved.
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*/
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if (!apic_x2apic_mode(apic) || (val & ~APIC_VECTOR_MASK))
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ret = 1;
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else
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kvm_apic_send_ipi(apic, APIC_DEST_SELF | val, 0);
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break;
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default:
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ret = 1;
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@ -2498,8 +2510,12 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
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}
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}
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if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE))
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kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
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if ((old_value ^ value) & X2APIC_ENABLE) {
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if (value & X2APIC_ENABLE)
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kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
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else if (value & MSR_IA32_APICBASE_ENABLE)
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kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
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}
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if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) {
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kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu);
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@ -3114,13 +3130,17 @@ static int kvm_lapic_msr_read(struct kvm_lapic *apic, u32 reg, u64 *data)
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static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data)
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{
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/*
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* ICR is a 64-bit register in x2APIC mode (and Hyper'v PV vAPIC) and
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* ICR is a 64-bit register in x2APIC mode (and Hyper-V PV vAPIC) and
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* can be written as such, all other registers remain accessible only
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* through 32-bit reads/writes.
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*/
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if (reg == APIC_ICR)
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return kvm_x2apic_icr_write(apic, data);
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/* Bits 63:32 are reserved in all other registers. */
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if (data >> 32)
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return 1;
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return kvm_lapic_reg_write(apic, reg, (u32)data);
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}
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@ -3143,9 +3163,6 @@ int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
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if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
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return 1;
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if (reg == APIC_DFR)
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return 1;
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return kvm_lapic_msr_read(apic, reg, data);
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}
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@ -146,6 +146,8 @@ int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
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int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
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void kvm_lapic_exit(void);
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u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic);
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#define VEC_POS(v) ((v) & (32 - 1))
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#define REG_POS(v) (((v) >> 5) << 4)
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@ -4018,29 +4018,20 @@ void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type)
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vmx_set_msr_bitmap_write(msr_bitmap, msr);
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}
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static void vmx_reset_x2apic_msrs(struct kvm_vcpu *vcpu, u8 mode)
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{
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unsigned long *msr_bitmap = to_vmx(vcpu)->vmcs01.msr_bitmap;
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unsigned long read_intercept;
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int msr;
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read_intercept = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
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for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
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unsigned int read_idx = msr / BITS_PER_LONG;
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unsigned int write_idx = read_idx + (0x800 / sizeof(long));
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msr_bitmap[read_idx] = read_intercept;
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msr_bitmap[write_idx] = ~0ul;
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}
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}
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static void vmx_update_msr_bitmap_x2apic(struct kvm_vcpu *vcpu)
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{
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/*
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* x2APIC indices for 64-bit accesses into the RDMSR and WRMSR halves
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* of the MSR bitmap. KVM emulates APIC registers up through 0x3f0,
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* i.e. MSR 0x83f, and so only needs to dynamically manipulate 64 bits.
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*/
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const int read_idx = APIC_BASE_MSR / BITS_PER_LONG_LONG;
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const int write_idx = read_idx + (0x800 / sizeof(u64));
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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u64 *msr_bitmap = (u64 *)vmx->vmcs01.msr_bitmap;
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u8 mode;
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if (!cpu_has_vmx_msr_bitmap())
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if (!cpu_has_vmx_msr_bitmap() || WARN_ON_ONCE(!lapic_in_kernel(vcpu)))
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return;
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if (cpu_has_secondary_exec_ctrls() &&
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@ -4058,7 +4049,18 @@ static void vmx_update_msr_bitmap_x2apic(struct kvm_vcpu *vcpu)
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vmx->x2apic_msr_bitmap_mode = mode;
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vmx_reset_x2apic_msrs(vcpu, mode);
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/*
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* Reset the bitmap for MSRs 0x800 - 0x83f. Leave AMD's uber-extended
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* registers (0x840 and above) intercepted, KVM doesn't support them.
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* Intercept all writes by default and poke holes as needed. Pass
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* through reads for all valid registers by default in x2APIC+APICv
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* mode, only the current timer count needs on-demand emulation by KVM.
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*/
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if (mode & MSR_BITMAP_MODE_X2APIC_APICV)
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msr_bitmap[read_idx] = ~kvm_lapic_readable_reg_mask(vcpu->arch.apic);
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else
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msr_bitmap[read_idx] = ~0ull;
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msr_bitmap[write_idx] = ~0ull;
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/*
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* TPR reads and writes can be virtualized even if virtual interrupt
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@ -132,6 +132,59 @@ static void test_icr(struct xapic_vcpu *x)
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__test_icr(x, -1ull & ~APIC_DM_FIXED_MASK);
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}
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static void __test_apic_id(struct kvm_vcpu *vcpu, uint64_t apic_base)
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{
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uint32_t apic_id, expected;
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struct kvm_lapic_state xapic;
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vcpu_set_msr(vcpu, MSR_IA32_APICBASE, apic_base);
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vcpu_ioctl(vcpu, KVM_GET_LAPIC, &xapic);
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expected = apic_base & X2APIC_ENABLE ? vcpu->id : vcpu->id << 24;
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apic_id = *((u32 *)&xapic.regs[APIC_ID]);
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TEST_ASSERT(apic_id == expected,
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"APIC_ID not set back to %s format; wanted = %x, got = %x",
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(apic_base & X2APIC_ENABLE) ? "x2APIC" : "xAPIC",
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expected, apic_id);
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}
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/*
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* Verify that KVM switches the APIC_ID between xAPIC and x2APIC when userspace
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* stuffs MSR_IA32_APICBASE. Setting the APIC_ID when x2APIC is enabled and
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* when the APIC transitions for DISABLED to ENABLED is architectural behavior
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* (on Intel), whereas the x2APIC => xAPIC transition behavior is KVM ABI since
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* attempted to transition from x2APIC to xAPIC without disabling the APIC is
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* architecturally disallowed.
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*/
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static void test_apic_id(void)
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{
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const uint32_t NR_VCPUS = 3;
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struct kvm_vcpu *vcpus[NR_VCPUS];
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uint64_t apic_base;
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struct kvm_vm *vm;
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int i;
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vm = vm_create_with_vcpus(NR_VCPUS, NULL, vcpus);
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vm_enable_cap(vm, KVM_CAP_X2APIC_API, KVM_X2APIC_API_USE_32BIT_IDS);
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for (i = 0; i < NR_VCPUS; i++) {
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apic_base = vcpu_get_msr(vcpus[i], MSR_IA32_APICBASE);
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TEST_ASSERT(apic_base & MSR_IA32_APICBASE_ENABLE,
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"APIC not in ENABLED state at vCPU RESET");
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TEST_ASSERT(!(apic_base & X2APIC_ENABLE),
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"APIC not in xAPIC mode at vCPU RESET");
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__test_apic_id(vcpus[i], apic_base);
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__test_apic_id(vcpus[i], apic_base | X2APIC_ENABLE);
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__test_apic_id(vcpus[i], apic_base);
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}
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kvm_vm_free(vm);
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}
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int main(int argc, char *argv[])
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{
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struct xapic_vcpu x = {
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@ -157,4 +210,6 @@ int main(int argc, char *argv[])
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virt_pg_map(vm, APIC_DEFAULT_GPA, APIC_DEFAULT_GPA);
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test_icr(&x);
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kvm_vm_free(vm);
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test_apic_id();
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}
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