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MIPS: SB1: Remove support for Pass 1 parts.
Pass 1 parts had a number of significant erratas and were only available in small numbers and under NDA. Full support also required the use of a special toolchain that kept branches properly aligned. These workarounds were never upstreamed and the only toolchain known to have them is Montavista's GCC 3.0-based toolchain which completly obsoleted if not useless these days. So now that automated testing has tripped over the user of the -msb1-pass1-workarounds option, rather than fixing it remove support for pass 1 parts. Probably nobody will notice. I seem to own the last know pass 1 board and I haven't noticed another one in the wild in the past decade, at least. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -2263,11 +2263,6 @@ config MIPS_CM
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config MIPS_CPC
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bool
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config SB1_PASS_1_WORKAROUNDS
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bool
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depends on CPU_SB1_PASS_1
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default y
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config SB1_PASS_2_WORKAROUNDS
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bool
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depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)
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@ -181,13 +181,6 @@ cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,)
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cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,)
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cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,)
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ifdef CONFIG_CPU_SB1
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ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
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KBUILD_AFLAGS_MODULE += -msb1-pass1-workarounds
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KBUILD_CFLAGS_MODULE += -msb1-pass1-workarounds
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endif
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endif
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# For smartmips configurations, there are hundreds of warnings due to ISA overrides
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# in assembly and header files. smartmips is only supported for MIPS32r1 onwards
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# and there is no support for 64-bit. Various '.set mips2' or '.set mips3' or
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@ -13,8 +13,7 @@
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#define R4600_V2_HIT_CACHEOP_WAR 0
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#define R5432_CP0_INTERRUPT_WAR 0
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#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \
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defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
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#if defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
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#ifndef __ASSEMBLY__
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extern int sb1250_m3_workaround_needed(void);
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@ -81,11 +81,6 @@ choice
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prompt "SiByte SOC Stepping"
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depends on SIBYTE_SB1xxx_SOC
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config CPU_SB1_PASS_1
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bool "1250 Pass1"
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depends on SIBYTE_SB1250
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select CPU_HAS_PREFETCH
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config CPU_SB1_PASS_2_1250
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bool "1250 An"
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depends on SIBYTE_SB1250
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@ -81,10 +81,7 @@ void check_bus_watcher(void)
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{
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u32 status, l2_err, memio_err;
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#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
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/* Destructive read, clears register and interrupt */
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status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS));
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#elif defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250)
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#if defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250)
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/* Use non-destructive register */
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status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS_DEBUG));
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#elif defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
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@ -202,12 +202,10 @@ void __init sb1250_setup(void)
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switch (war_pass) {
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case K_SYS_REVISION_BCM1250_PASS1:
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#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
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printk("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, "
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"and the kernel doesn't have the proper "
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"workarounds compiled in. @@@@\n");
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bad_config = 1;
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#endif
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break;
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case K_SYS_REVISION_BCM1250_PASS2:
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/* Pass 2 - easiest as default for now - so many numbers */
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@ -1508,16 +1508,7 @@ static void sbmac_channel_start(struct sbmac_softc *s)
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__raw_writeq(reg, port);
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port = s->sbm_base + R_MAC_ETHERNET_ADDR;
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#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
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/*
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* Pass1 SOCs do not receive packets addressed to the
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* destination address in the R_MAC_ETHERNET_ADDR register.
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* Set the value to zero.
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*/
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__raw_writeq(0, port);
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#else
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__raw_writeq(reg, port);
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#endif
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/*
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* Set the receive filter for no packets, and write values
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