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powerpc/mpc5121: update mpc5121ads DTS
Collects several changes needed after applying
previous mpc5121 platform and driver patches:
- Add mpc5121 reset module node
- Clean up and fix NAND description, remove unused properties
here and correct NAND flash chip size.
- Clean up I2C nodes: remove obsolete "cell-index" properties,
add "fsl,preserve-clocking" property
- Add I2C RTC node for m41t61 RTC
- Add I2C nodes for AD7414 temperature sensor and AT24C32CD3 EEPROM
- Fix compatible property in DMA node
- Clean up CAN nodes, remove unused "cell-index" properties
- Fix compatible property in DIU node
- USB node changes:
- use "fsl,mpc5121-usb2-dr" compatible property only
- remove "port0" and "port1" properties as these are only used
for multi-port host(MHP) module which is not available
on MPC5121.
- use 'fsl,invert-drvvbus' and 'fsl,invert-pwr-fault' in
USB node for internal PHY to specify polarities
of the appropriate port pins.
Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
Anatolij Gustschin
Grant Likely
parent
5b2b6255f2
commit
dcc79d7870
1 changed files with 33 additions and 22 deletions
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@ -62,17 +62,12 @@ nfc@40000000 {
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interrupt-parent = < &ipic >;
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#address-cells = <1>;
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#size-cells = <1>;
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bank-width = <1>;
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// ADS has two Hynix 512MB Nand flash chips in a single
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// stacked package .
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// stacked package.
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chips = <2>;
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nand0@0 {
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label = "nand0";
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reg = <0x00000000 0x02000000>; // first 32 MB of chip 0
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};
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nand1@20000000 {
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label = "nand1";
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reg = <0x20000000 0x02000000>; // first 32 MB of chip 1
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nand@0 {
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label = "nand";
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reg = <0x00000000 0x40000000>; // 512MB + 512MB
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};
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};
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@ -166,6 +161,11 @@ rtc@a00 { // Real time clock
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interrupt-parent = < &ipic >;
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};
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reset@e00 { // Reset module
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compatible = "fsl,mpc5121-reset";
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reg = <0xe00 0x100>;
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};
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clock@f00 { // Clock control
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compatible = "fsl,mpc5121-clock";
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reg = <0xf00 0x100>;
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@ -185,17 +185,15 @@ gpio@1100 {
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interrupt-parent = < &ipic >;
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};
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mscan@1300 {
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can@1300 {
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compatible = "fsl,mpc5121-mscan";
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cell-index = <0>;
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interrupts = <12 0x8>;
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interrupt-parent = < &ipic >;
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reg = <0x1300 0x80>;
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};
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mscan@1380 {
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can@1380 {
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compatible = "fsl,mpc5121-mscan";
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cell-index = <1>;
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interrupts = <13 0x8>;
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interrupt-parent = < &ipic >;
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reg = <0x1380 0x80>;
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@ -205,17 +203,31 @@ i2c@1700 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5121-i2c", "fsl-i2c";
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cell-index = <0>;
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reg = <0x1700 0x20>;
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interrupts = <9 0x8>;
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interrupt-parent = < &ipic >;
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fsl,preserve-clocking;
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hwmon@4a {
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compatible = "adi,ad7414";
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reg = <0x4a>;
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};
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eeprom@50 {
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compatible = "at,24c32";
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reg = <0x50>;
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};
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rtc@68 {
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compatible = "stm,m41t62";
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reg = <0x68>;
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};
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};
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i2c@1720 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5121-i2c", "fsl-i2c";
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cell-index = <1>;
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reg = <0x1720 0x20>;
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interrupts = <10 0x8>;
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interrupt-parent = < &ipic >;
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@ -225,7 +237,6 @@ i2c@1740 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5121-i2c", "fsl-i2c";
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cell-index = <2>;
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reg = <0x1740 0x20>;
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interrupts = <11 0x8>;
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interrupt-parent = < &ipic >;
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@ -244,7 +255,7 @@ axe@2000 {
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};
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display@2100 {
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compatible = "fsl,mpc5121-diu", "fsl-diu";
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compatible = "fsl,mpc5121-diu", "fsl,diu";
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reg = <0x2100 0x100>;
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interrupts = <64 0x8>;
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interrupt-parent = < &ipic >;
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@ -277,7 +288,7 @@ ethernet@2800 {
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// USB1 using external ULPI PHY
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//usb@3000 {
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// compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr";
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// compatible = "fsl,mpc5121-usb2-dr";
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// reg = <0x3000 0x1000>;
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// #address-cells = <1>;
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// #size-cells = <0>;
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@ -285,12 +296,11 @@ ethernet@2800 {
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// interrupts = <43 0x8>;
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// dr_mode = "otg";
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// phy_type = "ulpi";
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// port1;
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//};
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// USB0 using internal UTMI PHY
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usb@4000 {
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compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr";
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compatible = "fsl,mpc5121-usb2-dr";
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reg = <0x4000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -298,7 +308,8 @@ usb@4000 {
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interrupts = <44 0x8>;
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dr_mode = "otg";
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phy_type = "utmi_wide";
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port0;
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fsl,invert-drvvbus;
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fsl,invert-pwr-fault;
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};
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// IO control
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@ -365,7 +376,7 @@ pscfifo@11f00 {
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};
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dma@14000 {
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compatible = "fsl,mpc5121-dma2";
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compatible = "fsl,mpc5121-dma";
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reg = <0x14000 0x1800>;
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interrupts = <65 0x8>;
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interrupt-parent = < &ipic >;
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