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drm/amd/display: increase dcn315 pstate change latency
[Why & How] Update after new measurment came in Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -46,6 +46,9 @@
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#define TO_CLK_MGR_DCN315(clk_mgr)\
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container_of(clk_mgr, struct clk_mgr_dcn315, base)
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#define UNSUPPORTED_DCFCLK 10000000
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#define MIN_DPP_DISP_CLK 100000
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static int dcn315_get_active_display_cnt_wa(
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struct dc *dc,
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struct dc_state *context)
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@ -147,6 +150,9 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
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}
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}
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/* Lock pstate by requesting unsupported dcfclk if change is unsupported */
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if (!new_clocks->p_state_change_support)
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new_clocks->dcfclk_khz = UNSUPPORTED_DCFCLK;
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if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
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clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
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dcn315_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
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@ -160,10 +166,10 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
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// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
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if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
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if (new_clocks->dppclk_khz < 100000)
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new_clocks->dppclk_khz = 100000;
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if (new_clocks->dispclk_khz < 100000)
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new_clocks->dispclk_khz = 100000;
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if (new_clocks->dppclk_khz < MIN_DPP_DISP_CLK)
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new_clocks->dppclk_khz = MIN_DPP_DISP_CLK;
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if (new_clocks->dispclk_khz < MIN_DPP_DISP_CLK)
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new_clocks->dispclk_khz = MIN_DPP_DISP_CLK;
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}
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if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
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@ -276,7 +282,7 @@ static struct wm_table ddr5_wm_table = {
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{
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.wm_inst = WM_A,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 64.0,
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.pstate_latency_us = 129.0,
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.sr_exit_time_us = 11.5,
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.sr_enter_plus_exit_time_us = 14.5,
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.valid = true,
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@ -284,7 +290,7 @@ static struct wm_table ddr5_wm_table = {
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{
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.wm_inst = WM_B,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 64.0,
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.pstate_latency_us = 129.0,
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.sr_exit_time_us = 11.5,
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.sr_enter_plus_exit_time_us = 14.5,
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.valid = true,
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@ -292,7 +298,7 @@ static struct wm_table ddr5_wm_table = {
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{
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.wm_inst = WM_C,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 64.0,
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.pstate_latency_us = 129.0,
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.sr_exit_time_us = 11.5,
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.sr_enter_plus_exit_time_us = 14.5,
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.valid = true,
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@ -300,7 +306,7 @@ static struct wm_table ddr5_wm_table = {
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{
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.wm_inst = WM_D,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 64.0,
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.pstate_latency_us = 129.0,
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.sr_exit_time_us = 11.5,
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.sr_enter_plus_exit_time_us = 14.5,
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.valid = true,
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