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dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G2UL SoC
Document RZ/G2UL (R9A07G043U) IRQC bindings. The IRQC block on RZ/G2UL SoC is almost identical to one found on the RZ/G2L SoC the only difference being it can support BUS_ERR_INT for which it has additional registers. Hence new generic compatible string "renesas,r9a07g043u-irqc" is added for RZ/G2UL SoC. Now that we have additional interrupt for RZ/G2UL and RZ/Five SoC interrupt-names property is added so that we can parse them based on names. While at it updated the example node to four spaces and added interrupt-names property. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20231006121058.13890-1-prabhakar.mahadev-lad.rj@bp.renesas.com
This commit is contained in:
Lad Prabhakar
Marc Zyngier
parent
9b8df572ba
commit
db712c0089
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@ -19,13 +19,11 @@ description: |
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- NMI edge select (NMI is not treated as NMI exception and supports fall edge and
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stand-up edge detection interrupts)
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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properties:
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compatible:
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items:
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- enum:
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- renesas,r9a07g043u-irqc # RZ/G2UL
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- renesas,r9a07g044-irqc # RZ/G2{L,LC}
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- renesas,r9a07g054-irqc # RZ/V2L
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- const: renesas,rzg2l-irqc
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@ -45,7 +43,96 @@ properties:
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maxItems: 1
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interrupts:
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maxItems: 41
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minItems: 41
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items:
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- description: NMI interrupt
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- description: IRQ0 interrupt
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- description: IRQ1 interrupt
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- description: IRQ2 interrupt
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- description: IRQ3 interrupt
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- description: IRQ4 interrupt
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- description: IRQ5 interrupt
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- description: IRQ6 interrupt
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- description: IRQ7 interrupt
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- description: GPIO interrupt, TINT0
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- description: GPIO interrupt, TINT1
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- description: GPIO interrupt, TINT2
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- description: GPIO interrupt, TINT3
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- description: GPIO interrupt, TINT4
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- description: GPIO interrupt, TINT5
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- description: GPIO interrupt, TINT6
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- description: GPIO interrupt, TINT7
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- description: GPIO interrupt, TINT8
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- description: GPIO interrupt, TINT9
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- description: GPIO interrupt, TINT10
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- description: GPIO interrupt, TINT11
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- description: GPIO interrupt, TINT12
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- description: GPIO interrupt, TINT13
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- description: GPIO interrupt, TINT14
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- description: GPIO interrupt, TINT15
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- description: GPIO interrupt, TINT16
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- description: GPIO interrupt, TINT17
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- description: GPIO interrupt, TINT18
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- description: GPIO interrupt, TINT19
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- description: GPIO interrupt, TINT20
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- description: GPIO interrupt, TINT21
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- description: GPIO interrupt, TINT22
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- description: GPIO interrupt, TINT23
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- description: GPIO interrupt, TINT24
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- description: GPIO interrupt, TINT25
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- description: GPIO interrupt, TINT26
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- description: GPIO interrupt, TINT27
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- description: GPIO interrupt, TINT28
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- description: GPIO interrupt, TINT29
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- description: GPIO interrupt, TINT30
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- description: GPIO interrupt, TINT31
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- description: Bus error interrupt
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interrupt-names:
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minItems: 41
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items:
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- const: nmi
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- const: irq0
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- const: irq1
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- const: irq2
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- const: irq3
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- const: irq4
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- const: irq5
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- const: irq6
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- const: irq7
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- const: tint0
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- const: tint1
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- const: tint2
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- const: tint3
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- const: tint4
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- const: tint5
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- const: tint6
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- const: tint7
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- const: tint8
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- const: tint9
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- const: tint10
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- const: tint11
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- const: tint12
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- const: tint13
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- const: tint14
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- const: tint15
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- const: tint16
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- const: tint17
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- const: tint18
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- const: tint19
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- const: tint20
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- const: tint21
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- const: tint22
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- const: tint23
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- const: tint24
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- const: tint25
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- const: tint26
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- const: tint27
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- const: tint28
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- const: tint29
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- const: tint30
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- const: tint31
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- const: bus-err
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clocks:
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maxItems: 2
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@ -73,6 +160,23 @@ required:
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- power-domains
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- resets
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r9a07g043u-irqc
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then:
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properties:
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interrupts:
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minItems: 42
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interrupt-names:
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minItems: 42
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required:
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- interrupt-names
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unevaluatedProperties: false
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examples:
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@ -81,55 +185,66 @@ examples:
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#include <dt-bindings/clock/r9a07g044-cpg.h>
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irqc: interrupt-controller@110a0000 {
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compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
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reg = <0x110a0000 0x10000>;
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#interrupt-cells = <2>;
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#address-cells = <0>;
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interrupt-controller;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
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<&cpg CPG_MOD R9A07G044_IA55_PCLK>;
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clock-names = "clk", "pclk";
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power-domains = <&cpg>;
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resets = <&cpg R9A07G044_IA55_RESETN>;
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compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
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reg = <0x110a0000 0x10000>;
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#interrupt-cells = <2>;
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#address-cells = <0>;
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interrupt-controller;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "nmi",
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"irq0", "irq1", "irq2", "irq3",
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"irq4", "irq5", "irq6", "irq7",
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"tint0", "tint1", "tint2", "tint3",
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"tint4", "tint5", "tint6", "tint7",
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"tint8", "tint9", "tint10", "tint11",
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"tint12", "tint13", "tint14", "tint15",
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"tint16", "tint17", "tint18", "tint19",
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"tint20", "tint21", "tint22", "tint23",
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"tint24", "tint25", "tint26", "tint27",
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"tint28", "tint29", "tint30", "tint31";
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clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
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<&cpg CPG_MOD R9A07G044_IA55_PCLK>;
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clock-names = "clk", "pclk";
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power-domains = <&cpg>;
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resets = <&cpg R9A07G044_IA55_RESETN>;
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};
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