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mmc: tmio: add actual clock support as option
Some controller is supporting actual clock on SD_CLK_CTRL :: DIV[7:0]. Renesas SH-Mobile SDHI doesn't support, but, Renesas R-Car SDHI supports it. This patch adds new TMIO_MMC_CLK_ACTUAL flag for it. [Kuninori Morimoto: tidyuped for upstreaming] Tested-by: Nguyen Xuan Nui <nx-nui@jinso.co.jp> Tested-by: Hiep Cao Minh <cm-hiep@jinso.co.jp> Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -49,12 +49,14 @@ static const struct sh_mobile_sdhi_of_data sh_mobile_sdhi_of_cfg[] = {
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};
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};
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static const struct sh_mobile_sdhi_of_data of_rcar_gen1_compatible = {
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static const struct sh_mobile_sdhi_of_data of_rcar_gen1_compatible = {
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.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE,
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.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
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TMIO_MMC_CLK_ACTUAL,
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.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
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.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
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};
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};
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static const struct sh_mobile_sdhi_of_data of_rcar_gen2_compatible = {
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static const struct sh_mobile_sdhi_of_data of_rcar_gen2_compatible = {
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.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE,
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.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE |
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TMIO_MMC_CLK_ACTUAL,
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.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
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.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
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.capabilities2 = MMC_CAP2_NO_MULTI_READ,
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.capabilities2 = MMC_CAP2_NO_MULTI_READ,
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.dma_rx_offset = 0x2000,
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.dma_rx_offset = 0x2000,
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@ -159,6 +159,11 @@ static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
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for (clock = host->mmc->f_min, clk = 0x80000080;
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for (clock = host->mmc->f_min, clk = 0x80000080;
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new_clock >= (clock<<1); clk >>= 1)
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new_clock >= (clock<<1); clk >>= 1)
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clock <<= 1;
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clock <<= 1;
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/* 1/1 clock is option */
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if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) &&
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((clk >> 22) & 0x1))
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clk |= 0xff;
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}
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}
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if (host->set_clk_div)
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if (host->set_clk_div)
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@ -99,6 +99,11 @@
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*/
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*/
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#define TMIO_MMC_HAVE_CTL_DMA_REG (1 << 9)
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#define TMIO_MMC_HAVE_CTL_DMA_REG (1 << 9)
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/*
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* Some controllers allows to set SDx actual clock
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*/
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#define TMIO_MMC_CLK_ACTUAL (1 << 10)
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int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
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int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
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int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
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int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
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void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
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void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
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