mirror of
https://github.com/torvalds/linux
synced 2024-10-26 05:09:47 +00:00
perf vendor events: Add IvyTown V19 event file
Add a Intel event file for perf. Signed-off-by: Andi Kleen <ak@linux.intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Link: http://lkml.kernel.org/n/tip-p5mtp091orxty69pot9vd6ga@git.kernel.org [ Lowercased the directory and file names ] Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Andi Kleen
Arnaldo Carvalho de Melo
parent
4b90798ebb
commit
d910f0ba6d
1272
tools/perf/pmu-events/arch/x86/ivytown/cache.json
Normal file
1272
tools/perf/pmu-events/arch/x86/ivytown/cache.json
Normal file
File diff suppressed because it is too large
Load diff
151
tools/perf/pmu-events/arch/x86/ivytown/floating-point.json
Normal file
151
tools/perf/pmu-events/arch/x86/ivytown/floating-point.json
Normal file
|
|
@ -0,0 +1,151 @@
|
|||
[
|
||||
{
|
||||
"PublicDescription": "Counts number of X87 uops executed.",
|
||||
"EventCode": "0x10",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "FP_COMP_OPS_EXE.X87",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",
|
||||
"EventCode": "0x10",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x10",
|
||||
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",
|
||||
"EventCode": "0x10",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x20",
|
||||
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",
|
||||
"EventCode": "0x10",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x40",
|
||||
"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Counts number of SSE* or AVX-128 double precision FP scalar uops executed.",
|
||||
"EventCode": "0x10",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x80",
|
||||
"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Counts 256-bit packed single-precision floating-point instructions.",
|
||||
"EventCode": "0x11",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "SIMD_FP_256.PACKED_SINGLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Counts 256-bit packed double-precision floating-point instructions.",
|
||||
"EventCode": "0x11",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x2",
|
||||
"EventName": "SIMD_FP_256.PACKED_DOUBLE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Number of assists associated with 256-bit AVX store operations.",
|
||||
"EventCode": "0xC1",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x8",
|
||||
"EventName": "OTHER_ASSISTS.AVX_STORE",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC1",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x10",
|
||||
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC1",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x20",
|
||||
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Number of X87 FP assists due to output values.",
|
||||
"EventCode": "0xCA",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x2",
|
||||
"EventName": "FP_ASSIST.X87_OUTPUT",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Number of X87 assists due to output value.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Number of X87 FP assists due to input values.",
|
||||
"EventCode": "0xCA",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x4",
|
||||
"EventName": "FP_ASSIST.X87_INPUT",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Number of X87 assists due to input value.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Number of SIMD FP assists due to output values.",
|
||||
"EventCode": "0xCA",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x8",
|
||||
"EventName": "FP_ASSIST.SIMD_OUTPUT",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Number of SIMD FP assists due to Output values",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Number of SIMD FP assists due to input values.",
|
||||
"EventCode": "0xCA",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x10",
|
||||
"EventName": "FP_ASSIST.SIMD_INPUT",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Number of SIMD FP assists due to input values",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Cycles with any input/output SSE* or FP assists.",
|
||||
"EventCode": "0xCA",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1e",
|
||||
"EventName": "FP_ASSIST.ANY",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Cycles with any input/output SSE or FP assist",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
}
|
||||
]
|
||||
305
tools/perf/pmu-events/arch/x86/ivytown/frontend.json
Normal file
305
tools/perf/pmu-events/arch/x86/ivytown/frontend.json
Normal file
|
|
@ -0,0 +1,305 @@
|
|||
[
|
||||
{
|
||||
"PublicDescription": "Counts cycles the IDQ is empty.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x2",
|
||||
"EventName": "IDQ.EMPTY",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x4",
|
||||
"EventName": "IDQ.MITE_UOPS",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x8",
|
||||
"EventName": "IDQ.DSB_UOPS",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x10",
|
||||
"EventName": "IDQ.MS_DSB_UOPS",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x20",
|
||||
"EventName": "IDQ.MS_MITE_UOPS",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x30",
|
||||
"EventName": "IDQ.MS_UOPS",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x30",
|
||||
"EventName": "IDQ.MS_CYCLES",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x4",
|
||||
"EventName": "IDQ.MITE_CYCLES",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x8",
|
||||
"EventName": "IDQ.DSB_CYCLES",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x10",
|
||||
"EventName": "IDQ.MS_DSB_CYCLES",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x10",
|
||||
"EdgeDetect": "1",
|
||||
"EventName": "IDQ.MS_DSB_OCCUR",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x18",
|
||||
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
|
||||
"CounterMask": "4",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x18",
|
||||
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x24",
|
||||
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles MITE is delivering 4 Uops",
|
||||
"CounterMask": "4",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Counts cycles MITE is delivered at least one uops. Set Cmask = 1.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x24",
|
||||
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles MITE is delivering any Uop",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Number of uops delivered to IDQ from any path.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x3c",
|
||||
"EventName": "IDQ.MITE_ALL_UOPS",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
|
||||
"EventCode": "0x80",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "ICACHE.HIT",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.",
|
||||
"EventCode": "0x80",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x2",
|
||||
"EventName": "ICACHE.MISSES",
|
||||
"SampleAfterValue": "200003",
|
||||
"BriefDescription": "Instruction cache, streaming buffer and victim cache misses",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.",
|
||||
"EventCode": "0x80",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x4",
|
||||
"EventName": "ICACHE.IFETCH_STALL",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.",
|
||||
"EventCode": "0x9C",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled ",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x9C",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
|
||||
"CounterMask": "4",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x9C",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
|
||||
"CounterMask": "3",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x9C",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
|
||||
"CounterMask": "2",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x9C",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x9C",
|
||||
"Invert": "1",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Number of DSB to MITE switches.",
|
||||
"EventCode": "0xAB",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "DSB2MITE_SWITCHES.COUNT",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Cycles DSB to MITE switches caused delay.",
|
||||
"EventCode": "0xAB",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x2",
|
||||
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "DSB Fill encountered > 3 DSB lines.",
|
||||
"EventCode": "0xAC",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x8",
|
||||
"EventName": "DSB_FILL.EXCEED_DSB_LINES",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
|
||||
"EventCode": "0x79",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x30",
|
||||
"EdgeDetect": "1",
|
||||
"EventName": "IDQ.MS_SWITCHES",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
}
|
||||
]
|
||||
503
tools/perf/pmu-events/arch/x86/ivytown/memory.json
Normal file
503
tools/perf/pmu-events/arch/x86/ivytown/memory.json
Normal file
|
|
@ -0,0 +1,503 @@
|
|||
[
|
||||
{
|
||||
"PublicDescription": "Speculative cache-line split load uops dispatched to L1D.",
|
||||
"EventCode": "0x05",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "MISALIGN_MEM_REF.LOADS",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.",
|
||||
"EventCode": "0x05",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x2",
|
||||
"EventName": "MISALIGN_MEM_REF.STORES",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC3",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x2",
|
||||
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PEBS": "2",
|
||||
"EventCode": "0xCD",
|
||||
"Counter": "3",
|
||||
"UMask": "0x2",
|
||||
"EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.",
|
||||
"PRECISE_STORE": "1",
|
||||
"TakenAlone": "1",
|
||||
"CounterHTOff": "3"
|
||||
},
|
||||
{
|
||||
"PEBS": "2",
|
||||
"PublicDescription": "Loads with latency value being above 4.",
|
||||
"EventCode": "0xCD",
|
||||
"MSRValue": "0x4",
|
||||
"Counter": "3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
|
||||
"MSRIndex": "0x3F6",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Loads with latency value being above 4",
|
||||
"TakenAlone": "1",
|
||||
"CounterHTOff": "3"
|
||||
},
|
||||
{
|
||||
"PEBS": "2",
|
||||
"PublicDescription": "Loads with latency value being above 8.",
|
||||
"EventCode": "0xCD",
|
||||
"MSRValue": "0x8",
|
||||
"Counter": "3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
|
||||
"MSRIndex": "0x3F6",
|
||||
"SampleAfterValue": "50021",
|
||||
"BriefDescription": "Loads with latency value being above 8",
|
||||
"TakenAlone": "1",
|
||||
"CounterHTOff": "3"
|
||||
},
|
||||
{
|
||||
"PEBS": "2",
|
||||
"PublicDescription": "Loads with latency value being above 16.",
|
||||
"EventCode": "0xCD",
|
||||
"MSRValue": "0x10",
|
||||
"Counter": "3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
|
||||
"MSRIndex": "0x3F6",
|
||||
"SampleAfterValue": "20011",
|
||||
"BriefDescription": "Loads with latency value being above 16",
|
||||
"TakenAlone": "1",
|
||||
"CounterHTOff": "3"
|
||||
},
|
||||
{
|
||||
"PEBS": "2",
|
||||
"PublicDescription": "Loads with latency value being above 32.",
|
||||
"EventCode": "0xCD",
|
||||
"MSRValue": "0x20",
|
||||
"Counter": "3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
|
||||
"MSRIndex": "0x3F6",
|
||||
"SampleAfterValue": "100007",
|
||||
"BriefDescription": "Loads with latency value being above 32",
|
||||
"TakenAlone": "1",
|
||||
"CounterHTOff": "3"
|
||||
},
|
||||
{
|
||||
"PEBS": "2",
|
||||
"PublicDescription": "Loads with latency value being above 64.",
|
||||
"EventCode": "0xCD",
|
||||
"MSRValue": "0x40",
|
||||
"Counter": "3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
|
||||
"MSRIndex": "0x3F6",
|
||||
"SampleAfterValue": "2003",
|
||||
"BriefDescription": "Loads with latency value being above 64",
|
||||
"TakenAlone": "1",
|
||||
"CounterHTOff": "3"
|
||||
},
|
||||
{
|
||||
"PEBS": "2",
|
||||
"PublicDescription": "Loads with latency value being above 128.",
|
||||
"EventCode": "0xCD",
|
||||
"MSRValue": "0x80",
|
||||
"Counter": "3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
|
||||
"MSRIndex": "0x3F6",
|
||||
"SampleAfterValue": "1009",
|
||||
"BriefDescription": "Loads with latency value being above 128",
|
||||
"TakenAlone": "1",
|
||||
"CounterHTOff": "3"
|
||||
},
|
||||
{
|
||||
"PEBS": "2",
|
||||
"PublicDescription": "Loads with latency value being above 256.",
|
||||
"EventCode": "0xCD",
|
||||
"MSRValue": "0x100",
|
||||
"Counter": "3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
|
||||
"MSRIndex": "0x3F6",
|
||||
"SampleAfterValue": "503",
|
||||
"BriefDescription": "Loads with latency value being above 256",
|
||||
"TakenAlone": "1",
|
||||
"CounterHTOff": "3"
|
||||
},
|
||||
{
|
||||
"PEBS": "2",
|
||||
"PublicDescription": "Loads with latency value being above 512.",
|
||||
"EventCode": "0xCD",
|
||||
"MSRValue": "0x200",
|
||||
"Counter": "3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
|
||||
"MSRIndex": "0x3F6",
|
||||
"SampleAfterValue": "101",
|
||||
"BriefDescription": "Loads with latency value being above 512",
|
||||
"TakenAlone": "1",
|
||||
"CounterHTOff": "3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x3fffc00244",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts all demand & prefetch code reads that miss the LLC",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x67f800244",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_DRAM",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from remote dram",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x87f800244",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data forwarded from remote cache",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x3fffc20091",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts all demand & prefetch data reads that hits the LLC",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x3fffc203f7",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit the LLC",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x6004003f7",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from local dram",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x87f8203f7",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data forwarded from remote cache",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x107fc003f7",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC the data is found in M state in remote cache and forwarded from there",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x3fffc20004",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts all demand code reads that miss the LLC",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x600400004",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from local dram",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x67f800004",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from remote dram",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x87f820004",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts all demand code reads that miss the LLC and the data forwarded from remote cache",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x107fc00004",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x67fc00001",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote & local dram",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x3fffc20001",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts demand data reads that miss in the LLC",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x600400001",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from local dram",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x67f800001",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote dram",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x87f820001",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts demand data reads that miss the LLC and the data forwarded from remote cache",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x107fc00001",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x107fc20002",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts all demand data writes (RFOs) that miss the LLC and the data is found in M state in remote cache and forwarded from there.",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x3fffc20040",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x67fc00010",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x3fffc20010",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x600400010",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x67f800010",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x87f820010",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x107fc00010",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x3fffc20200",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB7, 0xBB",
|
||||
"MSRValue": "0x3fffc20080",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"Offcore": "1",
|
||||
"EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",
|
||||
"MSRIndex": "0x1a6,0x1a7",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that miss in the LLC",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
}
|
||||
]
|
||||
44
tools/perf/pmu-events/arch/x86/ivytown/other.json
Normal file
44
tools/perf/pmu-events/arch/x86/ivytown/other.json
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
[
|
||||
{
|
||||
"PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
|
||||
"EventCode": "0x5C",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "CPL_CYCLES.RING0",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
|
||||
"EventCode": "0x5C",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x2",
|
||||
"EventName": "CPL_CYCLES.RING123",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Number of intervals between processor halts while thread is in ring 0.",
|
||||
"EventCode": "0x5C",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EdgeDetect": "1",
|
||||
"EventName": "CPL_CYCLES.RING0_TRANS",
|
||||
"SampleAfterValue": "100007",
|
||||
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
|
||||
"CounterMask": "1",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
|
||||
"EventCode": "0x63",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
}
|
||||
]
|
||||
1307
tools/perf/pmu-events/arch/x86/ivytown/pipeline.json
Normal file
1307
tools/perf/pmu-events/arch/x86/ivytown/pipeline.json
Normal file
File diff suppressed because it is too large
Load diff
198
tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json
Normal file
198
tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json
Normal file
|
|
@ -0,0 +1,198 @@
|
|||
[
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x82",
|
||||
"EventName": "DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x84",
|
||||
"EventName": "DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x08",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x88",
|
||||
"EventName": "DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Page walk for a large page completed for Demand load.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
|
||||
"EventCode": "0x49",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G).",
|
||||
"EventCode": "0x49",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x2",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Cycles PMH is busy with this walk.",
|
||||
"EventCode": "0x49",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x4",
|
||||
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles when PMH is busy with page walks",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
|
||||
"EventCode": "0x49",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x10",
|
||||
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x4F",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x10",
|
||||
"EventName": "EPT.WALK_CYCLES",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Counts load operations that missed 1st level DTLB but hit the 2nd level.",
|
||||
"EventCode": "0x5F",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x4",
|
||||
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Misses in all ITLB levels that cause page walks.",
|
||||
"EventCode": "0x85",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Misses at all ITLB levels that cause page walks",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Misses in all ITLB levels that cause completed page walks.",
|
||||
"EventCode": "0x85",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x2",
|
||||
"EventName": "ITLB_MISSES.WALK_COMPLETED",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Misses in all ITLB levels that cause completed page walks",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Cycle PMH is busy with a walk.",
|
||||
"EventCode": "0x85",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x4",
|
||||
"EventName": "ITLB_MISSES.WALK_DURATION",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Cycles when PMH is busy with page walks",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Number of cache load STLB hits. No page walk.",
|
||||
"EventCode": "0x85",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x10",
|
||||
"EventName": "ITLB_MISSES.STLB_HIT",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.",
|
||||
"EventCode": "0x85",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x80",
|
||||
"EventName": "ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.",
|
||||
"EventCode": "0xAE",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "ITLB.ITLB_FLUSH",
|
||||
"SampleAfterValue": "100007",
|
||||
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "DTLB flush attempts of the thread-specific entries.",
|
||||
"EventCode": "0xBD",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x1",
|
||||
"EventName": "TLB_FLUSH.DTLB_THREAD",
|
||||
"SampleAfterValue": "100007",
|
||||
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Count number of STLB flush attempts.",
|
||||
"EventCode": "0xBD",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x20",
|
||||
"EventName": "TLB_FLUSH.STLB_ANY",
|
||||
"SampleAfterValue": "100007",
|
||||
"BriefDescription": "STLB flush attempts",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand loads.",
|
||||
"EventCode": "0x08",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x81",
|
||||
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by demand loads.",
|
||||
"EventCode": "0x08",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x82",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
|
||||
"SampleAfterValue": "100003",
|
||||
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"PublicDescription": "Cycle PMH is busy with a walk due to demand loads.",
|
||||
"EventCode": "0x08",
|
||||
"Counter": "0,1,2,3",
|
||||
"UMask": "0x84",
|
||||
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
|
||||
"SampleAfterValue": "2000003",
|
||||
"BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
}
|
||||
]
|
||||
|
|
@ -14,3 +14,4 @@ GenuineIntel-6-45,v24,haswell,core
|
|||
GenuineIntel-6-46,v24,haswell,core
|
||||
GenuineIntel-6-3F,v17,haswellx,core
|
||||
GenuineIntel-6-3A,v18,ivybridge,core
|
||||
GenuineIntel-6-3E,v19,ivytown,core
|
||||
|
|
|
|||
|
Loading…
Reference in a new issue