mirror of
https://github.com/torvalds/linux
synced 2024-09-22 12:26:27 +00:00
Merge branch 'clk-shmobile-for-v4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
This commit is contained in:
Michael Turquette
commit
d90e149666
|
|
@ -20,6 +20,10 @@ Required Properties:
|
|||
clocks must be specified. For clocks with multiple parents, invalid
|
||||
settings must be specified as "<0>".
|
||||
- #clock-cells: Must be 0
|
||||
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- clock-output-names: The name of the clock as a free-form string
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||||
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||||
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||||
|
|
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|||
|
|
@ -71,6 +71,7 @@ obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
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|||
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
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obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
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obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile/
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obj-$(CONFIG_ARCH_RENESAS) += shmobile/
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obj-$(CONFIG_ARCH_SIRF) += sirf/
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obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
|
||||
obj-$(CONFIG_PLAT_SPEAR) += spear/
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||||
|
|
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|||
|
|
@ -1,13 +1,13 @@
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obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o
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obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o
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obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o
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obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o
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obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o
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obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
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obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o
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obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o
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obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o
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obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o
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obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o
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obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-div6.o
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obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-mstp.o
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obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o clk-mstp.o
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obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o clk-mstp.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o clk-mstp.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o clk-mstp.o
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obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o clk-mstp.o
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obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7793) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
|
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obj-$(CONFIG_ARCH_R8A7794) += clk-rcar-gen2.o clk-mstp.o clk-div6.o
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obj-$(CONFIG_ARCH_R8A7795) += renesas-cpg-mssr.o \
|
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r8a7795-cpg-mssr.o clk-div6.o
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obj-$(CONFIG_ARCH_SH73A0) += clk-sh73a0.o clk-mstp.o clk-div6.o
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|
|
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@ -18,6 +18,8 @@
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include "clk-div6.h"
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|
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#define CPG_DIV6_CKSTP BIT(8)
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#define CPG_DIV6_DIV(d) ((d) & 0x3f)
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#define CPG_DIV6_DIV_MASK 0x3f
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@ -172,67 +174,44 @@ static const struct clk_ops cpg_div6_clock_ops = {
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.set_rate = cpg_div6_clock_set_rate,
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};
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|
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static void __init cpg_div6_clock_init(struct device_node *np)
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|
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/**
|
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* cpg_div6_register - Register a DIV6 clock
|
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* @name: Name of the DIV6 clock
|
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* @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8)
|
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* @parent_names: Array containing the names of the parent clocks
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* @reg: Mapped register used to control the DIV6 clock
|
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*/
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struct clk * __init cpg_div6_register(const char *name,
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unsigned int num_parents,
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const char **parent_names,
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void __iomem *reg)
|
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{
|
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unsigned int num_parents, valid_parents;
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const char **parent_names;
|
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unsigned int valid_parents;
|
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struct clk_init_data init;
|
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struct div6_clock *clock;
|
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const char *name;
|
||||
struct clk *clk;
|
||||
unsigned int i;
|
||||
int ret;
|
||||
|
||||
clock = kzalloc(sizeof(*clock), GFP_KERNEL);
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||||
if (!clock)
|
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return;
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|
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num_parents = of_clk_get_parent_count(np);
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if (num_parents < 1) {
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pr_err("%s: no parent found for %s DIV6 clock\n",
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__func__, np->name);
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return;
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}
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return ERR_PTR(-ENOMEM);
|
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|
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clock->parents = kmalloc_array(num_parents, sizeof(*clock->parents),
|
||||
GFP_KERNEL);
|
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parent_names = kmalloc_array(num_parents, sizeof(*parent_names),
|
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GFP_KERNEL);
|
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if (!parent_names)
|
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return;
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GFP_KERNEL);
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if (!clock->parents) {
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clk = ERR_PTR(-ENOMEM);
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goto free_clock;
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}
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|
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/* Remap the clock register and read the divisor. Disabling the
|
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* clock overwrites the divisor, so we need to cache its value for the
|
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* enable operation.
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clock->reg = reg;
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|
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/*
|
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* Read the divisor. Disabling the clock overwrites the divisor, so we
|
||||
* need to cache its value for the enable operation.
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*/
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clock->reg = of_iomap(np, 0);
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if (clock->reg == NULL) {
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pr_err("%s: failed to map %s DIV6 clock register\n",
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__func__, np->name);
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goto error;
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}
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clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
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/* Parse the DT properties. */
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ret = of_property_read_string(np, "clock-output-names", &name);
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if (ret < 0) {
|
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pr_err("%s: failed to get %s DIV6 clock output name\n",
|
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__func__, np->name);
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goto error;
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}
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|
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|
||||
for (i = 0, valid_parents = 0; i < num_parents; i++) {
|
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const char *name = of_clk_get_parent_name(np, i);
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if (name) {
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parent_names[valid_parents] = name;
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clock->parents[valid_parents] = i;
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valid_parents++;
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}
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}
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switch (num_parents) {
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case 1:
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/* fixed parent clock */
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@ -250,8 +229,18 @@ static void __init cpg_div6_clock_init(struct device_node *np)
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break;
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default:
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pr_err("%s: invalid number of parents for DIV6 clock %s\n",
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__func__, np->name);
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goto error;
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__func__, name);
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clk = ERR_PTR(-EINVAL);
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goto free_parents;
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}
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|
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/* Filter out invalid parents */
|
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for (i = 0, valid_parents = 0; i < num_parents; i++) {
|
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if (parent_names[i]) {
|
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parent_names[valid_parents] = parent_names[i];
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clock->parents[valid_parents] = i;
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valid_parents++;
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}
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}
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/* Register the clock. */
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@ -264,6 +253,53 @@ static void __init cpg_div6_clock_init(struct device_node *np)
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clock->hw.init = &init;
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clk = clk_register(NULL, &clock->hw);
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if (IS_ERR(clk))
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goto free_parents;
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return clk;
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free_parents:
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kfree(clock->parents);
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free_clock:
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kfree(clock);
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return clk;
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}
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static void __init cpg_div6_clock_init(struct device_node *np)
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{
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unsigned int num_parents;
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const char **parent_names;
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const char *clk_name = np->name;
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void __iomem *reg;
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struct clk *clk;
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unsigned int i;
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num_parents = of_clk_get_parent_count(np);
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if (num_parents < 1) {
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pr_err("%s: no parent found for %s DIV6 clock\n",
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__func__, np->name);
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return;
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}
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parent_names = kmalloc_array(num_parents, sizeof(*parent_names),
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GFP_KERNEL);
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if (!parent_names)
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return;
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reg = of_iomap(np, 0);
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if (reg == NULL) {
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pr_err("%s: failed to map %s DIV6 clock register\n",
|
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__func__, np->name);
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goto error;
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}
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/* Parse the DT properties. */
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of_property_read_string(np, "clock-output-names", &clk_name);
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for (i = 0; i < num_parents; i++)
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parent_names[i] = of_clk_get_parent_name(np, i);
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clk = cpg_div6_register(clk_name, num_parents, parent_names, reg);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register %s DIV6 clock (%ld)\n",
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__func__, np->name, PTR_ERR(clk));
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@ -276,9 +312,8 @@ static void __init cpg_div6_clock_init(struct device_node *np)
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return;
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|
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error:
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if (clock->reg)
|
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iounmap(clock->reg);
|
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if (reg)
|
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iounmap(reg);
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kfree(parent_names);
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kfree(clock);
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}
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CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);
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|
|
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7
drivers/clk/shmobile/clk-div6.h
Normal file
7
drivers/clk/shmobile/clk-div6.h
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
#ifndef __SHMOBILE_CLK_DIV6_H__
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#define __SHMOBILE_CLK_DIV6_H__
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|
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struct clk *cpg_div6_register(const char *name, unsigned int num_parents,
|
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const char **parent_names, void __iomem *reg);
|
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|
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#endif
|
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382
drivers/clk/shmobile/r8a7795-cpg-mssr.c
Normal file
382
drivers/clk/shmobile/r8a7795-cpg-mssr.c
Normal file
|
|
@ -0,0 +1,382 @@
|
|||
/*
|
||||
* r8a7795 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
*
|
||||
* Based on clk-rcar-gen3.c
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A7795_CLK_OSC,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_EXTALR,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL2,
|
||||
CLK_PLL3,
|
||||
CLK_PLL4,
|
||||
CLK_PLL1_DIV2,
|
||||
CLK_PLL1_DIV4,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_SSPSRC,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
enum r8a7795_clk_types {
|
||||
CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
|
||||
CLK_TYPE_GEN3_PLL0,
|
||||
CLK_TYPE_GEN3_PLL1,
|
||||
CLK_TYPE_GEN3_PLL2,
|
||||
CLK_TYPE_GEN3_PLL3,
|
||||
CLK_TYPE_GEN3_PLL4,
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("extalr", CLK_EXTALR),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll2", CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
|
||||
DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
|
||||
DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
|
||||
DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
|
||||
DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1),
|
||||
DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1),
|
||||
DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
|
||||
DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
|
||||
DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
|
||||
DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
|
||||
DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("scif1", 206, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("scif0", 207, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("msiof3", 208, R8A7795_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
|
||||
DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("audmac1", 501, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("vspd2", 621, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("vspd1", 622, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("vspd0", 623, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("vspbc", 624, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("vspbd", 626, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("vspi1", 630, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("vspi0", 631, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("du3", 721, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("du2", 722, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("du1", 723, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("du0", 724, R8A7795_CLK_S2D1),
|
||||
DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
|
||||
DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
|
||||
DEF_MOD("etheravb", 812, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("gpio7", 905, R8A7795_CLK_CP),
|
||||
DEF_MOD("gpio6", 906, R8A7795_CLK_CP),
|
||||
DEF_MOD("gpio5", 907, R8A7795_CLK_CP),
|
||||
DEF_MOD("gpio4", 908, R8A7795_CLK_CP),
|
||||
DEF_MOD("gpio3", 909, R8A7795_CLK_CP),
|
||||
DEF_MOD("gpio2", 910, R8A7795_CLK_CP),
|
||||
DEF_MOD("gpio1", 911, R8A7795_CLK_CP),
|
||||
DEF_MOD("gpio0", 912, R8A7795_CLK_CP),
|
||||
DEF_MOD("i2c6", 918, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("i2c5", 919, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("i2c4", 927, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("i2c3", 928, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("i2c2", 929, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("ssi-all", 1005, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
static const unsigned int r8a7795_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(408), /* INTC-AP (GIC) */
|
||||
};
|
||||
|
||||
|
||||
#define CPG_PLL0CR 0x00d8
|
||||
#define CPG_PLL2CR 0x002c
|
||||
#define CPG_PLL4CR 0x01f4
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
|
||||
* 14 13 19 17 (MHz)
|
||||
*-------------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
|
||||
* 0 0 1 0 Prohibited setting
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
|
||||
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
|
||||
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
|
||||
* 0 1 1 0 Prohibited setting
|
||||
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
|
||||
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
|
||||
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
|
||||
* 1 0 1 0 Prohibited setting
|
||||
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
|
||||
* 1 1 1 0 Prohibited setting
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
|
||||
(((md) & BIT(13)) >> 11) | \
|
||||
(((md) & BIT(19)) >> 18) | \
|
||||
(((md) & BIT(17)) >> 17))
|
||||
|
||||
struct cpg_pll_config {
|
||||
unsigned int extal_div;
|
||||
unsigned int pll1_mult;
|
||||
unsigned int pll3_mult;
|
||||
};
|
||||
|
||||
static const struct cpg_pll_config cpg_pll_configs[16] __initconst = {
|
||||
/* EXTAL div PLL1 mult PLL3 mult */
|
||||
{ 1, 192, 192, },
|
||||
{ 1, 192, 128, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 192, },
|
||||
{ 1, 160, 160, },
|
||||
{ 1, 160, 106, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 160, },
|
||||
{ 1, 128, 128, },
|
||||
{ 1, 128, 84, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 128, },
|
||||
{ 2, 192, 192, },
|
||||
{ 2, 192, 128, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 192, },
|
||||
};
|
||||
|
||||
static const struct cpg_pll_config *cpg_pll_config __initdata;
|
||||
|
||||
static
|
||||
struct clk * __init r8a7795_cpg_clk_register(struct device *dev,
|
||||
const struct cpg_core_clk *core,
|
||||
const struct cpg_mssr_info *info,
|
||||
struct clk **clks,
|
||||
void __iomem *base)
|
||||
{
|
||||
const struct clk *parent;
|
||||
unsigned int mult = 1;
|
||||
unsigned int div = 1;
|
||||
u32 value;
|
||||
|
||||
parent = clks[core->parent];
|
||||
if (IS_ERR(parent))
|
||||
return ERR_CAST(parent);
|
||||
|
||||
switch (core->type) {
|
||||
case CLK_TYPE_GEN3_MAIN:
|
||||
div = cpg_pll_config->extal_div;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN3_PLL0:
|
||||
/*
|
||||
* PLL0 is a configurable multiplier clock. Register it as a
|
||||
* fixed factor clock for now as there's no generic multiplier
|
||||
* clock implementation and we currently have no need to change
|
||||
* the multiplier value.
|
||||
*/
|
||||
value = readl(base + CPG_PLL0CR);
|
||||
mult = (((value >> 24) & 0x7f) + 1) * 2;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN3_PLL1:
|
||||
mult = cpg_pll_config->pll1_mult;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN3_PLL2:
|
||||
/*
|
||||
* PLL2 is a configurable multiplier clock. Register it as a
|
||||
* fixed factor clock for now as there's no generic multiplier
|
||||
* clock implementation and we currently have no need to change
|
||||
* the multiplier value.
|
||||
*/
|
||||
value = readl(base + CPG_PLL2CR);
|
||||
mult = (((value >> 24) & 0x7f) + 1) * 2;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN3_PLL3:
|
||||
mult = cpg_pll_config->pll3_mult;
|
||||
break;
|
||||
|
||||
case CLK_TYPE_GEN3_PLL4:
|
||||
/*
|
||||
* PLL4 is a configurable multiplier clock. Register it as a
|
||||
* fixed factor clock for now as there's no generic multiplier
|
||||
* clock implementation and we currently have no need to change
|
||||
* the multiplier value.
|
||||
*/
|
||||
value = readl(base + CPG_PLL4CR);
|
||||
mult = (((value >> 24) & 0x7f) + 1) * 2;
|
||||
break;
|
||||
|
||||
default:
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
return clk_register_fixed_factor(NULL, core->name,
|
||||
__clk_get_name(parent), 0, mult, div);
|
||||
}
|
||||
|
||||
/*
|
||||
* Reset register definitions.
|
||||
*/
|
||||
#define MODEMR 0xe6160060
|
||||
|
||||
static u32 rcar_gen3_read_mode_pins(void)
|
||||
{
|
||||
void __iomem *modemr = ioremap_nocache(MODEMR, 4);
|
||||
u32 mode;
|
||||
|
||||
BUG_ON(!modemr);
|
||||
mode = ioread32(modemr);
|
||||
iounmap(modemr);
|
||||
|
||||
return mode;
|
||||
}
|
||||
|
||||
static int __init r8a7795_cpg_mssr_init(struct device *dev)
|
||||
{
|
||||
u32 cpg_mode = rcar_gen3_read_mode_pins();
|
||||
|
||||
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
if (!cpg_pll_config->extal_div) {
|
||||
dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = {
|
||||
/* Core Clocks */
|
||||
.core_clks = r8a7795_core_clks,
|
||||
.num_core_clks = ARRAY_SIZE(r8a7795_core_clks),
|
||||
.last_dt_core_clk = LAST_DT_CORE_CLK,
|
||||
.num_total_core_clks = MOD_CLK_BASE,
|
||||
|
||||
/* Module Clocks */
|
||||
.mod_clks = r8a7795_mod_clks,
|
||||
.num_mod_clks = ARRAY_SIZE(r8a7795_mod_clks),
|
||||
.num_hw_mod_clks = 12 * 32,
|
||||
|
||||
/* Critical Module Clocks */
|
||||
.crit_mod_clks = r8a7795_crit_mod_clks,
|
||||
.num_crit_mod_clks = ARRAY_SIZE(r8a7795_crit_mod_clks),
|
||||
|
||||
/* Callbacks */
|
||||
.init = r8a7795_cpg_mssr_init,
|
||||
.cpg_clk_register = r8a7795_cpg_clk_register,
|
||||
};
|
||||
596
drivers/clk/shmobile/renesas-cpg-mssr.c
Normal file
596
drivers/clk/shmobile/renesas-cpg-mssr.c
Normal file
|
|
@ -0,0 +1,596 @@
|
|||
/*
|
||||
* Renesas Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
*
|
||||
* Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
|
||||
*
|
||||
* Copyright (C) 2013 Ideas On Board SPRL
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_clock.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "clk-div6.h"
|
||||
|
||||
#ifdef DEBUG
|
||||
#define WARN_DEBUG(x) do { } while (0)
|
||||
#else
|
||||
#define WARN_DEBUG(x) WARN_ON(x)
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Module Standby and Software Reset register offets.
|
||||
*
|
||||
* If the registers exist, these are valid for SH-Mobile, R-Mobile,
|
||||
* R-Car Gen 2, and R-Car Gen 3.
|
||||
* These are NOT valid for R-Car Gen1 and RZ/A1!
|
||||
*/
|
||||
|
||||
/*
|
||||
* Module Stop Status Register offsets
|
||||
*/
|
||||
|
||||
static const u16 mstpsr[] = {
|
||||
0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
|
||||
0x9A0, 0x9A4, 0x9A8, 0x9AC,
|
||||
};
|
||||
|
||||
#define MSTPSR(i) mstpsr[i]
|
||||
|
||||
|
||||
/*
|
||||
* System Module Stop Control Register offsets
|
||||
*/
|
||||
|
||||
static const u16 smstpcr[] = {
|
||||
0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
|
||||
0x990, 0x994, 0x998, 0x99C,
|
||||
};
|
||||
|
||||
#define SMSTPCR(i) smstpcr[i]
|
||||
|
||||
|
||||
/*
|
||||
* Software Reset Register offsets
|
||||
*/
|
||||
|
||||
static const u16 srcr[] = {
|
||||
0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
|
||||
0x920, 0x924, 0x928, 0x92C,
|
||||
};
|
||||
|
||||
#define SRCR(i) srcr[i]
|
||||
|
||||
|
||||
/* Realtime Module Stop Control Register offsets */
|
||||
#define RMSTPCR(i) (smstpcr[i] - 0x20)
|
||||
|
||||
/* Modem Module Stop Control Register offsets (r8a73a4) */
|
||||
#define MMSTPCR(i) (smstpcr[i] + 0x20)
|
||||
|
||||
/* Software Reset Clearing Register offsets */
|
||||
#define SRSTCLR(i) (0x940 + (i) * 4)
|
||||
|
||||
|
||||
/**
|
||||
* Clock Pulse Generator / Module Standby and Software Reset Private Data
|
||||
*
|
||||
* @dev: CPG/MSSR device
|
||||
* @base: CPG/MSSR register block base address
|
||||
* @mstp_lock: protects writes to SMSTPCR
|
||||
* @clks: Array containing all Core and Module Clocks
|
||||
* @num_core_clks: Number of Core Clocks in clks[]
|
||||
* @num_mod_clks: Number of Module Clocks in clks[]
|
||||
* @last_dt_core_clk: ID of the last Core Clock exported to DT
|
||||
*/
|
||||
struct cpg_mssr_priv {
|
||||
struct device *dev;
|
||||
void __iomem *base;
|
||||
spinlock_t mstp_lock;
|
||||
|
||||
struct clk **clks;
|
||||
unsigned int num_core_clks;
|
||||
unsigned int num_mod_clks;
|
||||
unsigned int last_dt_core_clk;
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* struct mstp_clock - MSTP gating clock
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @index: MSTP clock number
|
||||
* @priv: CPG/MSSR private data
|
||||
*/
|
||||
struct mstp_clock {
|
||||
struct clk_hw hw;
|
||||
u32 index;
|
||||
struct cpg_mssr_priv *priv;
|
||||
};
|
||||
|
||||
#define to_mstp_clock(_hw) container_of(_hw, struct mstp_clock, hw)
|
||||
|
||||
static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
|
||||
{
|
||||
struct mstp_clock *clock = to_mstp_clock(hw);
|
||||
struct cpg_mssr_priv *priv = clock->priv;
|
||||
unsigned int reg = clock->index / 32;
|
||||
unsigned int bit = clock->index % 32;
|
||||
struct device *dev = priv->dev;
|
||||
u32 bitmask = BIT(bit);
|
||||
unsigned long flags;
|
||||
unsigned int i;
|
||||
u32 value;
|
||||
|
||||
dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
|
||||
enable ? "ON" : "OFF");
|
||||
spin_lock_irqsave(&priv->mstp_lock, flags);
|
||||
|
||||
value = clk_readl(priv->base + SMSTPCR(reg));
|
||||
if (enable)
|
||||
value &= ~bitmask;
|
||||
else
|
||||
value |= bitmask;
|
||||
clk_writel(value, priv->base + SMSTPCR(reg));
|
||||
|
||||
spin_unlock_irqrestore(&priv->mstp_lock, flags);
|
||||
|
||||
if (!enable)
|
||||
return 0;
|
||||
|
||||
for (i = 1000; i > 0; --i) {
|
||||
if (!(clk_readl(priv->base + MSTPSR(reg)) &
|
||||
bitmask))
|
||||
break;
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
if (!i) {
|
||||
dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
|
||||
priv->base + SMSTPCR(reg), bit);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cpg_mstp_clock_enable(struct clk_hw *hw)
|
||||
{
|
||||
return cpg_mstp_clock_endisable(hw, true);
|
||||
}
|
||||
|
||||
static void cpg_mstp_clock_disable(struct clk_hw *hw)
|
||||
{
|
||||
cpg_mstp_clock_endisable(hw, false);
|
||||
}
|
||||
|
||||
static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct mstp_clock *clock = to_mstp_clock(hw);
|
||||
struct cpg_mssr_priv *priv = clock->priv;
|
||||
u32 value;
|
||||
|
||||
value = clk_readl(priv->base + MSTPSR(clock->index / 32));
|
||||
|
||||
return !(value & BIT(clock->index % 32));
|
||||
}
|
||||
|
||||
static const struct clk_ops cpg_mstp_clock_ops = {
|
||||
.enable = cpg_mstp_clock_enable,
|
||||
.disable = cpg_mstp_clock_disable,
|
||||
.is_enabled = cpg_mstp_clock_is_enabled,
|
||||
};
|
||||
|
||||
static
|
||||
struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
|
||||
void *data)
|
||||
{
|
||||
unsigned int clkidx = clkspec->args[1];
|
||||
struct cpg_mssr_priv *priv = data;
|
||||
struct device *dev = priv->dev;
|
||||
unsigned int idx;
|
||||
const char *type;
|
||||
struct clk *clk;
|
||||
|
||||
switch (clkspec->args[0]) {
|
||||
case CPG_CORE:
|
||||
type = "core";
|
||||
if (clkidx > priv->last_dt_core_clk) {
|
||||
dev_err(dev, "Invalid %s clock index %u\n", type,
|
||||
clkidx);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
clk = priv->clks[clkidx];
|
||||
break;
|
||||
|
||||
case CPG_MOD:
|
||||
type = "module";
|
||||
idx = MOD_CLK_PACK(clkidx);
|
||||
if (clkidx % 100 > 31 || idx >= priv->num_mod_clks) {
|
||||
dev_err(dev, "Invalid %s clock index %u\n", type,
|
||||
clkidx);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
clk = priv->clks[priv->num_core_clks + idx];
|
||||
break;
|
||||
|
||||
default:
|
||||
dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
if (IS_ERR(clk))
|
||||
dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
|
||||
PTR_ERR(clk));
|
||||
else
|
||||
dev_dbg(dev, "clock (%u, %u) is %pC at %pCr Hz\n",
|
||||
clkspec->args[0], clkspec->args[1], clk, clk);
|
||||
return clk;
|
||||
}
|
||||
|
||||
static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
|
||||
const struct cpg_mssr_info *info,
|
||||
struct cpg_mssr_priv *priv)
|
||||
{
|
||||
struct clk *clk = NULL, *parent;
|
||||
struct device *dev = priv->dev;
|
||||
unsigned int id = core->id;
|
||||
const char *parent_name;
|
||||
|
||||
WARN_DEBUG(id >= priv->num_core_clks);
|
||||
WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
|
||||
|
||||
switch (core->type) {
|
||||
case CLK_TYPE_IN:
|
||||
clk = of_clk_get_by_name(priv->dev->of_node, core->name);
|
||||
break;
|
||||
|
||||
case CLK_TYPE_FF:
|
||||
case CLK_TYPE_DIV6P1:
|
||||
WARN_DEBUG(core->parent >= priv->num_core_clks);
|
||||
parent = priv->clks[core->parent];
|
||||
if (IS_ERR(parent)) {
|
||||
clk = parent;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
parent_name = __clk_get_name(parent);
|
||||
if (core->type == CLK_TYPE_FF) {
|
||||
clk = clk_register_fixed_factor(NULL, core->name,
|
||||
parent_name, 0,
|
||||
core->mult, core->div);
|
||||
} else {
|
||||
clk = cpg_div6_register(core->name, 1, &parent_name,
|
||||
priv->base + core->offset);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
if (info->cpg_clk_register)
|
||||
clk = info->cpg_clk_register(dev, core, info,
|
||||
priv->clks, priv->base);
|
||||
else
|
||||
dev_err(dev, "%s has unsupported core clock type %u\n",
|
||||
core->name, core->type);
|
||||
break;
|
||||
}
|
||||
|
||||
if (IS_ERR_OR_NULL(clk))
|
||||
goto fail;
|
||||
|
||||
dev_dbg(dev, "Core clock %pC at %pCr Hz\n", clk, clk);
|
||||
priv->clks[id] = clk;
|
||||
return;
|
||||
|
||||
fail:
|
||||
dev_err(dev, "Failed to register %s clock %s: %ld\n", "core,",
|
||||
core->name, PTR_ERR(clk));
|
||||
}
|
||||
|
||||
static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
|
||||
const struct cpg_mssr_info *info,
|
||||
struct cpg_mssr_priv *priv)
|
||||
{
|
||||
struct mstp_clock *clock = NULL;
|
||||
struct device *dev = priv->dev;
|
||||
unsigned int id = mod->id;
|
||||
struct clk_init_data init;
|
||||
struct clk *parent, *clk;
|
||||
const char *parent_name;
|
||||
unsigned int i;
|
||||
|
||||
WARN_DEBUG(id < priv->num_core_clks);
|
||||
WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
|
||||
WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
|
||||
WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
|
||||
|
||||
parent = priv->clks[mod->parent];
|
||||
if (IS_ERR(parent)) {
|
||||
clk = parent;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
clock = kzalloc(sizeof(*clock), GFP_KERNEL);
|
||||
if (!clock) {
|
||||
clk = ERR_PTR(-ENOMEM);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
init.name = mod->name;
|
||||
init.ops = &cpg_mstp_clock_ops;
|
||||
init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
|
||||
for (i = 0; i < info->num_crit_mod_clks; i++)
|
||||
if (id == info->crit_mod_clks[i]) {
|
||||
#ifdef CLK_ENABLE_HAND_OFF
|
||||
dev_dbg(dev, "MSTP %s setting CLK_ENABLE_HAND_OFF\n",
|
||||
mod->name);
|
||||
init.flags |= CLK_ENABLE_HAND_OFF;
|
||||
break;
|
||||
#else
|
||||
dev_dbg(dev, "Ignoring MSTP %s to prevent disabling\n",
|
||||
mod->name);
|
||||
return;
|
||||
#endif
|
||||
}
|
||||
|
||||
parent_name = __clk_get_name(parent);
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
clock->index = id - priv->num_core_clks;
|
||||
clock->priv = priv;
|
||||
clock->hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &clock->hw);
|
||||
if (IS_ERR(clk))
|
||||
goto fail;
|
||||
|
||||
dev_dbg(dev, "Module clock %pC at %pCr Hz\n", clk, clk);
|
||||
priv->clks[id] = clk;
|
||||
return;
|
||||
|
||||
fail:
|
||||
dev_err(dev, "Failed to register %s clock %s: %ld\n", "module,",
|
||||
mod->name, PTR_ERR(clk));
|
||||
kfree(clock);
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
|
||||
struct cpg_mssr_clk_domain {
|
||||
struct generic_pm_domain genpd;
|
||||
struct device_node *np;
|
||||
unsigned int num_core_pm_clks;
|
||||
unsigned int core_pm_clks[0];
|
||||
};
|
||||
|
||||
static bool cpg_mssr_is_pm_clk(const struct of_phandle_args *clkspec,
|
||||
struct cpg_mssr_clk_domain *pd)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
if (clkspec->np != pd->np || clkspec->args_count != 2)
|
||||
return false;
|
||||
|
||||
switch (clkspec->args[0]) {
|
||||
case CPG_CORE:
|
||||
for (i = 0; i < pd->num_core_pm_clks; i++)
|
||||
if (clkspec->args[1] == pd->core_pm_clks[i])
|
||||
return true;
|
||||
return false;
|
||||
|
||||
case CPG_MOD:
|
||||
return true;
|
||||
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static int cpg_mssr_attach_dev(struct generic_pm_domain *genpd,
|
||||
struct device *dev)
|
||||
{
|
||||
struct cpg_mssr_clk_domain *pd =
|
||||
container_of(genpd, struct cpg_mssr_clk_domain, genpd);
|
||||
struct device_node *np = dev->of_node;
|
||||
struct of_phandle_args clkspec;
|
||||
struct clk *clk;
|
||||
int i = 0;
|
||||
int error;
|
||||
|
||||
while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
|
||||
&clkspec)) {
|
||||
if (cpg_mssr_is_pm_clk(&clkspec, pd))
|
||||
goto found;
|
||||
|
||||
of_node_put(clkspec.np);
|
||||
i++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
found:
|
||||
clk = of_clk_get_from_provider(&clkspec);
|
||||
of_node_put(clkspec.np);
|
||||
|
||||
if (IS_ERR(clk))
|
||||
return PTR_ERR(clk);
|
||||
|
||||
error = pm_clk_create(dev);
|
||||
if (error) {
|
||||
dev_err(dev, "pm_clk_create failed %d\n", error);
|
||||
goto fail_put;
|
||||
}
|
||||
|
||||
error = pm_clk_add_clk(dev, clk);
|
||||
if (error) {
|
||||
dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
|
||||
goto fail_destroy;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
fail_destroy:
|
||||
pm_clk_destroy(dev);
|
||||
fail_put:
|
||||
clk_put(clk);
|
||||
return error;
|
||||
}
|
||||
|
||||
static void cpg_mssr_detach_dev(struct generic_pm_domain *genpd,
|
||||
struct device *dev)
|
||||
{
|
||||
if (!list_empty(&dev->power.subsys_data->clock_list))
|
||||
pm_clk_destroy(dev);
|
||||
}
|
||||
|
||||
static int __init cpg_mssr_add_clk_domain(struct device *dev,
|
||||
const unsigned int *core_pm_clks,
|
||||
unsigned int num_core_pm_clks)
|
||||
{
|
||||
struct device_node *np = dev->of_node;
|
||||
struct generic_pm_domain *genpd;
|
||||
struct cpg_mssr_clk_domain *pd;
|
||||
size_t pm_size = num_core_pm_clks * sizeof(core_pm_clks[0]);
|
||||
|
||||
pd = devm_kzalloc(dev, sizeof(*pd) + pm_size, GFP_KERNEL);
|
||||
if (!pd)
|
||||
return -ENOMEM;
|
||||
|
||||
pd->np = np;
|
||||
pd->num_core_pm_clks = num_core_pm_clks;
|
||||
memcpy(pd->core_pm_clks, core_pm_clks, pm_size);
|
||||
|
||||
genpd = &pd->genpd;
|
||||
genpd->name = np->name;
|
||||
genpd->flags = GENPD_FLAG_PM_CLK;
|
||||
pm_genpd_init(genpd, &simple_qos_governor, false);
|
||||
genpd->attach_dev = cpg_mssr_attach_dev;
|
||||
genpd->detach_dev = cpg_mssr_detach_dev;
|
||||
|
||||
of_genpd_add_provider_simple(np, genpd);
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
static inline int cpg_mssr_add_clk_domain(struct device *dev,
|
||||
const unsigned int *core_pm_clks,
|
||||
unsigned int num_core_pm_clks)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* !CONFIG_PM_GENERIC_DOMAINS_OF */
|
||||
|
||||
|
||||
static const struct of_device_id cpg_mssr_match[] = {
|
||||
#ifdef CONFIG_ARCH_R8A7795
|
||||
{
|
||||
.compatible = "renesas,r8a7795-cpg-mssr",
|
||||
.data = &r8a7795_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static void cpg_mssr_del_clk_provider(void *data)
|
||||
{
|
||||
of_clk_del_provider(data);
|
||||
}
|
||||
|
||||
static int __init cpg_mssr_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
const struct cpg_mssr_info *info;
|
||||
struct cpg_mssr_priv *priv;
|
||||
unsigned int nclks, i;
|
||||
struct resource *res;
|
||||
struct clk **clks;
|
||||
int error;
|
||||
|
||||
info = of_match_node(cpg_mssr_match, np)->data;
|
||||
if (info->init) {
|
||||
error = info->init(dev);
|
||||
if (error)
|
||||
return error;
|
||||
}
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->dev = dev;
|
||||
spin_lock_init(&priv->mstp_lock);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
priv->base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(priv->base))
|
||||
return PTR_ERR(priv->base);
|
||||
|
||||
nclks = info->num_total_core_clks + info->num_hw_mod_clks;
|
||||
clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
|
||||
if (!clks)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->clks = clks;
|
||||
priv->num_core_clks = info->num_total_core_clks;
|
||||
priv->num_mod_clks = info->num_hw_mod_clks;
|
||||
priv->last_dt_core_clk = info->last_dt_core_clk;
|
||||
|
||||
for (i = 0; i < nclks; i++)
|
||||
clks[i] = ERR_PTR(-ENOENT);
|
||||
|
||||
for (i = 0; i < info->num_core_clks; i++)
|
||||
cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
|
||||
|
||||
for (i = 0; i < info->num_mod_clks; i++)
|
||||
cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
|
||||
|
||||
error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
devm_add_action(dev, cpg_mssr_del_clk_provider, np);
|
||||
|
||||
error = cpg_mssr_add_clk_domain(dev, info->core_pm_clks,
|
||||
info->num_core_pm_clks);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver cpg_mssr_driver = {
|
||||
.driver = {
|
||||
.name = "renesas-cpg-mssr",
|
||||
.of_match_table = cpg_mssr_match,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init cpg_mssr_init(void)
|
||||
{
|
||||
return platform_driver_probe(&cpg_mssr_driver, cpg_mssr_probe);
|
||||
}
|
||||
|
||||
subsys_initcall(cpg_mssr_init);
|
||||
|
||||
MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
132
drivers/clk/shmobile/renesas-cpg-mssr.h
Normal file
132
drivers/clk/shmobile/renesas-cpg-mssr.h
Normal file
|
|
@ -0,0 +1,132 @@
|
|||
/*
|
||||
* Renesas Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#ifndef __CLK_RENESAS_CPG_MSSR_H__
|
||||
#define __CLK_RENESAS_CPG_MSSR_H__
|
||||
|
||||
/*
|
||||
* Definitions of CPG Core Clocks
|
||||
*
|
||||
* These include:
|
||||
* - Clock outputs exported to DT
|
||||
* - External input clocks
|
||||
* - Internal CPG clocks
|
||||
*/
|
||||
|
||||
struct cpg_core_clk {
|
||||
/* Common */
|
||||
const char *name;
|
||||
unsigned int id;
|
||||
unsigned int type;
|
||||
/* Depending on type */
|
||||
unsigned int parent; /* Core Clocks only */
|
||||
unsigned int div;
|
||||
unsigned int mult;
|
||||
unsigned int offset;
|
||||
};
|
||||
|
||||
enum clk_types {
|
||||
/* Generic */
|
||||
CLK_TYPE_IN, /* External Clock Input */
|
||||
CLK_TYPE_FF, /* Fixed Factor Clock */
|
||||
CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
|
||||
|
||||
/* Custom definitions start here */
|
||||
CLK_TYPE_CUSTOM,
|
||||
};
|
||||
|
||||
#define DEF_TYPE(_name, _id, _type...) \
|
||||
{ .name = _name, .id = _id, .type = _type }
|
||||
#define DEF_BASE(_name, _id, _type, _parent...) \
|
||||
DEF_TYPE(_name, _id, _type, .parent = _parent)
|
||||
|
||||
#define DEF_INPUT(_name, _id) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_IN)
|
||||
#define DEF_FIXED(_name, _id, _parent, _div, _mult) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
|
||||
#define DEF_DIV6P1(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
|
||||
|
||||
|
||||
/*
|
||||
* Definitions of Module Clocks
|
||||
*/
|
||||
|
||||
struct mssr_mod_clk {
|
||||
const char *name;
|
||||
unsigned int id;
|
||||
unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */
|
||||
};
|
||||
|
||||
/* Convert from sparse base-100 to packed index space */
|
||||
#define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
|
||||
|
||||
#define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))
|
||||
|
||||
#define DEF_MOD(_name, _mod, _parent...) \
|
||||
{ .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
|
||||
|
||||
|
||||
struct device_node;
|
||||
|
||||
/**
|
||||
* SoC-specific CPG/MSSR Description
|
||||
*
|
||||
* @core_clks: Array of Core Clock definitions
|
||||
* @num_core_clks: Number of entries in core_clks[]
|
||||
* @last_dt_core_clk: ID of the last Core Clock exported to DT
|
||||
* @num_total_core_clks: Total number of Core Clocks (exported + internal)
|
||||
*
|
||||
* @mod_clks: Array of Module Clock definitions
|
||||
* @num_mod_clks: Number of entries in mod_clks[]
|
||||
* @num_hw_mod_clks: Number of Module Clocks supported by the hardware
|
||||
*
|
||||
* @crit_mod_clks: Array with Module Clock IDs of critical clocks that
|
||||
* should not be disabled without a knowledgeable driver
|
||||
* @num_crit_mod_clks: Number of entries in crit_mod_clks[]
|
||||
*
|
||||
* @core_pm_clks: Array with IDs of Core Clocks that are suitable for Power
|
||||
* Management, in addition to Module Clocks
|
||||
* @num_core_pm_clks: Number of entries in core_pm_clks[]
|
||||
*
|
||||
* @init: Optional callback to perform SoC-specific initialization
|
||||
* @cpg_clk_register: Optional callback to handle special Core Clock types
|
||||
*/
|
||||
|
||||
struct cpg_mssr_info {
|
||||
/* Core Clocks */
|
||||
const struct cpg_core_clk *core_clks;
|
||||
unsigned int num_core_clks;
|
||||
unsigned int last_dt_core_clk;
|
||||
unsigned int num_total_core_clks;
|
||||
|
||||
/* Module Clocks */
|
||||
const struct mssr_mod_clk *mod_clks;
|
||||
unsigned int num_mod_clks;
|
||||
unsigned int num_hw_mod_clks;
|
||||
|
||||
/* Critical Module Clocks that should not be disabled */
|
||||
const unsigned int *crit_mod_clks;
|
||||
unsigned int num_crit_mod_clks;
|
||||
|
||||
/* Core Clocks suitable for PM, in addition to the Module Clocks */
|
||||
const unsigned int *core_pm_clks;
|
||||
unsigned int num_core_pm_clks;
|
||||
|
||||
/* Callbacks */
|
||||
int (*init)(struct device *dev);
|
||||
struct clk *(*cpg_clk_register)(struct device *dev,
|
||||
const struct cpg_core_clk *core,
|
||||
const struct cpg_mssr_info *info,
|
||||
struct clk **clks, void __iomem *base);
|
||||
};
|
||||
|
||||
extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
|
||||
#endif
|
||||
Loading…
Reference in a new issue