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https://github.com/torvalds/linux
synced 2024-11-05 18:23:50 +00:00
staging: fbtft: add fb_ra8875 driver
This commit adds the fb_ra8875 driver from the fbtft project at https://github.com/notro/fbtft. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Noralf Tronnes <notro@tronnes.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Thomas Petazzoni
Greg Kroah-Hartman
parent
39c3907243
commit
d8a53a9d0b
3 changed files with 338 additions and 0 deletions
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@ -79,3 +79,9 @@ config FB_TFT_PCD8544
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depends on FB_TFT
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help
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Generic Framebuffer support for PCD8544
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config FB_TFT_RA8875
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tristate "FB driver for the RA8875 LCD Controller"
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depends on FB_TFT
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help
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Generic Framebuffer support for RA8875
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@ -15,3 +15,4 @@ obj-$(CONFIG_FB_TFT_ILI9341) += fb_ili9341.o
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obj-$(CONFIG_FB_TFT_ILI9481) += fb_ili9481.o
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obj-$(CONFIG_FB_TFT_ILI9486) += fb_ili9486.o
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obj-$(CONFIG_FB_TFT_PCD8544) += fb_pcd8544.o
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obj-$(CONFIG_FB_TFT_RA8875) += fb_ra8875.o
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331
drivers/staging/fbtft/fb_ra8875.c
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331
drivers/staging/fbtft/fb_ra8875.c
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@ -0,0 +1,331 @@
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/******************************************************************************
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ProjectName: FBTFT driver ***** *****
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for the RA8875 LCD Controller * * ************
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* ** ** * *
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Copyright © by Pf@nne & NOTRO * * * * * **** *
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* * * * * * *
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Last modification by: * * * * **** *
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- Pf@nne (pf@nne-mail.de) * * ***** *
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* * * *******
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***** * *
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Date : 10.06.2014 * *
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Version : V1.13 *****
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Revison : 5
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*******************************************************************************
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include "fbtft.h"
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#define DRVNAME "fb_ra8875"
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static int write_spi(struct fbtft_par *par, void *buf, size_t len)
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{
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struct spi_transfer t = {
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.tx_buf = buf,
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.len = len,
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.speed_hz = 1000000,
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};
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struct spi_message m;
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fbtft_par_dbg_hex(DEBUG_WRITE, par, par->info->device, u8, buf, len,
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"%s(len=%d): ", __func__, len);
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if (!par->spi) {
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dev_err(par->info->device,
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"%s: par->spi is unexpectedly NULL\n", __func__);
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return -1;
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}
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spi_message_init(&m);
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if (par->txbuf.dma && buf == par->txbuf.buf) {
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t.tx_dma = par->txbuf.dma;
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m.is_dma_mapped = 1;
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}
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spi_message_add_tail(&t, &m);
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return spi_sync(par->spi, &m);
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}
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static int init_display(struct fbtft_par *par)
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{
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gpio_set_value(par->gpio.dc, 1);
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fbtft_par_dbg(DEBUG_INIT_DISPLAY, par,
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"%s()\n", __func__);
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fbtft_par_dbg(DEBUG_INIT_DISPLAY, par,
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"display size %dx%d\n", par->info->var.xres, par->info->var.yres);
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par->fbtftops.reset(par);
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if ((par->info->var.xres == 320) && (par->info->var.yres == 240)) {
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/* PLL clock frequency */
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write_reg(par, 0x88 , 0x0A);
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write_reg(par, 0x89 , 0x02);
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mdelay(10);
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/* color deep / MCU Interface */
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write_reg(par, 0x10 , 0x0C);
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/* pixel clock period */
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write_reg(par, 0x04 , 0x03);
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mdelay(1);
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/* horizontal settings */
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write_reg(par, 0x14 , 0x27);
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write_reg(par, 0x15 , 0x00);
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write_reg(par, 0x16 , 0x05);
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write_reg(par, 0x17 , 0x04);
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write_reg(par, 0x18 , 0x03);
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/* vertical settings */
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write_reg(par, 0x19 , 0xEF);
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write_reg(par, 0x1A , 0x00);
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write_reg(par, 0x1B , 0x05);
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write_reg(par, 0x1C , 0x00);
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write_reg(par, 0x1D , 0x0E);
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write_reg(par, 0x1E , 0x00);
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write_reg(par, 0x1F , 0x02);
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} else if ((par->info->var.xres == 480) && (par->info->var.yres == 272)) {
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/* PLL clock frequency */
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write_reg(par, 0x88 , 0x0A);
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write_reg(par, 0x89 , 0x02);
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mdelay(10);
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/* color deep / MCU Interface */
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write_reg(par, 0x10 , 0x0C);
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/* pixel clock period */
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write_reg(par, 0x04 , 0x82);
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mdelay(1);
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/* horizontal settings */
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write_reg(par, 0x14 , 0x3B);
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write_reg(par, 0x15 , 0x00);
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write_reg(par, 0x16 , 0x01);
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write_reg(par, 0x17 , 0x00);
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write_reg(par, 0x18 , 0x05);
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/* vertical settings */
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write_reg(par, 0x19 , 0x0F);
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write_reg(par, 0x1A , 0x01);
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write_reg(par, 0x1B , 0x02);
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write_reg(par, 0x1C , 0x00);
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write_reg(par, 0x1D , 0x07);
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write_reg(par, 0x1E , 0x00);
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write_reg(par, 0x1F , 0x09);
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} else if ((par->info->var.xres == 640) && (par->info->var.yres == 480)) {
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/* PLL clock frequency */
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write_reg(par, 0x88 , 0x0B);
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write_reg(par, 0x89 , 0x02);
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mdelay(10);
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/* color deep / MCU Interface */
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write_reg(par, 0x10 , 0x0C);
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/* pixel clock period */
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write_reg(par, 0x04 , 0x01);
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mdelay(1);
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/* horizontal settings */
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write_reg(par, 0x14 , 0x4F);
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write_reg(par, 0x15 , 0x05);
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write_reg(par, 0x16 , 0x0F);
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write_reg(par, 0x17 , 0x01);
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write_reg(par, 0x18 , 0x00);
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/* vertical settings */
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write_reg(par, 0x19 , 0xDF);
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write_reg(par, 0x1A , 0x01);
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write_reg(par, 0x1B , 0x0A);
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write_reg(par, 0x1C , 0x00);
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write_reg(par, 0x1D , 0x0E);
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write_reg(par, 0x1E , 0x00);
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write_reg(par, 0x1F , 0x01);
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} else if ((par->info->var.xres == 800) && (par->info->var.yres == 480)) {
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/* PLL clock frequency */
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write_reg(par, 0x88 , 0x0B);
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write_reg(par, 0x89 , 0x02);
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mdelay(10);
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/* color deep / MCU Interface */
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write_reg(par, 0x10 , 0x0C);
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/* pixel clock period */
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write_reg(par, 0x04 , 0x81);
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mdelay(1);
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/* horizontal settings */
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write_reg(par, 0x14 , 0x63);
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write_reg(par, 0x15 , 0x03);
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write_reg(par, 0x16 , 0x03);
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write_reg(par, 0x17 , 0x02);
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write_reg(par, 0x18 , 0x00);
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/* vertical settings */
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write_reg(par, 0x19 , 0xDF);
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write_reg(par, 0x1A , 0x01);
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write_reg(par, 0x1B , 0x14);
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write_reg(par, 0x1C , 0x00);
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write_reg(par, 0x1D , 0x06);
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write_reg(par, 0x1E , 0x00);
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write_reg(par, 0x1F , 0x01);
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} else {
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dev_err(par->info->device, "display size is not supported!!");
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return -1;
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}
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/* PWM clock */
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write_reg(par, 0x8a , 0x81);
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write_reg(par, 0x8b , 0xFF);
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mdelay(10);
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/* Display ON */
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write_reg(par, 0x01 , 0x80);
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mdelay(10);
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return 0;
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}
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static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
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{
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fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
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"%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
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/* Set_Active_Window */
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write_reg(par, 0x30 , xs & 0x00FF);
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write_reg(par, 0x31 , (xs & 0xFF00) >> 8);
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write_reg(par, 0x32 , ys & 0x00FF);
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write_reg(par, 0x33 , (ys & 0xFF00) >> 8);
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write_reg(par, 0x34 , (xs+xe) & 0x00FF);
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write_reg(par, 0x35 , ((xs+xe) & 0xFF00) >> 8);
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write_reg(par, 0x36 , (ys+ye) & 0x00FF);
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write_reg(par, 0x37 , ((ys+ye) & 0xFF00) >> 8);
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/* Set_Memory_Write_Cursor */
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write_reg(par, 0x46, xs & 0xff);
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write_reg(par, 0x47, (xs >> 8) & 0x03);
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write_reg(par, 0x48, ys & 0xff);
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write_reg(par, 0x49, (ys >> 8) & 0x01);
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write_reg(par, 0x02);
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}
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static void write_reg8_bus8(struct fbtft_par *par, int len, ...)
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{
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va_list args;
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int i, ret;
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u8 *buf = (u8 *)par->buf;
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/* slow down spi-speed for writing registers */
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par->fbtftops.write = write_spi;
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if (unlikely(par->debug & DEBUG_WRITE_REGISTER)) {
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va_start(args, len);
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for (i = 0; i < len; i++)
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buf[i] = (u8)va_arg(args, unsigned int);
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va_end(args);
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fbtft_par_dbg_hex(DEBUG_WRITE_REGISTER, par, par->info->device,
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u8, buf, len, "%s: ", __func__);
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}
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va_start(args, len);
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*buf++ = 0x80;
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*buf = (u8)va_arg(args, unsigned int);
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ret = par->fbtftops.write(par, par->buf, 2);
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if (ret < 0) {
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va_end(args);
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dev_err(par->info->device, "%s: write() failed and returned %dn",
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__func__, ret);
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return;
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}
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len--;
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udelay(100);
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if (len) {
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buf = (u8 *)par->buf;
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*buf++ = 0x00;
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i = len;
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while (i--)
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*buf++ = (u8)va_arg(args, unsigned int);
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ret = par->fbtftops.write(par, par->buf, len + 1);
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if (ret < 0) {
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va_end(args);
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dev_err(par->info->device, "%s: write() failed and returned %dn",
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__func__, ret);
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return;
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}
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}
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va_end(args);
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/* restore user spi-speed */
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par->fbtftops.write = fbtft_write_spi;
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udelay(100);
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}
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static int write_vmem16_bus8(struct fbtft_par *par, size_t offset, size_t len)
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{
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u16 *vmem16;
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u16 *txbuf16 = (u16 *)par->txbuf.buf;
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size_t remain;
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size_t to_copy;
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size_t tx_array_size;
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int i;
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int ret = 0;
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size_t startbyte_size = 0;
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fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "%s(offset=%zu, len=%zu)\n",
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__func__, offset, len);
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remain = len / 2;
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vmem16 = (u16 *)(par->info->screen_base + offset);
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tx_array_size = par->txbuf.len / 2;
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txbuf16 = (u16 *)(par->txbuf.buf + 1);
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tx_array_size -= 2;
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*(u8 *)(par->txbuf.buf) = 0x00;
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startbyte_size = 1;
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while (remain) {
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to_copy = remain > tx_array_size ? tx_array_size : remain;
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dev_dbg(par->info->device, " to_copy=%zu, remain=%zu\n",
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to_copy, remain - to_copy);
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for (i = 0; i < to_copy; i++)
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txbuf16[i] = cpu_to_be16(vmem16[i]);
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vmem16 = vmem16 + to_copy;
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ret = par->fbtftops.write(par, par->txbuf.buf,
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startbyte_size + to_copy * 2);
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if (ret < 0)
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return ret;
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remain -= to_copy;
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}
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return ret;
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}
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static struct fbtft_display display = {
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.regwidth = 8,
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.fbtftops = {
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.init_display = init_display,
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.set_addr_win = set_addr_win,
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.write_register = write_reg8_bus8,
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.write_vmem = write_vmem16_bus8,
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.write = write_spi,
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},
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};
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FBTFT_REGISTER_DRIVER(DRVNAME, "raio,ra8875", &display);
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MODULE_ALIAS("spi:" DRVNAME);
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MODULE_ALIAS("platform:" DRVNAME);
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MODULE_ALIAS("spi:ra8875");
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MODULE_ALIAS("platform:ra8875");
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MODULE_DESCRIPTION("FB driver for the RA8875 LCD Controller");
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MODULE_AUTHOR("Pf@nne");
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MODULE_LICENSE("GPL");
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