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arm64: dts: imx8mn: Add display pipeline components
Add LCDIF scanout engine and DSIM bridge nodes for i.MX8M Nano. This makes the DSI display pipeline available on this SoC. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -1057,6 +1057,61 @@ aips4: bus@32c00000 {
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#size-cells = <1>;
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ranges;
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lcdif: lcdif@32e00000 {
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compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif";
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reg = <0x32e00000 0x10000>;
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clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
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<&clk IMX8MN_CLK_DISP_APB_ROOT>,
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<&clk IMX8MN_CLK_DISP_AXI_ROOT>;
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clock-names = "pix", "axi", "disp_axi";
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assigned-clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
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<&clk IMX8MN_CLK_DISP_AXI>,
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<&clk IMX8MN_CLK_DISP_APB>;
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assigned-clock-parents = <&clk IMX8MN_CLK_DISP_PIXEL>,
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<&clk IMX8MN_SYS_PLL2_1000M>,
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<&clk IMX8MN_SYS_PLL1_800M>;
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assigned-clock-rates = <594000000>, <500000000>, <200000000>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>;
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status = "disabled";
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port {
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lcdif_to_dsim: endpoint {
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remote-endpoint = <&dsim_from_lcdif>;
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};
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};
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};
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mipi_dsi: dsi@32e10000 {
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compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim";
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reg = <0x32e10000 0x400>;
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clocks = <&clk IMX8MN_CLK_DSI_CORE>,
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<&clk IMX8MN_CLK_DSI_PHY_REF>;
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clock-names = "bus_clk", "sclk_mipi";
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assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
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<&clk IMX8MN_CLK_DSI_PHY_REF>;
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assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
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<&clk IMX8MN_CLK_24M>;
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assigned-clock-rates = <266000000>, <24000000>;
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samsung,pll-clock-frequency = <24000000>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsim_from_lcdif: endpoint {
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remote-endpoint = <&lcdif_to_dsim>;
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};
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};
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};
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};
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disp_blk_ctrl: blk-ctrl@32e28000 {
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compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
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reg = <0x32e28000 0x100>;
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