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[MIPS] MT: Reenable EIC support and add support for SOCit SC.
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
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ef300e4223
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d725cf3818
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@ -1557,6 +1557,7 @@ config MIPS_MT_SMP
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bool "Use 1 TC on each available VPE for SMP"
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bool "Use 1 TC on each available VPE for SMP"
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depends on SYS_SUPPORTS_MULTITHREADING
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depends on SYS_SUPPORTS_MULTITHREADING
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select CPU_MIPSR2_IRQ_VI
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select CPU_MIPSR2_IRQ_VI
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select CPU_MIPSR2_IRQ_EI
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select CPU_MIPSR2_SRS
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select CPU_MIPSR2_SRS
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select MIPS_MT
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select MIPS_MT
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select NR_CPUS_DEFAULT_2
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select NR_CPUS_DEFAULT_2
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@ -1572,6 +1573,7 @@ config MIPS_MT_SMTC
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#depends on CPU_MIPS64_R2 # once there is hardware ...
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#depends on CPU_MIPS64_R2 # once there is hardware ...
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depends on SYS_SUPPORTS_MULTITHREADING
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depends on SYS_SUPPORTS_MULTITHREADING
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select CPU_MIPSR2_IRQ_VI
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select CPU_MIPSR2_IRQ_VI
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select CPU_MIPSR2_IRQ_EI
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select CPU_MIPSR2_SRS
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select CPU_MIPSR2_SRS
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select MIPS_MT
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select MIPS_MT
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select NR_CPUS_DEFAULT_8
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select NR_CPUS_DEFAULT_8
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@ -1584,6 +1586,8 @@ config MIPS_MT_SMTC
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config MIPS_VPE_LOADER
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config MIPS_VPE_LOADER
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bool "VPE loader support."
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bool "VPE loader support."
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depends on SYS_SUPPORTS_MULTITHREADING
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depends on SYS_SUPPORTS_MULTITHREADING
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select CPU_MIPSR2_IRQ_VI
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select CPU_MIPSR2_IRQ_EI
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select MIPS_MT
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select MIPS_MT
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help
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help
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Includes a loader for loading an elf relocatable object
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Includes a loader for loading an elf relocatable object
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@ -132,11 +132,11 @@ struct irq_chip msc_edgeirq_type = {
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};
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};
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void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
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void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq)
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{
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{
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extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset);
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extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset);
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_icctrl_msc = (unsigned long) ioremap (MIPS_MSC01_IC_REG_BASE, 0x40000);
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_icctrl_msc = (unsigned long) ioremap (icubase, 0x40000);
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/* Reset interrupt controller - initialises all registers to 0 */
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/* Reset interrupt controller - initialises all registers to 0 */
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MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
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MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
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@ -148,14 +148,14 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
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switch (imp->im_type) {
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switch (imp->im_type) {
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case MSC01_IRQ_EDGE:
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case MSC01_IRQ_EDGE:
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set_irq_chip(base+n, &msc_edgeirq_type);
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set_irq_chip(irqbase+n, &msc_edgeirq_type);
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if (cpu_has_veic)
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if (cpu_has_veic)
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MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
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MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
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else
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else
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MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
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MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
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break;
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break;
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case MSC01_IRQ_LEVEL:
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case MSC01_IRQ_LEVEL:
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set_irq_chip(base+n, &msc_levelirq_type);
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set_irq_chip(irqbase+n, &msc_levelirq_type);
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if (cpu_has_veic)
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if (cpu_has_veic)
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MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
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MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
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else
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else
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@ -163,7 +163,7 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
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}
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}
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}
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}
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irq_base = base;
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irq_base = irqbase;
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MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */
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MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */
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@ -311,16 +311,21 @@ void __init arch_init_irq(void)
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if (!cpu_has_veic)
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if (!cpu_has_veic)
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mips_cpu_irq_init();
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mips_cpu_irq_init();
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switch(mips_revision_corid) {
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switch(mips_revision_sconid) {
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case MIPS_REVISION_CORID_CORE_MSC:
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case MIPS_REVISION_SCON_SOCIT:
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case MIPS_REVISION_CORID_CORE_FPGA2:
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case MIPS_REVISION_SCON_ROCIT:
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case MIPS_REVISION_CORID_CORE_FPGA3:
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case MIPS_REVISION_CORID_CORE_24K:
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case MIPS_REVISION_CORID_CORE_EMUL_MSC:
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if (cpu_has_veic)
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if (cpu_has_veic)
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init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
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init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
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else
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else
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init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
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init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
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break;
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case MIPS_REVISION_SCON_SOCITSC:
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case MIPS_REVISION_SCON_SOCITSCP:
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if (cpu_has_veic)
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init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
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else
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init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
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}
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}
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if (cpu_has_veic) {
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if (cpu_has_veic) {
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@ -25,6 +25,10 @@
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#include <asm/mips-boards/msc01_pci.h>
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#include <asm/mips-boards/msc01_pci.h>
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#include <asm/gt64120.h>
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#include <asm/gt64120.h>
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/* Mips interrupt controller found in SOCit variations */
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#define MIPS_MSC01_IC_REG_BASE 0x1bc40000
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#define MIPS_SOCITSC_IC_REG_BASE 0x1ffa0000
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/*
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/*
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* Malta I/O ports base address for the Galileo GT64120 and Algorithmics
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* Malta I/O ports base address for the Galileo GT64120 and Algorithmics
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* Bonito system controllers.
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* Bonito system controllers.
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@ -94,10 +94,7 @@
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/*
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/*
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* MIPS System controller interrupt register base.
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* MIPS System controller interrupt register base.
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*
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*
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* FIXME - are these macros specific to Malta and co or to the MSC? If the
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* latter, they should be moved elsewhere.
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*/
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*/
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#define MIPS_MSC01_IC_REG_BASE 0x1bc40000
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/*****************************************************************************
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/*****************************************************************************
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* Absolute register addresses
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* Absolute register addresses
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@ -144,7 +141,7 @@ typedef struct msc_irqmap {
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#define MSC01_IRQ_LEVEL 0
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#define MSC01_IRQ_LEVEL 0
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#define MSC01_IRQ_EDGE 1
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#define MSC01_IRQ_EDGE 1
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extern void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq);
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extern void __init init_msc_irqs(unsigned long icubase, unsigned int base, msc_irqmap_t *imp, int nirq);
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extern void ll_msc_irq(void);
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extern void ll_msc_irq(void);
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#endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */
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#endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */
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