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scsi: ufs: ufs-renesas: Add support for Renesas R-Car UFS controller
Add support for Renesas R-Car UFS controller which needs vendor-specific initialization. Link: https://lore.kernel.org/r/20220603110524.1997825-5-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Yoshihiro Shimoda
Martin K. Petersen
parent
2f11bbc2c7
commit
d69520288e
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@ -92,6 +92,18 @@ config SCSI_UFS_HISI
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Select this if you have UFS controller on Hisilicon chipset.
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If unsure, say N.
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config SCSI_UFS_RENESAS
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tristate "Renesas specific hooks to UFS controller platform driver"
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depends on (ARCH_RENESAS || COMPILE_TEST) && SCSI_UFSHCD_PLATFORM
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help
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This selects the Renesas specific additions to UFSHCD platform driver.
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UFS host on Renesas needs some vendor specific configuration before
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accessing the hardware.
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Select this if you have UFS controller on Renesas chipset.
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If unsure, say N.
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config SCSI_UFS_TI_J721E
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tristate "TI glue layer for Cadence UFS Controller"
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depends on OF && HAS_IOMEM && (ARCH_K3 || COMPILE_TEST)
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@ -11,4 +11,5 @@ obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o
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obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o
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obj-$(CONFIG_SCSI_UFS_HISI) += ufs-hisi.o
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obj-$(CONFIG_SCSI_UFS_MEDIATEK) += ufs-mediatek.o
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obj-$(CONFIG_SCSI_UFS_RENESAS) += ufs-renesas.o
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obj-$(CONFIG_SCSI_UFS_TI_J721E) += ti-j721e-ufs.o
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412
drivers/ufs/host/ufs-renesas.c
Normal file
412
drivers/ufs/host/ufs-renesas.c
Normal file
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@ -0,0 +1,412 @@
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// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Renesas UFS host controller driver
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*
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* Copyright (C) 2022 Renesas Electronics Corporation
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pm_runtime.h>
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#include <ufs/ufshcd.h>
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#include "ufshcd-pltfrm.h"
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struct ufs_renesas_priv {
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bool initialized; /* The hardware needs initialization once */
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};
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enum {
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SET_PHY_INDEX_LO = 0,
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SET_PHY_INDEX_HI,
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TIMER_INDEX,
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MAX_INDEX
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};
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enum ufs_renesas_init_param_mode {
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MODE_RESTORE,
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MODE_SET,
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MODE_SAVE,
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MODE_POLL,
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MODE_WAIT,
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MODE_WRITE,
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};
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#define PARAM_RESTORE(_reg, _index) \
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{ .mode = MODE_RESTORE, .reg = _reg, .index = _index }
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#define PARAM_SET(_index, _set) \
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{ .mode = MODE_SET, .index = _index, .u.set = _set }
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#define PARAM_SAVE(_reg, _mask, _index) \
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{ .mode = MODE_SAVE, .reg = _reg, .mask = (u32)(_mask), \
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.index = _index }
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#define PARAM_POLL(_reg, _expected, _mask) \
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{ .mode = MODE_POLL, .reg = _reg, .u.expected = _expected, \
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.mask = (u32)(_mask) }
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#define PARAM_WAIT(_delay_us) \
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{ .mode = MODE_WAIT, .u.delay_us = _delay_us }
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#define PARAM_WRITE(_reg, _val) \
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{ .mode = MODE_WRITE, .reg = _reg, .u.val = _val }
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#define PARAM_WRITE_D0_D4(_d0, _d4) \
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PARAM_WRITE(0xd0, _d0), PARAM_WRITE(0xd4, _d4)
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#define PARAM_WRITE_800_80C_POLL(_addr, _data_800) \
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PARAM_WRITE_D0_D4(0x0000080c, 0x00000100), \
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PARAM_WRITE_D0_D4(0x00000800, ((_data_800) << 16) | BIT(8) | (_addr)), \
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PARAM_WRITE(0xd0, 0x0000080c), \
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PARAM_POLL(0xd4, BIT(8), BIT(8))
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#define PARAM_RESTORE_800_80C_POLL(_index) \
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PARAM_WRITE_D0_D4(0x0000080c, 0x00000100), \
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PARAM_WRITE(0xd0, 0x00000800), \
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PARAM_RESTORE(0xd4, _index), \
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PARAM_WRITE(0xd0, 0x0000080c), \
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PARAM_POLL(0xd4, BIT(8), BIT(8))
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#define PARAM_WRITE_804_80C_POLL(_addr, _data_804) \
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PARAM_WRITE_D0_D4(0x0000080c, 0x00000100), \
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PARAM_WRITE_D0_D4(0x00000804, ((_data_804) << 16) | BIT(8) | (_addr)), \
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PARAM_WRITE(0xd0, 0x0000080c), \
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PARAM_POLL(0xd4, BIT(8), BIT(8))
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#define PARAM_WRITE_828_82C_POLL(_data_828) \
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PARAM_WRITE_D0_D4(0x0000082c, 0x0f000000), \
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PARAM_WRITE_D0_D4(0x00000828, _data_828), \
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PARAM_WRITE(0xd0, 0x0000082c), \
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PARAM_POLL(0xd4, _data_828, _data_828)
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#define PARAM_WRITE_PHY(_addr16, _data16) \
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PARAM_WRITE(0xf0, 1), \
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PARAM_WRITE_800_80C_POLL(0x16, (_addr16) & 0xff), \
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PARAM_WRITE_800_80C_POLL(0x17, ((_addr16) >> 8) & 0xff), \
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PARAM_WRITE_800_80C_POLL(0x18, (_data16) & 0xff), \
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PARAM_WRITE_800_80C_POLL(0x19, ((_data16) >> 8) & 0xff), \
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PARAM_WRITE_800_80C_POLL(0x1c, 0x01), \
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PARAM_WRITE_828_82C_POLL(0x0f000000), \
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PARAM_WRITE(0xf0, 0)
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#define PARAM_SET_PHY(_addr16, _data16) \
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PARAM_WRITE(0xf0, 1), \
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PARAM_WRITE_800_80C_POLL(0x16, (_addr16) & 0xff), \
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PARAM_WRITE_800_80C_POLL(0x17, ((_addr16) >> 8) & 0xff), \
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PARAM_WRITE_800_80C_POLL(0x1c, 0x01), \
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PARAM_WRITE_828_82C_POLL(0x0f000000), \
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PARAM_WRITE_804_80C_POLL(0x1a, 0), \
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PARAM_WRITE(0xd0, 0x00000808), \
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PARAM_SAVE(0xd4, 0xff, SET_PHY_INDEX_LO), \
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PARAM_WRITE_804_80C_POLL(0x1b, 0), \
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PARAM_WRITE(0xd0, 0x00000808), \
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PARAM_SAVE(0xd4, 0xff, SET_PHY_INDEX_HI), \
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PARAM_WRITE_828_82C_POLL(0x0f000000), \
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PARAM_WRITE(0xf0, 0), \
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PARAM_WRITE(0xf0, 1), \
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PARAM_WRITE_800_80C_POLL(0x16, (_addr16) & 0xff), \
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PARAM_WRITE_800_80C_POLL(0x17, ((_addr16) >> 8) & 0xff), \
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PARAM_SET(SET_PHY_INDEX_LO, ((_data16 & 0xff) << 16) | BIT(8) | 0x18), \
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PARAM_RESTORE_800_80C_POLL(SET_PHY_INDEX_LO), \
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PARAM_SET(SET_PHY_INDEX_HI, (((_data16 >> 8) & 0xff) << 16) | BIT(8) | 0x19), \
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PARAM_RESTORE_800_80C_POLL(SET_PHY_INDEX_HI), \
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PARAM_WRITE_800_80C_POLL(0x1c, 0x01), \
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PARAM_WRITE_828_82C_POLL(0x0f000000), \
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PARAM_WRITE(0xf0, 0)
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#define PARAM_INDIRECT_WRITE(_gpio, _addr, _data_800) \
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PARAM_WRITE(0xf0, _gpio), \
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PARAM_WRITE_800_80C_POLL(_addr, _data_800), \
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PARAM_WRITE_828_82C_POLL(0x0f000000), \
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PARAM_WRITE(0xf0, 0)
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#define PARAM_INDIRECT_POLL(_gpio, _addr, _expected, _mask) \
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PARAM_WRITE(0xf0, _gpio), \
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PARAM_WRITE_800_80C_POLL(_addr, 0), \
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PARAM_WRITE(0xd0, 0x00000808), \
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PARAM_POLL(0xd4, _expected, _mask), \
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PARAM_WRITE(0xf0, 0)
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struct ufs_renesas_init_param {
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enum ufs_renesas_init_param_mode mode;
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u32 reg;
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union {
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u32 expected;
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u32 delay_us;
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u32 set;
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u32 val;
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} u;
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u32 mask;
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u32 index;
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};
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/* This setting is for SERIES B */
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static const struct ufs_renesas_init_param ufs_param[] = {
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PARAM_WRITE(0xc0, 0x49425308),
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PARAM_WRITE_D0_D4(0x00000104, 0x00000002),
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PARAM_WAIT(1),
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PARAM_WRITE_D0_D4(0x00000828, 0x00000200),
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PARAM_WAIT(1),
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PARAM_WRITE_D0_D4(0x00000828, 0x00000000),
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PARAM_WRITE_D0_D4(0x00000104, 0x00000001),
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PARAM_WRITE_D0_D4(0x00000940, 0x00000001),
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PARAM_WAIT(1),
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PARAM_WRITE_D0_D4(0x00000940, 0x00000000),
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PARAM_WRITE(0xc0, 0x49425308),
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PARAM_WRITE(0xc0, 0x41584901),
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PARAM_WRITE_D0_D4(0x0000080c, 0x00000100),
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PARAM_WRITE_D0_D4(0x00000804, 0x00000000),
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PARAM_WRITE(0xd0, 0x0000080c),
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PARAM_POLL(0xd4, BIT(8), BIT(8)),
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PARAM_WRITE(REG_CONTROLLER_ENABLE, 0x00000001),
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PARAM_WRITE(0xd0, 0x00000804),
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PARAM_POLL(0xd4, BIT(8) | BIT(6) | BIT(0), BIT(8) | BIT(6) | BIT(0)),
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PARAM_WRITE(0xd0, 0x00000d00),
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PARAM_SAVE(0xd4, 0x0000ffff, TIMER_INDEX),
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PARAM_WRITE(0xd4, 0x00000000),
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PARAM_WRITE_D0_D4(0x0000082c, 0x0f000000),
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PARAM_WRITE_D0_D4(0x00000828, 0x08000000),
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PARAM_WRITE(0xd0, 0x0000082c),
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PARAM_POLL(0xd4, BIT(27), BIT(27)),
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PARAM_WRITE(0xd0, 0x00000d2c),
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PARAM_POLL(0xd4, BIT(0), BIT(0)),
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/* phy setup */
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PARAM_INDIRECT_WRITE(1, 0x01, 0x001f),
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PARAM_INDIRECT_WRITE(7, 0x5d, 0x0014),
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PARAM_INDIRECT_WRITE(7, 0x5e, 0x0014),
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PARAM_INDIRECT_WRITE(7, 0x0d, 0x0003),
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PARAM_INDIRECT_WRITE(7, 0x0e, 0x0007),
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PARAM_INDIRECT_WRITE(7, 0x5f, 0x0003),
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PARAM_INDIRECT_WRITE(7, 0x60, 0x0003),
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PARAM_INDIRECT_WRITE(7, 0x5b, 0x00a6),
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PARAM_INDIRECT_WRITE(7, 0x5c, 0x0003),
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PARAM_INDIRECT_POLL(7, 0x3c, 0, BIT(7)),
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PARAM_INDIRECT_POLL(7, 0x4c, 0, BIT(4)),
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PARAM_INDIRECT_WRITE(1, 0x32, 0x0080),
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PARAM_INDIRECT_WRITE(1, 0x1f, 0x0001),
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PARAM_INDIRECT_WRITE(0, 0x2c, 0x0001),
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PARAM_INDIRECT_WRITE(0, 0x32, 0x0087),
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PARAM_INDIRECT_WRITE(1, 0x4d, 0x0061),
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PARAM_INDIRECT_WRITE(4, 0x9b, 0x0009),
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PARAM_INDIRECT_WRITE(4, 0xa6, 0x0005),
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PARAM_INDIRECT_WRITE(4, 0xa5, 0x0058),
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PARAM_INDIRECT_WRITE(1, 0x39, 0x0027),
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PARAM_INDIRECT_WRITE(1, 0x47, 0x004c),
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PARAM_INDIRECT_WRITE(7, 0x0d, 0x0002),
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PARAM_INDIRECT_WRITE(7, 0x0e, 0x0007),
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PARAM_WRITE_PHY(0x0028, 0x0061),
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PARAM_WRITE_PHY(0x4014, 0x0061),
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PARAM_SET_PHY(0x401c, BIT(2)),
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PARAM_WRITE_PHY(0x4000, 0x0000),
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PARAM_WRITE_PHY(0x4001, 0x0000),
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PARAM_WRITE_PHY(0x10ae, 0x0001),
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PARAM_WRITE_PHY(0x10ad, 0x0000),
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PARAM_WRITE_PHY(0x10af, 0x0001),
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PARAM_WRITE_PHY(0x10b6, 0x0001),
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PARAM_WRITE_PHY(0x10ae, 0x0000),
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PARAM_WRITE_PHY(0x10ae, 0x0001),
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PARAM_WRITE_PHY(0x10ad, 0x0000),
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PARAM_WRITE_PHY(0x10af, 0x0002),
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PARAM_WRITE_PHY(0x10b6, 0x0001),
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PARAM_WRITE_PHY(0x10ae, 0x0000),
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PARAM_WRITE_PHY(0x10ae, 0x0001),
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PARAM_WRITE_PHY(0x10ad, 0x0080),
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PARAM_WRITE_PHY(0x10af, 0x0000),
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PARAM_WRITE_PHY(0x10b6, 0x0001),
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PARAM_WRITE_PHY(0x10ae, 0x0000),
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PARAM_WRITE_PHY(0x10ae, 0x0001),
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PARAM_WRITE_PHY(0x10ad, 0x0080),
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PARAM_WRITE_PHY(0x10af, 0x001a),
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PARAM_WRITE_PHY(0x10b6, 0x0001),
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PARAM_WRITE_PHY(0x10ae, 0x0000),
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PARAM_INDIRECT_WRITE(7, 0x70, 0x0016),
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PARAM_INDIRECT_WRITE(7, 0x71, 0x0016),
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PARAM_INDIRECT_WRITE(7, 0x72, 0x0014),
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PARAM_INDIRECT_WRITE(7, 0x73, 0x0014),
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PARAM_INDIRECT_WRITE(7, 0x74, 0x0000),
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PARAM_INDIRECT_WRITE(7, 0x75, 0x0000),
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PARAM_INDIRECT_WRITE(7, 0x76, 0x0010),
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PARAM_INDIRECT_WRITE(7, 0x77, 0x0010),
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PARAM_INDIRECT_WRITE(7, 0x78, 0x00ff),
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PARAM_INDIRECT_WRITE(7, 0x79, 0x0000),
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PARAM_INDIRECT_WRITE(7, 0x19, 0x0007),
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PARAM_INDIRECT_WRITE(7, 0x1a, 0x0007),
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PARAM_INDIRECT_WRITE(7, 0x24, 0x000c),
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PARAM_INDIRECT_WRITE(7, 0x25, 0x000c),
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PARAM_INDIRECT_WRITE(7, 0x62, 0x0000),
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PARAM_INDIRECT_WRITE(7, 0x63, 0x0000),
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PARAM_INDIRECT_WRITE(7, 0x5d, 0x0014),
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PARAM_INDIRECT_WRITE(7, 0x5e, 0x0017),
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PARAM_INDIRECT_WRITE(7, 0x5d, 0x0004),
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PARAM_INDIRECT_WRITE(7, 0x5e, 0x0017),
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PARAM_INDIRECT_POLL(7, 0x55, 0, BIT(6)),
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PARAM_INDIRECT_POLL(7, 0x41, 0, BIT(7)),
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/* end of phy setup */
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PARAM_WRITE(0xf0, 0),
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PARAM_WRITE(0xd0, 0x00000d00),
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PARAM_RESTORE(0xd4, TIMER_INDEX),
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};
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static void ufs_renesas_dbg_register_dump(struct ufs_hba *hba)
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{
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ufshcd_dump_regs(hba, 0xc0, 0x40, "regs: 0xc0 + ");
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}
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static void ufs_renesas_reg_control(struct ufs_hba *hba,
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const struct ufs_renesas_init_param *p)
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{
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static u32 save[MAX_INDEX];
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int ret;
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u32 val;
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WARN_ON(p->index >= MAX_INDEX);
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switch (p->mode) {
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case MODE_RESTORE:
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ufshcd_writel(hba, save[p->index], p->reg);
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break;
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case MODE_SET:
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save[p->index] |= p->u.set;
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break;
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case MODE_SAVE:
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save[p->index] = ufshcd_readl(hba, p->reg) & p->mask;
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break;
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case MODE_POLL:
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ret = readl_poll_timeout_atomic(hba->mmio_base + p->reg,
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val,
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(val & p->mask) == p->u.expected,
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10, 1000);
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if (ret)
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dev_err(hba->dev, "%s: poll failed %d (%08x, %08x, %08x)\n",
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__func__, ret, val, p->mask, p->u.expected);
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break;
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case MODE_WAIT:
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if (p->u.delay_us > 1000)
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mdelay(DIV_ROUND_UP(p->u.delay_us, 1000));
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else
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udelay(p->u.delay_us);
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break;
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case MODE_WRITE:
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ufshcd_writel(hba, p->u.val, p->reg);
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break;
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default:
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break;
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}
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}
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static void ufs_renesas_pre_init(struct ufs_hba *hba)
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{
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const struct ufs_renesas_init_param *p = ufs_param;
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(ufs_param); i++)
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ufs_renesas_reg_control(hba, &p[i]);
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}
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static int ufs_renesas_hce_enable_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status status)
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{
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struct ufs_renesas_priv *priv = ufshcd_get_variant(hba);
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if (priv->initialized)
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return 0;
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if (status == PRE_CHANGE)
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ufs_renesas_pre_init(hba);
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priv->initialized = true;
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return 0;
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}
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||||
|
||||
static int ufs_renesas_setup_clocks(struct ufs_hba *hba, bool on,
|
||||
enum ufs_notify_change_status status)
|
||||
{
|
||||
if (on && status == PRE_CHANGE)
|
||||
pm_runtime_get_sync(hba->dev);
|
||||
else if (!on && status == POST_CHANGE)
|
||||
pm_runtime_put(hba->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ufs_renesas_init(struct ufs_hba *hba)
|
||||
{
|
||||
struct ufs_renesas_priv *priv;
|
||||
|
||||
priv = devm_kmalloc(hba->dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
ufshcd_set_variant(hba, priv);
|
||||
|
||||
hba->quirks |= UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS | UFSHCD_QUIRK_HIBERN_FASTAUTO;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct ufs_hba_variant_ops ufs_renesas_vops = {
|
||||
.name = "renesas",
|
||||
.init = ufs_renesas_init,
|
||||
.setup_clocks = ufs_renesas_setup_clocks,
|
||||
.hce_enable_notify = ufs_renesas_hce_enable_notify,
|
||||
.dbg_register_dump = ufs_renesas_dbg_register_dump,
|
||||
};
|
||||
|
||||
static const struct of_device_id __maybe_unused ufs_renesas_of_match[] = {
|
||||
{ .compatible = "renesas,r8a779f0-ufs" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, ufs_renesas_of_match);
|
||||
|
||||
static int ufs_renesas_probe(struct platform_device *pdev)
|
||||
{
|
||||
return ufshcd_pltfrm_init(pdev, &ufs_renesas_vops);
|
||||
}
|
||||
|
||||
static int ufs_renesas_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct ufs_hba *hba = platform_get_drvdata(pdev);
|
||||
|
||||
ufshcd_remove(hba);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver ufs_renesas_platform = {
|
||||
.probe = ufs_renesas_probe,
|
||||
.remove = ufs_renesas_remove,
|
||||
.driver = {
|
||||
.name = "ufshcd-renesas",
|
||||
.of_match_table = of_match_ptr(ufs_renesas_of_match),
|
||||
},
|
||||
};
|
||||
module_platform_driver(ufs_renesas_platform);
|
||||
|
||||
MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
|
||||
MODULE_DESCRIPTION("Renesas UFS host controller driver");
|
||||
MODULE_LICENSE("Dual MIT/GPL");
|
||||
Loading…
Reference in a new issue