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- introduce Allwinner PPU driver
- limit iteration in sram debugfs -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQSPRixG1tysKC2PKM10Ba7+DO8kkwUCY9RTJgAKCRB0Ba7+DO8k kx95AP0X7OJAPv+c2E+LUkgR+GzOHWSefZm600tteEgcC3SBVQEAg3g/QyLk18SM LkZdm5++fSkxX0EwSrMthUq8P1CU5w4= =CS1P -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmPX3k0ACgkQmmx57+YA GNnL/Q//WrC02t6Kl+L4Pk9rWJS5pgdM2dUb3XAfR8/vp9PRW5yuPnxT41sv2dP4 uBMF1t6FKtJimabB6DFD8mZeiW3JiamEH/PSd0Qo11NX8pPmJhDYXYTUdy6fTHhB JMFK+piOkgVPiv55ROgXCEvTDd1wOedC3SumEMo2bZkpFRGcylYbb/k/MJbjktjA oC2tIGeDV7BxKjl7NxyLwfV7+TqswVd6OvacWKgUZuGxR1laHitDM6ggv9YvA1K4 w5CE5xaHoBXhtway0DdrAfURzhldn59Q6UdUvcHuYfjt6Di7RD431jJdQnlRTP9G WaUZYjIrTb2izyz5AWcDLI2O3Gzg8eBhoINLjSw7aaScQnPEB1g69M+nhQyOfh/w gC8M2ti7T7uX4HbAuhdOnfBtf6qaG6LluDlOClPTBmWcZvpKTzcqlx3ZNjMUfVGa z+Ft5ui8pdQmxtHUPt1xH6AFk5GMkgnSGTI5Kc302EntetPxG7UMgq3km4QfCBY6 6x/tF7GxgfYIbDGwr6qXpe5g8Oyuo7zqxKmChRiQjmCudKdG+rqdQfGYlvNdBtHq YJABQEb/+DDu+75tfURS0CY6eiMRr3NQUFgLExZv/hL2mN56j4IrALB39TRVwEON WKSFBq71G/BFWvNxIc2YsdR8+MechEZW2KmY1F2n6OXy+pJvo9I= =nXYr -----END PGP SIGNATURE----- Merge tag 'sunxi-drivers-for-6.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/drivers - introduce Allwinner PPU driver - limit iteration in sram debugfs * tag 'sunxi-drivers-for-6.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: soc: sunxi: Add Allwinner D1 PPU driver dt-bindings: power: Add Allwinner D1 PPU soc: sunxi: sram: Only iterate over SRAM children Link: https://lore.kernel.org/r/Y9RXXATRNqEv0GJT@jernej-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
d5d39b46f0
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@ -0,0 +1,54 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/power/allwinner,sun20i-d1-ppu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner SoCs PPU power domain controller
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maintainers:
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- Samuel Holland <samuel@sholland.org>
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description:
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D1 and related SoCs contain a power domain controller for the CPUs, GPU, and
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video-related hardware.
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properties:
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compatible:
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enum:
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- allwinner,sun20i-d1-ppu
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reg:
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maxItems: 1
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clocks:
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description: Bus Clock
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maxItems: 1
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resets:
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maxItems: 1
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'#power-domain-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- resets
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
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#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
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ppu: power-controller@7001000 {
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compatible = "allwinner,sun20i-d1-ppu";
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reg = <0x7001000 0x1000>;
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clocks = <&r_ccu CLK_BUS_R_PPU>;
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resets = <&r_ccu RST_BUS_R_PPU>;
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#power-domain-cells = <1>;
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};
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@ -19,3 +19,11 @@ config SUNXI_SRAM
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Say y here to enable the SRAM controller support. This
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device is responsible on mapping the SRAM in the sunXi SoCs
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whether to the CPU/DMA, or to the devices.
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config SUN20I_PPU
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bool "Allwinner D1 PPU power domain driver"
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depends on ARCH_SUNXI || COMPILE_TEST
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select PM_GENERIC_DOMAINS
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help
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Say y to enable the PPU power domain driver. This saves power
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when certain peripherals, such as the video engine, are idle.
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@ -1,3 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_SUNXI_MBUS) += sunxi_mbus.o
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obj-$(CONFIG_SUNXI_SRAM) += sunxi_sram.o
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obj-$(CONFIG_SUN20I_PPU) += sun20i-ppu.o
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207
drivers/soc/sunxi/sun20i-ppu.c
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207
drivers/soc/sunxi/sun20i-ppu.c
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@ -0,0 +1,207 @@
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// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/reset.h>
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#define PD_STATE_ON 1
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#define PD_STATE_OFF 2
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#define PD_RSTN_REG 0x00
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#define PD_CLK_GATE_REG 0x04
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#define PD_PWROFF_GATE_REG 0x08
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#define PD_PSW_ON_REG 0x0c
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#define PD_PSW_OFF_REG 0x10
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#define PD_PSW_DELAY_REG 0x14
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#define PD_OFF_DELAY_REG 0x18
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#define PD_ON_DELAY_REG 0x1c
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#define PD_COMMAND_REG 0x20
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#define PD_STATUS_REG 0x24
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#define PD_STATUS_COMPLETE BIT(1)
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#define PD_STATUS_BUSY BIT(3)
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#define PD_STATUS_STATE GENMASK(17, 16)
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#define PD_ACTIVE_CTRL_REG 0x2c
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#define PD_GATE_STATUS_REG 0x30
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#define PD_RSTN_STATUS BIT(0)
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#define PD_CLK_GATE_STATUS BIT(1)
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#define PD_PWROFF_GATE_STATUS BIT(2)
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#define PD_PSW_STATUS_REG 0x34
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#define PD_REGS_SIZE 0x80
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struct sun20i_ppu_desc {
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const char *const *names;
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unsigned int num_domains;
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};
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struct sun20i_ppu_pd {
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struct generic_pm_domain genpd;
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void __iomem *base;
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};
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#define to_sun20i_ppu_pd(_genpd) \
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container_of(_genpd, struct sun20i_ppu_pd, genpd)
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static bool sun20i_ppu_pd_is_on(const struct sun20i_ppu_pd *pd)
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{
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u32 status = readl(pd->base + PD_STATUS_REG);
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return FIELD_GET(PD_STATUS_STATE, status) == PD_STATE_ON;
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}
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static int sun20i_ppu_pd_set_power(const struct sun20i_ppu_pd *pd, bool power_on)
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{
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u32 state, status;
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int ret;
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if (sun20i_ppu_pd_is_on(pd) == power_on)
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return 0;
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/* Wait for the power controller to be idle. */
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ret = readl_poll_timeout(pd->base + PD_STATUS_REG, status,
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!(status & PD_STATUS_BUSY), 100, 1000);
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if (ret)
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return ret;
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state = power_on ? PD_STATE_ON : PD_STATE_OFF;
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writel(state, pd->base + PD_COMMAND_REG);
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/* Wait for the state transition to complete. */
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ret = readl_poll_timeout(pd->base + PD_STATUS_REG, status,
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FIELD_GET(PD_STATUS_STATE, status) == state &&
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(status & PD_STATUS_COMPLETE), 100, 1000);
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if (ret)
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return ret;
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/* Clear the completion flag. */
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writel(status, pd->base + PD_STATUS_REG);
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return 0;
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}
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static int sun20i_ppu_pd_power_on(struct generic_pm_domain *genpd)
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{
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const struct sun20i_ppu_pd *pd = to_sun20i_ppu_pd(genpd);
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return sun20i_ppu_pd_set_power(pd, true);
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}
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static int sun20i_ppu_pd_power_off(struct generic_pm_domain *genpd)
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{
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const struct sun20i_ppu_pd *pd = to_sun20i_ppu_pd(genpd);
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return sun20i_ppu_pd_set_power(pd, false);
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}
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static int sun20i_ppu_probe(struct platform_device *pdev)
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{
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const struct sun20i_ppu_desc *desc;
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struct device *dev = &pdev->dev;
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struct genpd_onecell_data *ppu;
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struct sun20i_ppu_pd *pds;
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struct reset_control *rst;
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void __iomem *base;
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struct clk *clk;
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int ret;
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desc = of_device_get_match_data(dev);
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if (!desc)
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return -EINVAL;
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pds = devm_kcalloc(dev, desc->num_domains, sizeof(*pds), GFP_KERNEL);
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if (!pds)
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return -ENOMEM;
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ppu = devm_kzalloc(dev, sizeof(*ppu), GFP_KERNEL);
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if (!ppu)
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return -ENOMEM;
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ppu->domains = devm_kcalloc(dev, desc->num_domains,
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sizeof(*ppu->domains), GFP_KERNEL);
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if (!ppu->domains)
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return -ENOMEM;
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ppu->num_domains = desc->num_domains;
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platform_set_drvdata(pdev, ppu);
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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clk = devm_clk_get_enabled(dev, NULL);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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rst = devm_reset_control_get_exclusive(dev, NULL);
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if (IS_ERR(rst))
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return PTR_ERR(rst);
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ret = reset_control_deassert(rst);
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if (ret)
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return ret;
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for (unsigned int i = 0; i < ppu->num_domains; ++i) {
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struct sun20i_ppu_pd *pd = &pds[i];
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pd->genpd.name = desc->names[i];
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pd->genpd.power_off = sun20i_ppu_pd_power_off;
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pd->genpd.power_on = sun20i_ppu_pd_power_on;
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pd->base = base + PD_REGS_SIZE * i;
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ret = pm_genpd_init(&pd->genpd, NULL, sun20i_ppu_pd_is_on(pd));
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if (ret) {
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dev_warn(dev, "Failed to add '%s' domain: %d\n",
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pd->genpd.name, ret);
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continue;
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}
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ppu->domains[i] = &pd->genpd;
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}
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ret = of_genpd_add_provider_onecell(dev->of_node, ppu);
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if (ret)
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dev_warn(dev, "Failed to add provider: %d\n", ret);
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return 0;
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}
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static const char *const sun20i_d1_ppu_pd_names[] = {
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"CPU",
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"VE",
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"DSP",
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};
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static const struct sun20i_ppu_desc sun20i_d1_ppu_desc = {
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.names = sun20i_d1_ppu_pd_names,
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.num_domains = ARRAY_SIZE(sun20i_d1_ppu_pd_names),
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};
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static const struct of_device_id sun20i_ppu_of_match[] = {
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{
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.compatible = "allwinner,sun20i-d1-ppu",
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.data = &sun20i_d1_ppu_desc,
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},
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{ }
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};
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MODULE_DEVICE_TABLE(of, sun20i_ppu_of_match);
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static struct platform_driver sun20i_ppu_driver = {
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.probe = sun20i_ppu_probe,
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.driver = {
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.name = "sun20i-ppu",
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.of_match_table = sun20i_ppu_of_match,
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/* Power domains cannot be removed while they are in use. */
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.suppress_bind_attrs = true,
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},
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};
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module_platform_driver(sun20i_ppu_driver);
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MODULE_AUTHOR("Samuel Holland <samuel@sholland.org>");
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MODULE_DESCRIPTION("Allwinner D1 PPU power domain driver");
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MODULE_LICENSE("GPL");
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@ -120,6 +120,9 @@ static int sunxi_sram_show(struct seq_file *s, void *data)
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seq_puts(s, "--------------------\n\n");
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for_each_child_of_node(sram_dev->of_node, sram_node) {
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if (!of_device_is_compatible(sram_node, "mmio-sram"))
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continue;
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sram_addr_p = of_get_address(sram_node, 0, NULL, NULL);
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seq_printf(s, "sram@%08x\n",
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10
include/dt-bindings/power/allwinner,sun20i-d1-ppu.h
Normal file
10
include/dt-bindings/power/allwinner,sun20i-d1-ppu.h
Normal file
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@ -0,0 +1,10 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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#ifndef _DT_BINDINGS_POWER_SUN20I_D1_PPU_H_
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#define _DT_BINDINGS_POWER_SUN20I_D1_PPU_H_
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#define PD_CPU 0
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#define PD_VE 1
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#define PD_DSP 2
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#endif /* _DT_BINDINGS_POWER_SUN20I_D1_PPU_H_ */
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