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sh: multiple vectors per irq - sh7201.
Follow the conversions as per the other subtypes. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
e45efe68d1
commit
d55eedd57d
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@ -2,6 +2,7 @@
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* SH7201 setup
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*
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* Copyright (C) 2008 Peter Griffin pgriffin@mpc-data.co.uk
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* Copyright (C) 2009 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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@ -18,57 +19,32 @@ enum {
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/* interrupt sources */
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
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PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
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ADC_ADI,
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MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
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MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F,
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MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
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MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
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MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
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MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
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MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W,
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RTC_ARM, RTC_PRD, RTC_CUP,
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WDT,
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IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, IIC30_TEI,
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IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, IIC31_TEI,
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IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, IIC32_TEI,
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MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU,
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MTU23_ABCD, MTU24_ABCD, MTU25_UVW, MTU2_TCI3V, MTU2_TCI4V,
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RTC, WDT,
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IIC30, IIC31, IIC32,
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DMAC0_DMINT0, DMAC1_DMINT1,
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DMAC2_DMINT2, DMAC3_DMINT3,
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SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
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SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
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SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
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SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
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SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
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SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
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SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
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SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
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SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
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DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6,
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DMAC7_DMINT7,
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RCAN0_ERS, RCAN0_OVR,
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RCAN0_SLE,
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RCAN0_RM0, RCAN0_RM1,
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RCAN1_ERS, RCAN1_OVR,
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RCAN1_SLE,
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RCAN1_RM0, RCAN1_RM1,
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RCAN0, RCAN1,
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SSI0_SSII, SSI1_SSII,
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TMR0_CMIA0, TMR0_CMIB0, TMR0_OVI0,
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TMR1_CMIA1, TMR1_CMIB1, TMR1_OVI1,
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TMR0, TMR1,
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/* interrupt groups */
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IRQ, PINT, ADC,
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MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU,
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MTU23_ABCD, MTU24_ABCD, MTU25_UVW,
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RTC, IIC30, IIC31, IIC32,
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SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
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RCAN0, RCAN1, TMR0, TMR1
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PINT,
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};
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static struct intc_vect vectors[] __initdata = {
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@ -76,6 +52,7 @@ static struct intc_vect vectors[] __initdata = {
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INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
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INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
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INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
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INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
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INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
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INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
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@ -83,123 +60,92 @@ static struct intc_vect vectors[] __initdata = {
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INTC_IRQ(ADC_ADI, 92),
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INTC_IRQ(MTU2_TGI0A, 108), INTC_IRQ(MTU2_TGI0B, 109),
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INTC_IRQ(MTU2_TGI0C, 110), INTC_IRQ(MTU2_TGI0D, 111),
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INTC_IRQ(MTU2_TCI0V, 112),
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INTC_IRQ(MTU2_TGI0E, 113), INTC_IRQ(MTU2_TGI0F, 114),
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INTC_IRQ(MTU20_ABCD, 108), INTC_IRQ(MTU20_ABCD, 109),
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INTC_IRQ(MTU20_ABCD, 110), INTC_IRQ(MTU20_ABCD, 111),
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INTC_IRQ(MTU2_TGI1A, 116), INTC_IRQ(MTU2_TGI1B, 117),
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INTC_IRQ(MTU2_TCI1V, 120), INTC_IRQ(MTU2_TCI1U, 121),
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INTC_IRQ(MTU20_VEF, 112), INTC_IRQ(MTU20_VEF, 113),
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INTC_IRQ(MTU20_VEF, 114),
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INTC_IRQ(MTU2_TGI2A, 124), INTC_IRQ(MTU2_TGI2B, 125),
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INTC_IRQ(MTU2_TCI2V, 128), INTC_IRQ(MTU2_TCI2U, 129),
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INTC_IRQ(MTU21_AB, 116), INTC_IRQ(MTU21_AB, 117),
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INTC_IRQ(MTU21_VU, 120), INTC_IRQ(MTU21_VU, 121),
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INTC_IRQ(MTU22_AB, 124), INTC_IRQ(MTU22_AB, 125),
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INTC_IRQ(MTU22_VU, 128), INTC_IRQ(MTU22_VU, 129),
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INTC_IRQ(MTU23_ABCD, 132), INTC_IRQ(MTU23_ABCD, 133),
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INTC_IRQ(MTU23_ABCD, 134), INTC_IRQ(MTU23_ABCD, 135),
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INTC_IRQ(MTU2_TGI3A, 132), INTC_IRQ(MTU2_TGI3B, 133),
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INTC_IRQ(MTU2_TGI3C, 134), INTC_IRQ(MTU2_TGI3D, 135),
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INTC_IRQ(MTU2_TCI3V, 136),
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INTC_IRQ(MTU2_TGI4A, 140), INTC_IRQ(MTU2_TGI4B, 141),
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INTC_IRQ(MTU2_TGI4C, 142), INTC_IRQ(MTU2_TGI4D, 143),
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INTC_IRQ(MTU24_ABCD, 140), INTC_IRQ(MTU24_ABCD, 141),
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INTC_IRQ(MTU24_ABCD, 142), INTC_IRQ(MTU24_ABCD, 143),
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INTC_IRQ(MTU2_TCI4V, 144),
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INTC_IRQ(MTU2_TGI5U, 148), INTC_IRQ(MTU2_TGI5V, 149),
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INTC_IRQ(MTU2_TGI5W, 150),
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INTC_IRQ(MTU25_UVW, 148), INTC_IRQ(MTU25_UVW, 149),
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INTC_IRQ(MTU25_UVW, 150),
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INTC_IRQ(RTC_ARM, 152), INTC_IRQ(RTC_PRD, 153),
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INTC_IRQ(RTC_CUP, 154), INTC_IRQ(WDT, 156),
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INTC_IRQ(RTC, 152), INTC_IRQ(RTC, 153),
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INTC_IRQ(RTC, 154),
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INTC_IRQ(IIC30_STPI, 157), INTC_IRQ(IIC30_NAKI, 158),
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INTC_IRQ(IIC30_RXI, 159), INTC_IRQ(IIC30_TXI, 160),
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INTC_IRQ(IIC30_TEI, 161),
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INTC_IRQ(WDT, 156),
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INTC_IRQ(IIC31_STPI, 164), INTC_IRQ(IIC31_NAKI, 165),
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INTC_IRQ(IIC31_RXI, 166), INTC_IRQ(IIC31_TXI, 167),
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INTC_IRQ(IIC31_TEI, 168),
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INTC_IRQ(IIC30, 157), INTC_IRQ(IIC30, 158),
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INTC_IRQ(IIC30, 159), INTC_IRQ(IIC30, 160),
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INTC_IRQ(IIC30, 161),
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INTC_IRQ(IIC32_STPI, 170), INTC_IRQ(IIC32_NAKI, 171),
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INTC_IRQ(IIC32_RXI, 172), INTC_IRQ(IIC32_TXI, 173),
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INTC_IRQ(IIC32_TEI, 174),
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INTC_IRQ(IIC31, 164), INTC_IRQ(IIC31, 165),
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INTC_IRQ(IIC31, 166), INTC_IRQ(IIC31, 167),
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INTC_IRQ(IIC31, 168),
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INTC_IRQ(IIC32, 170), INTC_IRQ(IIC32, 171),
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INTC_IRQ(IIC32, 172), INTC_IRQ(IIC32, 173),
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INTC_IRQ(IIC32, 174),
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INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177),
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INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179),
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INTC_IRQ(SCIF0_BRI, 180), INTC_IRQ(SCIF0_ERI, 181),
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INTC_IRQ(SCIF0_RXI, 182), INTC_IRQ(SCIF0_TXI, 183),
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INTC_IRQ(SCIF1_BRI, 184), INTC_IRQ(SCIF1_ERI, 185),
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INTC_IRQ(SCIF1_RXI, 186), INTC_IRQ(SCIF1_TXI, 187),
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INTC_IRQ(SCIF2_BRI, 188), INTC_IRQ(SCIF2_ERI, 189),
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INTC_IRQ(SCIF2_RXI, 190), INTC_IRQ(SCIF2_TXI, 191),
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INTC_IRQ(SCIF3_BRI, 192), INTC_IRQ(SCIF3_ERI, 193),
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INTC_IRQ(SCIF3_RXI, 194), INTC_IRQ(SCIF3_TXI, 195),
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INTC_IRQ(SCIF4_BRI, 196), INTC_IRQ(SCIF4_ERI, 197),
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INTC_IRQ(SCIF4_RXI, 198), INTC_IRQ(SCIF4_TXI, 199),
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INTC_IRQ(SCIF5_BRI, 200), INTC_IRQ(SCIF5_ERI, 201),
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INTC_IRQ(SCIF5_RXI, 202), INTC_IRQ(SCIF5_TXI, 203),
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INTC_IRQ(SCIF6_BRI, 204), INTC_IRQ(SCIF6_ERI, 205),
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INTC_IRQ(SCIF6_RXI, 206), INTC_IRQ(SCIF6_TXI, 207),
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INTC_IRQ(SCIF7_BRI, 208), INTC_IRQ(SCIF7_ERI, 209),
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INTC_IRQ(SCIF7_RXI, 210), INTC_IRQ(SCIF7_TXI, 211),
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INTC_IRQ(SCIF0, 180), INTC_IRQ(SCIF0, 181),
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INTC_IRQ(SCIF0, 182), INTC_IRQ(SCIF0, 183),
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INTC_IRQ(SCIF1, 184), INTC_IRQ(SCIF1, 185),
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INTC_IRQ(SCIF1, 186), INTC_IRQ(SCIF1, 187),
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INTC_IRQ(SCIF2, 188), INTC_IRQ(SCIF2, 189),
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INTC_IRQ(SCIF2, 190), INTC_IRQ(SCIF2, 191),
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INTC_IRQ(SCIF3, 192), INTC_IRQ(SCIF3, 193),
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INTC_IRQ(SCIF3, 194), INTC_IRQ(SCIF3, 195),
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INTC_IRQ(SCIF4, 196), INTC_IRQ(SCIF4, 197),
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INTC_IRQ(SCIF4, 198), INTC_IRQ(SCIF4, 199),
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INTC_IRQ(SCIF5, 200), INTC_IRQ(SCIF5, 201),
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INTC_IRQ(SCIF5, 202), INTC_IRQ(SCIF5, 203),
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INTC_IRQ(SCIF6, 204), INTC_IRQ(SCIF6, 205),
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INTC_IRQ(SCIF6, 206), INTC_IRQ(SCIF6, 207),
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INTC_IRQ(SCIF7, 208), INTC_IRQ(SCIF7, 209),
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INTC_IRQ(SCIF7, 210), INTC_IRQ(SCIF7, 211),
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INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216),
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INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218),
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INTC_IRQ(DMAC7_DMINT7, 219),
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INTC_IRQ(RCAN0_ERS, 228), INTC_IRQ(RCAN0_OVR, 229),
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INTC_IRQ(RCAN0_SLE, 230),
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INTC_IRQ(RCAN0_RM0, 231), INTC_IRQ(RCAN0_RM1, 232),
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INTC_IRQ(RCAN0, 228), INTC_IRQ(RCAN0, 229),
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INTC_IRQ(RCAN0, 230),
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INTC_IRQ(RCAN0, 231), INTC_IRQ(RCAN0, 232),
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INTC_IRQ(RCAN1_ERS, 234), INTC_IRQ(RCAN1_OVR, 235),
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INTC_IRQ(RCAN1_SLE, 236),
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INTC_IRQ(RCAN1_RM0, 237), INTC_IRQ(RCAN1_RM1, 238),
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INTC_IRQ(RCAN1, 234), INTC_IRQ(RCAN1, 235),
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INTC_IRQ(RCAN1, 236),
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INTC_IRQ(RCAN1, 237), INTC_IRQ(RCAN1, 238),
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INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245),
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INTC_IRQ(TMR0_CMIA0, 246), INTC_IRQ(TMR0_CMIB0, 247),
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INTC_IRQ(TMR0_OVI0, 248),
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INTC_IRQ(TMR1_CMIA1, 252), INTC_IRQ(TMR1_CMIB1, 253),
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INTC_IRQ(TMR1_OVI1, 254),
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INTC_IRQ(TMR0, 246), INTC_IRQ(TMR0, 247),
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INTC_IRQ(TMR0, 248),
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INTC_IRQ(TMR1, 252), INTC_IRQ(TMR1, 253),
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INTC_IRQ(TMR1, 254),
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};
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
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PINT4, PINT5, PINT6, PINT7),
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INTC_GROUP(MTU20_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D),
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INTC_GROUP(MTU20_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F),
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INTC_GROUP(MTU21_AB, MTU2_TGI1A, MTU2_TGI1B),
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INTC_GROUP(MTU21_VU, MTU2_TCI1V, MTU2_TCI1U),
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INTC_GROUP(MTU22_AB, MTU2_TGI2A, MTU2_TGI2B),
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INTC_GROUP(MTU22_VU, MTU2_TCI2V, MTU2_TCI2U),
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INTC_GROUP(MTU23_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D),
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INTC_GROUP(MTU24_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
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INTC_GROUP(MTU25_UVW, MTU2_TGI5U, MTU2_TGI5V, MTU2_TGI5W),
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INTC_GROUP(RTC, RTC_ARM, RTC_PRD, RTC_CUP ),
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INTC_GROUP(IIC30, IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI,
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IIC30_TEI),
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INTC_GROUP(IIC31, IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI,
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IIC31_TEI),
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INTC_GROUP(IIC32, IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI,
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IIC32_TEI),
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INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
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INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
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INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
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INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
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INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
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INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
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INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
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INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
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INTC_GROUP(RCAN0, RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1,
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RCAN0_SLE),
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INTC_GROUP(RCAN1, RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1,
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RCAN1_SLE),
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INTC_GROUP(TMR0, TMR0_CMIA0, TMR0_CMIB0, TMR0_OVI0),
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INTC_GROUP(TMR1, TMR1_CMIA1, TMR1_CMIB1, TMR1_OVI1),
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};
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static struct intc_prio_reg prio_registers[] __initdata = {
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@ -212,7 +158,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } },
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{ 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } },
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{ 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0 , SCIF1 } },
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{ 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0, SCIF1 } },
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{ 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } },
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{ 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4 } },
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{ 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } },
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@ -234,42 +180,42 @@ static struct plat_sci_port sci_platform_data[] = {
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.mapbase = 0xfffe8000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 181, 182, 183, 180}
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.irqs = { 180, 180, 180, 180 }
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}, {
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.mapbase = 0xfffe8800,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 185, 186, 187, 184}
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||||
.irqs = { 184, 184, 184, 184 }
|
||||
}, {
|
||||
.mapbase = 0xfffe9000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 189, 186, 187, 188}
|
||||
.irqs = { 188, 188, 188, 188 }
|
||||
}, {
|
||||
.mapbase = 0xfffe9800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 193, 194, 195, 192}
|
||||
.irqs = { 192, 192, 192, 192 }
|
||||
}, {
|
||||
.mapbase = 0xfffea000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 196, 198, 199, 196}
|
||||
.irqs = { 196, 196, 196, 196 }
|
||||
}, {
|
||||
.mapbase = 0xfffea800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 201, 202, 203, 200}
|
||||
.irqs = { 200, 200, 200, 200 }
|
||||
}, {
|
||||
.mapbase = 0xfffeb000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 205, 206, 207, 204}
|
||||
.irqs = { 204, 204, 204, 204 }
|
||||
}, {
|
||||
.mapbase = 0xfffeb800,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 209, 210, 211, 208}
|
||||
.irqs = { 208, 208, 208, 208 }
|
||||
}, {
|
||||
.flags = 0,
|
||||
}
|
||||
|
|
@ -290,17 +236,7 @@ static struct resource rtc_resources[] = {
|
|||
.flags = IORESOURCE_IO,
|
||||
},
|
||||
[1] = {
|
||||
/* Period IRQ */
|
||||
.start = 153,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
/* Carry IRQ */
|
||||
.start = 154,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[3] = {
|
||||
/* Alarm IRQ */
|
||||
/* Shared Period/Carry/Alarm IRQ */
|
||||
.start = 152,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
|
|
|
|||
Loading…
Reference in a new issue