i.MX clock fixes for 5.5:

- Add missing lock to divider in the composite driver for exclusive
    register access.
  - Add missing sentinel for ulp_div_table in clk-imx7ulp driver.
  - Fix clk_pll14xx_wait_lock() function which calls into
    readl_poll_timeout() with incorrect parameter.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJd8jdEAAoJEFBXWFqHsHzOeJgH/0b6QemDjFC2Y1x1UGSj0BXV
 foprgLINmf/UZfvXXK/4Vzqsxjtp75cIyRdUrCOTw8+wDbCYLHQbvmSGPKC5fMEM
 +IsKP6BflZvbop6HEkqNXVxanH8DD/4b/5mdpCGcyehBcRgMT12NLg0tHzFse5XE
 IP0AFShc/CL75RYEUgbM8ZW7aMF7Ett+Mh14XYVmFj0A5MCENSvZ82neblpbZuIm
 NPh6l/X2NIdmJ5ushcZ0IbpcBiccA+Wq8HezTF60ExnyIQGQkqdSd+BRVJABTkrz
 DFKk/vzI0VInGGx+h2tX0HyA4zJZlbnEfnTi5mtFwVtnoAZChA92hln1hBh9u1U=
 =PH1+
 -----END PGP SIGNATURE-----

Merge tag 'imx-clk-fixes-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-fixes

Pull i.MX clk fixes from Shawn Guo:

 - Add missing lock to divider in the composite driver for exclusive
   register access
 - Add missing sentinel for ulp_div_table in clk-imx7ulp driver
 - Fix clk_pll14xx_wait_lock() function which calls into
   readl_poll_timeout() with incorrect parameter

* tag 'imx-clk-fixes-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  clk: imx: pll14xx: fix clk_pll14xx_wait_lock
  clk: imx: clk-imx7ulp: Add missing sentinel of ulp_div_table
  clk: imx: clk-composite-8m: add lock to gate/mux
This commit is contained in:
Stephen Boyd 2019-12-12 19:00:01 -08:00
commit d3ab06f432
3 changed files with 4 additions and 1 deletions

View file

@ -142,6 +142,7 @@ struct clk *imx8m_clk_composite_flags(const char *name,
mux->reg = reg;
mux->shift = PCG_PCS_SHIFT;
mux->mask = PCG_PCS_MASK;
mux->lock = &imx_ccm_lock;
div = kzalloc(sizeof(*div), GFP_KERNEL);
if (!div)
@ -161,6 +162,7 @@ struct clk *imx8m_clk_composite_flags(const char *name,
gate_hw = &gate->hw;
gate->reg = reg;
gate->bit_idx = PCG_CGC_SHIFT;
gate->lock = &imx_ccm_lock;
hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
mux_hw, &clk_mux_ops, div_hw,

View file

@ -40,6 +40,7 @@ static const struct clk_div_table ulp_div_table[] = {
{ .val = 5, .div = 16, },
{ .val = 6, .div = 32, },
{ .val = 7, .div = 64, },
{ /* sentinel */ },
};
static const int pcc2_uart_clk_ids[] __initconst = {

View file

@ -159,7 +159,7 @@ static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
{
u32 val;
return readl_poll_timeout(pll->base, val, val & LOCK_TIMEOUT_US, 0,
return readl_poll_timeout(pll->base, val, val & LOCK_STATUS, 0,
LOCK_TIMEOUT_US);
}