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https://github.com/torvalds/linux
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drm/amdkfd: display debug capabilities
Expose debug capabilities in the KFD topology node's HSA capabilities and debug properties flags. Ensure correct capabilities are exposed based on firmware support. Flag definitions can be referenced in uapi/linux/kfd_sysfs.h. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jonathan Kim
Alex Deucher
parent
4f98cf2baf
commit
d230f1bfe7
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@ -535,6 +535,8 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr,
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dev->gpu->kfd->mec_fw_version);
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sysfs_show_32bit_prop(buffer, offs, "capability",
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dev->node_props.capability);
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sysfs_show_64bit_prop(buffer, offs, "debug_prop",
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dev->node_props.debug_prop);
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sysfs_show_32bit_prop(buffer, offs, "sdma_fw_version",
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dev->gpu->kfd->sdma_fw_version);
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sysfs_show_64bit_prop(buffer, offs, "unique_id",
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@ -1857,6 +1859,97 @@ static int kfd_topology_add_device_locked(struct kfd_node *gpu, uint32_t gpu_id,
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return res;
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}
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static void kfd_topology_set_dbg_firmware_support(struct kfd_topology_device *dev)
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{
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bool firmware_supported = true;
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if (KFD_GC_VERSION(dev->gpu) >= IP_VERSION(11, 0, 0) &&
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KFD_GC_VERSION(dev->gpu) < IP_VERSION(12, 0, 0)) {
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firmware_supported =
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(dev->gpu->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 9;
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goto out;
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}
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/*
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* Note: Any unlisted devices here are assumed to support exception handling.
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* Add additional checks here as needed.
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*/
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switch (KFD_GC_VERSION(dev->gpu)) {
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case IP_VERSION(9, 0, 1):
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firmware_supported = dev->gpu->kfd->mec_fw_version >= 459 + 32768;
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break;
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case IP_VERSION(9, 1, 0):
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case IP_VERSION(9, 2, 1):
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case IP_VERSION(9, 2, 2):
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case IP_VERSION(9, 3, 0):
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case IP_VERSION(9, 4, 0):
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firmware_supported = dev->gpu->kfd->mec_fw_version >= 459;
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break;
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case IP_VERSION(9, 4, 1):
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firmware_supported = dev->gpu->kfd->mec_fw_version >= 60;
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break;
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case IP_VERSION(9, 4, 2):
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firmware_supported = dev->gpu->kfd->mec_fw_version >= 51;
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break;
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case IP_VERSION(10, 1, 10):
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case IP_VERSION(10, 1, 2):
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case IP_VERSION(10, 1, 1):
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firmware_supported = dev->gpu->kfd->mec_fw_version >= 144;
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break;
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case IP_VERSION(10, 3, 0):
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case IP_VERSION(10, 3, 2):
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 4):
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case IP_VERSION(10, 3, 5):
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firmware_supported = dev->gpu->kfd->mec_fw_version >= 89;
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break;
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case IP_VERSION(10, 1, 3):
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case IP_VERSION(10, 3, 3):
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firmware_supported = false;
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break;
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default:
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break;
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}
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out:
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if (firmware_supported)
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dev->node_props.capability |= HSA_CAP_TRAP_DEBUG_FIRMWARE_SUPPORTED;
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}
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static void kfd_topology_set_capabilities(struct kfd_topology_device *dev)
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{
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dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
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HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
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HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
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dev->node_props.capability |= HSA_CAP_TRAP_DEBUG_SUPPORT |
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HSA_CAP_TRAP_DEBUG_WAVE_LAUNCH_TRAP_OVERRIDE_SUPPORTED |
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HSA_CAP_TRAP_DEBUG_WAVE_LAUNCH_MODE_SUPPORTED;
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if (KFD_GC_VERSION(dev->gpu) < IP_VERSION(10, 0, 0)) {
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dev->node_props.debug_prop |= HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX9 |
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HSA_DBG_WATCH_ADDR_MASK_HI_BIT;
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if (KFD_GC_VERSION(dev->gpu) < IP_VERSION(9, 4, 2))
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dev->node_props.debug_prop |=
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HSA_DBG_DISPATCH_INFO_ALWAYS_VALID;
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else
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dev->node_props.capability |=
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HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED;
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} else {
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dev->node_props.debug_prop |= HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX10 |
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HSA_DBG_WATCH_ADDR_MASK_HI_BIT;
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if (KFD_GC_VERSION(dev->gpu) < IP_VERSION(11, 0, 0))
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dev->node_props.debug_prop |= HSA_DBG_DISPATCH_INFO_ALWAYS_VALID;
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else
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dev->node_props.capability |=
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HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED;
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}
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kfd_topology_set_dbg_firmware_support(dev);
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}
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int kfd_topology_add_device(struct kfd_node *gpu)
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{
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uint32_t gpu_id;
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@ -1967,13 +2060,11 @@ int kfd_topology_add_device(struct kfd_node *gpu)
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HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
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break;
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default:
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if (KFD_GC_VERSION(dev->gpu) >= IP_VERSION(9, 0, 1))
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dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
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HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
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HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
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else
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if (KFD_GC_VERSION(dev->gpu) < IP_VERSION(9, 0, 1))
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WARN(1, "Unexpected ASIC family %u",
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dev->gpu->adev->asic_type);
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else
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kfd_topology_set_capabilities(dev);
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}
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/*
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@ -31,6 +31,11 @@
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#define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 32
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#define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX9 6
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#define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX10 7
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#define HSA_DBG_WATCH_ADDR_MASK_HI_BIT \
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(29 << HSA_DBG_WATCH_ADDR_MASK_HI_BIT_SHIFT)
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struct kfd_node_properties {
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uint64_t hive_id;
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uint32_t cpu_cores_count;
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@ -42,6 +47,7 @@ struct kfd_node_properties {
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uint32_t cpu_core_id_base;
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uint32_t simd_id_base;
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uint32_t capability;
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uint64_t debug_prop;
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uint32_t max_waves_per_simd;
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uint32_t lds_size_in_kb;
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uint32_t gds_size_in_kb;
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@ -43,6 +43,11 @@
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#define HSA_CAP_DOORBELL_TYPE_2_0 0x2
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#define HSA_CAP_AQL_QUEUE_DOUBLE_MAP 0x00004000
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#define HSA_CAP_TRAP_DEBUG_SUPPORT 0x00008000
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#define HSA_CAP_TRAP_DEBUG_WAVE_LAUNCH_TRAP_OVERRIDE_SUPPORTED 0x00010000
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#define HSA_CAP_TRAP_DEBUG_WAVE_LAUNCH_MODE_SUPPORTED 0x00020000
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#define HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED 0x00040000
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/* Old buggy user mode depends on this being 0 */
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#define HSA_CAP_RESERVED_WAS_SRAM_EDCSUPPORTED 0x00080000
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@ -53,8 +58,18 @@
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#define HSA_CAP_SRAM_EDCSUPPORTED 0x04000000
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#define HSA_CAP_SVMAPI_SUPPORTED 0x08000000
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#define HSA_CAP_FLAGS_COHERENTHOSTACCESS 0x10000000
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#define HSA_CAP_TRAP_DEBUG_FIRMWARE_SUPPORTED 0x20000000
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#define HSA_CAP_RESERVED 0xe00f8000
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/* debug_prop bits in node properties */
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#define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_MASK 0x0000000f
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#define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_SHIFT 0
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#define HSA_DBG_WATCH_ADDR_MASK_HI_BIT_MASK 0x000003f0
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#define HSA_DBG_WATCH_ADDR_MASK_HI_BIT_SHIFT 4
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#define HSA_DBG_DISPATCH_INFO_ALWAYS_VALID 0x00000400
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#define HSA_DBG_WATCHPOINTS_EXCLUSIVE 0x00000800
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#define HSA_DBG_RESERVED 0xfffffffffffff000ull
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/* Heap types in memory properties */
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#define HSA_MEM_HEAP_TYPE_SYSTEM 0
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#define HSA_MEM_HEAP_TYPE_FB_PUBLIC 1
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