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MIPS: Octeon: Add PCIe2 support in arch_setup_msi_irq()
In arch_setup_msi_irq(), there is no case for PCIe2. So board which have PCIe2 functionality fails to boot with "Kernel panic - not syncing: arch_setup_msi_irq: Invalid octeon_dma_bar_type" message. This patch solve this problem. Signed-off-by: Eunbong Song <eunb.song@samsung.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/6747/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -15,6 +15,7 @@
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#include <asm/octeon/cvmx-npi-defs.h>
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#include <asm/octeon/cvmx-pci-defs.h>
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#include <asm/octeon/cvmx-npei-defs.h>
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#include <asm/octeon/cvmx-sli-defs.h>
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#include <asm/octeon/cvmx-pexp-defs.h>
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#include <asm/octeon/pci-octeon.h>
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@ -162,6 +163,11 @@ int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
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msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff;
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msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;
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break;
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case OCTEON_DMA_BAR_TYPE_PCIE2:
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/* When using PCIe2, Bar 0 is based at 0 */
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msg.address_lo = (0 + CVMX_SLI_PCIE_MSI_RCV) & 0xffffffff;
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msg.address_hi = (0 + CVMX_SLI_PCIE_MSI_RCV) >> 32;
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break;
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default:
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panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type");
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}
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