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Docs: dt: document ARM SMMU generic binding usage

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Document how the generic "iommus" binding should be used to describe ARM
SMMU stream IDs instead of the old "mmu-masters" binding.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Robin Murphy 2016-09-12 17:13:56 +01:00 committed by Will Deacon
parent adfec2e709
commit d0acbb750a
1 changed files with 48 additions and 15 deletions
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63
Documentation/devicetree/bindings/iommu/arm,smmu.txt
View file

@ -35,12 +35,16 @@ conditions.
interrupt per context bank. In the case of a single, interrupt per context bank. In the case of a single,
combined interrupt, it must be listed multiple times. combined interrupt, it must be listed multiple times.
- mmu-masters : A list of phandles to device nodes representing bus - #iommu-cells : See Documentation/devicetree/bindings/iommu/iommu.txt
masters for which the SMMU can provide a translation for details. With a value of 1, each "iommus" entry
and their corresponding StreamIDs (see example below). represents a distinct stream ID emitted by that device
Each device node linked from this list must have a into the relevant SMMU.
"#stream-id-cells" property, indicating the number of
StreamIDs associated with it. SMMUs with stream matching support and complex masters
may use a value of 2, where the second cell represents
an SMR mask to combine with the ID in the first cell.
Care must be taken to ensure the set of matched IDs
does not result in conflicts.
** System MMU optional properties: ** System MMU optional properties:
@ -56,9 +60,20 @@ conditions.
aliases of secure registers have to be used during aliases of secure registers have to be used during
SMMU configuration. SMMU configuration.
Example: ** Deprecated properties:
smmu { - mmu-masters (deprecated in favour of the generic "iommus" binding) :
A list of phandles to device nodes representing bus
masters for which the SMMU can provide a translation
and their corresponding Stream IDs. Each device node
linked from this list must have a "#stream-id-cells"
property, indicating the number of Stream ID
arguments associated with its phandle.
** Examples:
/* SMMU with stream matching or stream indexing */
smmu1: iommu {
compatible = "arm,smmu-v1"; compatible = "arm,smmu-v1";
reg = <0xba5e0000 0x10000>; reg = <0xba5e0000 0x10000>;
#global-interrupts = <2>; #global-interrupts = <2>;
@ -68,11 +83,29 @@ Example:
<0 35 4>, <0 35 4>,
<0 36 4>, <0 36 4>,
<0 37 4>; <0 37 4>;
#iommu-cells = <1>;
/* };
* Two DMA controllers, the first with two StreamIDs (0xd01d
* and 0xd01e) and the second with only one (0xd11c). /* device with two stream IDs, 0 and 7 */
*/ master1 {
mmu-masters = <&dma0 0xd01d 0xd01e>, iommus = <&smmu1 0>,
<&dma1 0xd11c>; <&smmu1 7>;
};
/* SMMU with stream matching */
smmu2: iommu {
...
#iommu-cells = <2>;
};
/* device with stream IDs 0 and 7 */
master2 {
iommus = <&smmu2 0 0>,
<&smmu2 7 0>;
};
/* device with stream IDs 1, 17, 33 and 49 */
master3 {
iommus = <&smmu2 1 0x30>;
}; };