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pinctrl: samsung: Add Exynos850 SoC specific data
Add Samsung Exynos850 SoC specific data to enable pinctrl support for all platforms based on Exynos850. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20210811114827.27322-3-semen.protsenko@linaro.org [krzysztof: lower-case the hex-numbers] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
This commit is contained in:
Sam Protsenko
Krzysztof Kozlowski
parent
71b833b329
commit
cdd3d945dc
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@ -40,6 +40,24 @@ static const struct samsung_pin_bank_type exynos5433_bank_type_alive = {
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.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
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};
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/*
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* Bank type for non-alive type. Bit fields:
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* CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4
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*/
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static const struct samsung_pin_bank_type exynos850_bank_type_off = {
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.fld_width = { 4, 1, 4, 4, 2, 4, },
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.reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
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};
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/*
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* Bank type for alive type. Bit fields:
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* CON: 4, DAT: 1, PUD: 4, DRV: 4
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*/
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static const struct samsung_pin_bank_type exynos850_bank_type_alive = {
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.fld_width = { 4, 1, 4, 4, },
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.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
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};
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/* Pad retention control code for accessing PMU regmap */
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static atomic_t exynos_shared_retention_refcnt;
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@ -422,3 +440,101 @@ const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = {
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.ctrl = exynos7_pin_ctrl,
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.num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl),
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};
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/* pin banks of exynos850 pin-controller 0 (ALIVE) */
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static const struct samsung_pin_bank_data exynos850_pin_banks0[] __initconst = {
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/* Must start with EINTG banks, ordered by EINT group number. */
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EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
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EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
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EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
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EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
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EXYNOS850_PIN_BANK_EINTW(4, 0x080, "gpa4", 0x10),
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EXYNOS850_PIN_BANK_EINTN(3, 0x0a0, "gpq0"),
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};
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/* pin banks of exynos850 pin-controller 1 (CMGP) */
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static const struct samsung_pin_bank_data exynos850_pin_banks1[] __initconst = {
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/* Must start with EINTG banks, ordered by EINT group number. */
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EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00),
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EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04),
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EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08),
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EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0c),
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EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10),
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EXYNOS850_PIN_BANK_EINTW(1, 0x0a0, "gpm5", 0x14),
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EXYNOS850_PIN_BANK_EINTW(1, 0x0c0, "gpm6", 0x18),
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EXYNOS850_PIN_BANK_EINTW(1, 0x0e0, "gpm7", 0x1c),
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};
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/* pin banks of exynos850 pin-controller 2 (AUD) */
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static const struct samsung_pin_bank_data exynos850_pin_banks2[] __initconst = {
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/* Must start with EINTG banks, ordered by EINT group number. */
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EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
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EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gpb1", 0x04),
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};
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/* pin banks of exynos850 pin-controller 3 (HSI) */
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static const struct samsung_pin_bank_data exynos850_pin_banks3[] __initconst = {
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/* Must start with EINTG banks, ordered by EINT group number. */
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EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf2", 0x00),
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};
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/* pin banks of exynos850 pin-controller 4 (CORE) */
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static const struct samsung_pin_bank_data exynos850_pin_banks4[] __initconst = {
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/* Must start with EINTG banks, ordered by EINT group number. */
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EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00),
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EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04),
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};
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/* pin banks of exynos850 pin-controller 5 (PERI) */
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static const struct samsung_pin_bank_data exynos850_pin_banks5[] __initconst = {
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/* Must start with EINTG banks, ordered by EINT group number. */
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EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpg0", 0x00),
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EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpp0", 0x04),
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EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08),
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EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c),
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EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg1", 0x10),
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EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpg2", 0x14),
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EXYNOS850_PIN_BANK_EINTG(1, 0x0c0, "gpg3", 0x18),
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EXYNOS850_PIN_BANK_EINTG(3, 0x0e0, "gpc0", 0x1c),
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EXYNOS850_PIN_BANK_EINTG(6, 0x100, "gpc1", 0x20),
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};
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static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = {
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{
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/* pin-controller instance 0 ALIVE data */
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.pin_banks = exynos850_pin_banks0,
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.nr_banks = ARRAY_SIZE(exynos850_pin_banks0),
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.eint_gpio_init = exynos_eint_gpio_init,
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.eint_wkup_init = exynos_eint_wkup_init,
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}, {
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/* pin-controller instance 1 CMGP data */
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.pin_banks = exynos850_pin_banks1,
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.nr_banks = ARRAY_SIZE(exynos850_pin_banks1),
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.eint_gpio_init = exynos_eint_gpio_init,
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.eint_wkup_init = exynos_eint_wkup_init,
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}, {
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/* pin-controller instance 2 AUD data */
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.pin_banks = exynos850_pin_banks2,
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.nr_banks = ARRAY_SIZE(exynos850_pin_banks2),
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}, {
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/* pin-controller instance 3 HSI data */
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.pin_banks = exynos850_pin_banks3,
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.nr_banks = ARRAY_SIZE(exynos850_pin_banks3),
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.eint_gpio_init = exynos_eint_gpio_init,
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}, {
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/* pin-controller instance 4 CORE data */
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.pin_banks = exynos850_pin_banks4,
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.nr_banks = ARRAY_SIZE(exynos850_pin_banks4),
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.eint_gpio_init = exynos_eint_gpio_init,
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}, {
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/* pin-controller instance 5 PERI data */
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.pin_banks = exynos850_pin_banks5,
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.nr_banks = ARRAY_SIZE(exynos850_pin_banks5),
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.eint_gpio_init = exynos_eint_gpio_init,
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},
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};
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const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = {
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.ctrl = exynos850_pin_ctrl,
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.num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl),
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};
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@ -108,6 +108,35 @@
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.pctl_res_idx = pctl_idx, \
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} \
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#define EXYNOS850_PIN_BANK_EINTN(pins, reg, id) \
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{ \
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.type = &exynos850_bank_type_alive, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_NONE, \
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.name = id \
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}
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#define EXYNOS850_PIN_BANK_EINTG(pins, reg, id, offs) \
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{ \
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.type = &exynos850_bank_type_off, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_GPIO, \
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.eint_offset = offs, \
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.name = id \
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}
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#define EXYNOS850_PIN_BANK_EINTW(pins, reg, id, offs) \
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{ \
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.type = &exynos850_bank_type_alive, \
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.pctl_offset = reg, \
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.nr_pins = pins, \
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.eint_type = EINT_TYPE_WKUP, \
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.eint_offset = offs, \
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.name = id \
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}
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/**
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* struct exynos_weint_data: irq specific data for all the wakeup interrupts
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* generated by the external wakeup interrupt controller.
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@ -1264,6 +1264,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
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.data = &exynos5433_of_data },
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{ .compatible = "samsung,exynos7-pinctrl",
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.data = &exynos7_of_data },
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{ .compatible = "samsung,exynos850-pinctrl",
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.data = &exynos850_of_data },
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#endif
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#ifdef CONFIG_PINCTRL_S3C64XX
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{ .compatible = "samsung,s3c64xx-pinctrl",
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@ -339,6 +339,7 @@ extern const struct samsung_pinctrl_of_match_data exynos5410_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos5420_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos5433_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
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extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
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extern const struct samsung_pinctrl_of_match_data s3c2412_of_data;
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extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;
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