mirror of
https://github.com/torvalds/linux
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Merge branch 'lorenzo/pci/mediatek'
- implement Mediatek chained IRQ handling (Honghui Zhang) - fix vendor ID & class type for Mediatek MT7622 (Honghui Zhang) * lorenzo/pci/mediatek: PCI: mediatek: Implement chained IRQ handling setup PCI: mediatek: Set up vendor ID and class type for MT7622 # Conflicts: # drivers/pci/host/Kconfig
This commit is contained in:
Bjorn Helgaas
commit
cc64520f97
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@ -193,6 +193,7 @@ config PCIE_MEDIATEK
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bool "MediaTek PCIe controller"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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depends on OF
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depends on PCI_MSI_IRQ_DOMAIN
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select PCIEPORTBUS
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help
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Say Y here if you want to enable PCIe controller support on
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@ -11,8 +11,10 @@
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/msi.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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@ -68,6 +70,10 @@
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/* PCIe V2 per-port registers */
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#define PCIE_MSI_VECTOR 0x0c0
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#define PCIE_CONF_VEND_ID 0x100
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#define PCIE_CONF_CLASS_ID 0x106
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#define PCIE_INT_MASK 0x420
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#define INTX_MASK GENMASK(19, 16)
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#define INTX_SHIFT 16
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@ -127,13 +133,13 @@ struct mtk_pcie_port;
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/**
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* struct mtk_pcie_soc - differentiate between host generations
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* @has_msi: whether this host supports MSI interrupts or not
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* @need_fix_class_id: whether this host's class ID needed to be fixed or not
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* @ops: pointer to configuration access functions
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* @startup: pointer to controller setting functions
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* @setup_irq: pointer to initialize IRQ functions
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*/
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struct mtk_pcie_soc {
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bool has_msi;
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bool need_fix_class_id;
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struct pci_ops *ops;
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int (*startup)(struct mtk_pcie_port *port);
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int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
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@ -157,7 +163,9 @@ struct mtk_pcie_soc {
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* @lane: lane count
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* @slot: port slot
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* @irq_domain: legacy INTx IRQ domain
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* @inner_domain: inner IRQ domain
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* @msi_domain: MSI IRQ domain
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* @lock: protect the msi_irq_in_use bitmap
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* @msi_irq_in_use: bit map for assigned MSI IRQ
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*/
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struct mtk_pcie_port {
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@ -175,7 +183,9 @@ struct mtk_pcie_port {
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u32 lane;
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u32 slot;
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struct irq_domain *irq_domain;
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struct irq_domain *inner_domain;
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struct irq_domain *msi_domain;
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struct mutex lock;
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DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM);
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};
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@ -377,6 +387,7 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
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{
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struct mtk_pcie *pcie = port->pcie;
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struct resource *mem = &pcie->mem;
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const struct mtk_pcie_soc *soc = port->pcie->soc;
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u32 val;
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size_t size;
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int err;
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@ -405,6 +416,15 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
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PCIE_MAC_SRSTB | PCIE_CRSTB;
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writel(val, port->base + PCIE_RST_CTRL);
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/* Set up vendor ID and class code */
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if (soc->need_fix_class_id) {
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val = PCI_VENDOR_ID_MEDIATEK;
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writew(val, port->base + PCIE_CONF_VEND_ID);
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val = PCI_CLASS_BRIDGE_HOST;
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writew(val, port->base + PCIE_CONF_CLASS_ID);
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}
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/* 100ms timeout value should be enough for Gen1/2 training */
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err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
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!!(val & PCIE_PORT_LINKUP_V2), 20,
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@ -432,103 +452,130 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
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return 0;
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}
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static int mtk_pcie_msi_alloc(struct mtk_pcie_port *port)
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static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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{
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int msi;
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msi = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM);
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if (msi < MTK_MSI_IRQS_NUM)
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set_bit(msi, port->msi_irq_in_use);
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else
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return -ENOSPC;
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return msi;
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}
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static void mtk_pcie_msi_free(struct mtk_pcie_port *port, unsigned long hwirq)
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{
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clear_bit(hwirq, port->msi_irq_in_use);
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}
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static int mtk_pcie_msi_setup_irq(struct msi_controller *chip,
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struct pci_dev *pdev, struct msi_desc *desc)
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{
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struct mtk_pcie_port *port;
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struct msi_msg msg;
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unsigned int irq;
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int hwirq;
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phys_addr_t msg_addr;
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port = mtk_pcie_find_port(pdev->bus, pdev->devfn);
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if (!port)
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return -EINVAL;
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hwirq = mtk_pcie_msi_alloc(port);
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if (hwirq < 0)
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return hwirq;
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irq = irq_create_mapping(port->msi_domain, hwirq);
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if (!irq) {
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mtk_pcie_msi_free(port, hwirq);
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return -EINVAL;
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}
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chip->dev = &pdev->dev;
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irq_set_msi_desc(irq, desc);
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struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
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phys_addr_t addr;
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/* MT2712/MT7622 only support 32-bit MSI addresses */
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msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
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msg.address_hi = 0;
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msg.address_lo = lower_32_bits(msg_addr);
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msg.data = hwirq;
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addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
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msg->address_hi = 0;
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msg->address_lo = lower_32_bits(addr);
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pci_write_msi_msg(irq, &msg);
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msg->data = data->hwirq;
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dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n",
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(int)data->hwirq, msg->address_hi, msg->address_lo);
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}
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static int mtk_msi_set_affinity(struct irq_data *irq_data,
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const struct cpumask *mask, bool force)
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{
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return -EINVAL;
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}
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static void mtk_msi_ack_irq(struct irq_data *data)
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{
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struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
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u32 hwirq = data->hwirq;
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writel(1 << hwirq, port->base + PCIE_IMSI_STATUS);
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}
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static struct irq_chip mtk_msi_bottom_irq_chip = {
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.name = "MTK MSI",
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.irq_compose_msi_msg = mtk_compose_msi_msg,
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.irq_set_affinity = mtk_msi_set_affinity,
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.irq_ack = mtk_msi_ack_irq,
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};
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static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *args)
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{
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struct mtk_pcie_port *port = domain->host_data;
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unsigned long bit;
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WARN_ON(nr_irqs != 1);
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mutex_lock(&port->lock);
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bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM);
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if (bit >= MTK_MSI_IRQS_NUM) {
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mutex_unlock(&port->lock);
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return -ENOSPC;
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}
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__set_bit(bit, port->msi_irq_in_use);
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mutex_unlock(&port->lock);
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irq_domain_set_info(domain, virq, bit, &mtk_msi_bottom_irq_chip,
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domain->host_data, handle_edge_irq,
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NULL, NULL);
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return 0;
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}
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static void mtk_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
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static void mtk_pcie_irq_domain_free(struct irq_domain *domain,
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unsigned int virq, unsigned int nr_irqs)
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{
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struct pci_dev *pdev = to_pci_dev(chip->dev);
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struct irq_data *d = irq_get_irq_data(irq);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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struct mtk_pcie_port *port;
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struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d);
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port = mtk_pcie_find_port(pdev->bus, pdev->devfn);
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if (!port)
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return;
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mutex_lock(&port->lock);
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irq_dispose_mapping(irq);
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mtk_pcie_msi_free(port, hwirq);
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if (!test_bit(d->hwirq, port->msi_irq_in_use))
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dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n",
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d->hwirq);
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else
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__clear_bit(d->hwirq, port->msi_irq_in_use);
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mutex_unlock(&port->lock);
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irq_domain_free_irqs_parent(domain, virq, nr_irqs);
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}
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static struct msi_controller mtk_pcie_msi_chip = {
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.setup_irq = mtk_pcie_msi_setup_irq,
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.teardown_irq = mtk_msi_teardown_irq,
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static const struct irq_domain_ops msi_domain_ops = {
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.alloc = mtk_pcie_irq_domain_alloc,
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.free = mtk_pcie_irq_domain_free,
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};
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static struct irq_chip mtk_msi_irq_chip = {
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.name = "MTK PCIe MSI",
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.irq_enable = pci_msi_unmask_irq,
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.irq_disable = pci_msi_mask_irq,
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.irq_ack = irq_chip_ack_parent,
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.irq_mask = pci_msi_mask_irq,
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.irq_unmask = pci_msi_unmask_irq,
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};
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static int mtk_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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static struct msi_domain_info mtk_msi_domain_info = {
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
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MSI_FLAG_PCI_MSIX),
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.chip = &mtk_msi_irq_chip,
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};
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static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port)
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{
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irq_set_chip_and_handler(irq, &mtk_msi_irq_chip, handle_simple_irq);
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irq_set_chip_data(irq, domain->host_data);
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struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node);
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mutex_init(&port->lock);
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port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM,
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&msi_domain_ops, port);
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if (!port->inner_domain) {
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dev_err(port->pcie->dev, "failed to create IRQ domain\n");
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return -ENOMEM;
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}
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port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info,
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port->inner_domain);
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if (!port->msi_domain) {
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dev_err(port->pcie->dev, "failed to create MSI domain\n");
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irq_domain_remove(port->inner_domain);
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return -ENOMEM;
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}
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return 0;
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}
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static const struct irq_domain_ops msi_domain_ops = {
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.map = mtk_pcie_msi_map,
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};
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static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
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{
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u32 val;
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@ -561,6 +608,7 @@ static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port,
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{
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struct device *dev = port->pcie->dev;
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struct device_node *pcie_intc_node;
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int ret;
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/* Setup INTx */
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pcie_intc_node = of_get_next_child(node, NULL);
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@ -577,27 +625,28 @@ static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port,
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}
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if (IS_ENABLED(CONFIG_PCI_MSI)) {
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port->msi_domain = irq_domain_add_linear(node, MTK_MSI_IRQS_NUM,
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&msi_domain_ops,
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&mtk_pcie_msi_chip);
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if (!port->msi_domain) {
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dev_err(dev, "failed to create MSI IRQ domain\n");
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return -ENODEV;
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}
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ret = mtk_pcie_allocate_msi_domains(port);
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if (ret)
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return ret;
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mtk_pcie_enable_msi(port);
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}
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return 0;
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}
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static irqreturn_t mtk_pcie_intr_handler(int irq, void *data)
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static void mtk_pcie_intr_handler(struct irq_desc *desc)
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{
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struct mtk_pcie_port *port = (struct mtk_pcie_port *)data;
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struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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unsigned long status;
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u32 virq;
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u32 bit = INTX_SHIFT;
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while ((status = readl(port->base + PCIE_INT_STATUS)) & INTX_MASK) {
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chained_irq_enter(irqchip, desc);
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status = readl(port->base + PCIE_INT_STATUS);
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if (status & INTX_MASK) {
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for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
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/* Clear the INTx */
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writel(1 << bit, port->base + PCIE_INT_STATUS);
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@ -608,14 +657,12 @@ static irqreturn_t mtk_pcie_intr_handler(int irq, void *data)
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}
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if (IS_ENABLED(CONFIG_PCI_MSI)) {
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while ((status = readl(port->base + PCIE_INT_STATUS)) & MSI_STATUS) {
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if (status & MSI_STATUS){
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unsigned long imsi_status;
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while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
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for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) {
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/* Clear the MSI */
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writel(1 << bit, port->base + PCIE_IMSI_STATUS);
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virq = irq_find_mapping(port->msi_domain, bit);
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virq = irq_find_mapping(port->inner_domain, bit);
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generic_handle_irq(virq);
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}
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}
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@ -624,7 +671,9 @@ static irqreturn_t mtk_pcie_intr_handler(int irq, void *data)
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}
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}
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|
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return IRQ_HANDLED;
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chained_irq_exit(irqchip, desc);
|
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|
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return;
|
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}
|
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|
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static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
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|
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@ -635,20 +684,15 @@ static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
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struct platform_device *pdev = to_platform_device(dev);
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int err, irq;
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irq = platform_get_irq(pdev, port->slot);
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err = devm_request_irq(dev, irq, mtk_pcie_intr_handler,
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IRQF_SHARED, "mtk-pcie", port);
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if (err) {
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dev_err(dev, "unable to request IRQ %d\n", irq);
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return err;
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}
|
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|
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err = mtk_pcie_init_irq_domain(port, node);
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if (err) {
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dev_err(dev, "failed to init PCIe IRQ domain\n");
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return err;
|
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}
|
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|
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irq = platform_get_irq(pdev, port->slot);
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irq_set_chained_handler_and_data(irq, mtk_pcie_intr_handler, port);
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return 0;
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}
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|
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@ -1082,8 +1126,6 @@ static int mtk_pcie_register_host(struct pci_host_bridge *host)
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host->map_irq = of_irq_parse_and_map_pci;
|
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host->swizzle_irq = pci_common_swizzle;
|
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host->sysdata = pcie;
|
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if (IS_ENABLED(CONFIG_PCI_MSI) && pcie->soc->has_msi)
|
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host->msi = &mtk_pcie_msi_chip;
|
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|
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err = pci_scan_root_bus_bridge(host);
|
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if (err < 0)
|
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|
|
@ -1144,8 +1186,14 @@ static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
|
|||
.startup = mtk_pcie_startup_port,
|
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};
|
||||
|
||||
static const struct mtk_pcie_soc mtk_pcie_soc_v2 = {
|
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.has_msi = true,
|
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static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = {
|
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.ops = &mtk_pcie_ops_v2,
|
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.startup = mtk_pcie_startup_port_v2,
|
||||
.setup_irq = mtk_pcie_setup_irq,
|
||||
};
|
||||
|
||||
static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = {
|
||||
.need_fix_class_id = true,
|
||||
.ops = &mtk_pcie_ops_v2,
|
||||
.startup = mtk_pcie_startup_port_v2,
|
||||
.setup_irq = mtk_pcie_setup_irq,
|
||||
|
|
@ -1154,8 +1202,8 @@ static const struct mtk_pcie_soc mtk_pcie_soc_v2 = {
|
|||
static const struct of_device_id mtk_pcie_ids[] = {
|
||||
{ .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
|
||||
{ .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
|
||||
{ .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_v2 },
|
||||
{ .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_v2 },
|
||||
{ .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
|
||||
{ .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
|
||||
{},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -2120,6 +2120,8 @@
|
|||
|
||||
#define PCI_VENDOR_ID_MYRICOM 0x14c1
|
||||
|
||||
#define PCI_VENDOR_ID_MEDIATEK 0x14c3
|
||||
|
||||
#define PCI_VENDOR_ID_TITAN 0x14D2
|
||||
#define PCI_DEVICE_ID_TITAN_010L 0x8001
|
||||
#define PCI_DEVICE_ID_TITAN_100L 0x8010
|
||||
|
|
|
|||
Loading…
Reference in a new issue