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ASoC: SOF: ipc4: Add macros for chain-dma message bits
In the chained DMA mode, the firmware allocates buffers for the host and link DMA, and takes care of copying data between host- and link-DMA buffers in a low-latency thread. This is different to a regular pipeline, no processing is allowed, and the connection between host- and link DMA is handled with a dedicated IPC. This patch exposes the macros needed to create the required IPC messages. Signed-off-by: Jyri Sarha <jyri.sarha@intel.com> Reviewed-by: Rander Wang <rander.wang@intel.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com> Link: https://lore.kernel.org/r/20230321092654.7292-3-peter.ujfalusi@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -196,6 +196,35 @@ enum sof_ipc4_pipeline_state {
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#define SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID_SHIFT 16
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#define SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID(x) ((x) << SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID_SHIFT)
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/* chain dma ipc message */
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#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_SHIFT 0
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#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_MASK GENMASK(4, 0)
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#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID(x) (((x) << SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_SHIFT) & \
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SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_MASK)
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#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_SHIFT 8
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#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_MASK GENMASK(12, 8)
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#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID(x) (((x) << SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_SHIFT) & \
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SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_MASK)
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#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_SHIFT 16
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#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_MASK BIT(16)
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#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_SHIFT)
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#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE_SHIFT 17
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#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE_MASK BIT(17)
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#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_ENABLE_SHIFT)
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#define SOF_IPC4_GLB_CHAIN_DMA_SCS_SHIFT 18
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#define SOF_IPC4_GLB_CHAIN_DMA_SCS_MASK BIT(18)
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#define SOF_IPC4_GLB_CHAIN_DMA_SCS(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_SCS_SHIFT)
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#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_SHIFT 0
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#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_MASK GENMASK(24, 0)
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#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE(x) (((x) << \
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SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_SHIFT) & \
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SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_MASK)
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enum sof_ipc4_channel_config {
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/* one channel only. */
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SOF_IPC4_CHANNEL_CONFIG_MONO,
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