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arc: perf: Move static structs to where they're really used
It is all well described by Stephen Rothwell who initially spotted that:
----------------------------->8----------------------------
After merging the origin tree, today's linux-next build (arc
haps_hs_smp_defconfig+kselftest) produced these warnings:
arch/arc/include/asm/perf_event.h:126:27: warning: 'arc_pmu_cache_map' defined but not used [-Wunused-const-variable=]
arch/arc/include/asm/perf_event.h:91:27: warning: 'arc_pmu_ev_hw_map' defined but not used [-Wunused-const-variable=]
Introduced by commit 0dd450fe13 ("ARC: Add perf support for ARC700 cores")
The 2 static arrays should be moved into arch/arc/kernel/perf_event.c
(the only place that uses them). We get the warning because perf_event.h
is also included by arch/arc/kernel/unaligned.c.
----------------------------->8----------------------------
Could be easily reproduced by running make with "W=1" on any up-to-date
sources, when extra warnings get enabled (in particular
"-Wunused-const-variable"), otherwise disabled by default in the top-level
Makefile as "These warnings generated too much noise in a regular build".
Cc: Mischa Jonker <mjonker@synopsys.com>
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@kernel.org>
This commit is contained in:
Alexey Brodkin
Vineet Gupta
parent
1b2a62beca
commit
ca295ffb91
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@ -63,166 +63,4 @@ struct arc_reg_cc_build {
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#define PERF_COUNT_ARC_HW_MAX (PERF_COUNT_HW_MAX + 8)
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/*
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* Some ARC pct quirks:
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*
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* PERF_COUNT_HW_STALLED_CYCLES_BACKEND
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* PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
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* The ARC 700 can either measure stalls per pipeline stage, or all stalls
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* combined; for now we assign all stalls to STALLED_CYCLES_BACKEND
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* and all pipeline flushes (e.g. caused by mispredicts, etc.) to
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* STALLED_CYCLES_FRONTEND.
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*
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* We could start multiple performance counters and combine everything
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* afterwards, but that makes it complicated.
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*
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* Note that I$ cache misses aren't counted by either of the two!
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*/
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/*
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* ARC PCT has hardware conditions with fixed "names" but variable "indexes"
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* (based on a specific RTL build)
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* Below is the static map between perf generic/arc specific event_id and
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* h/w condition names.
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* At the time of probe, we loop thru each index and find it's name to
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* complete the mapping of perf event_id to h/w index as latter is needed
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* to program the counter really
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*/
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static const char * const arc_pmu_ev_hw_map[] = {
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/* count cycles */
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[PERF_COUNT_HW_CPU_CYCLES] = "crun",
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[PERF_COUNT_HW_REF_CPU_CYCLES] = "crun",
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[PERF_COUNT_HW_BUS_CYCLES] = "crun",
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[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = "bflush",
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[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = "bstall",
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/* counts condition */
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[PERF_COUNT_HW_INSTRUCTIONS] = "iall",
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/* All jump instructions that are taken */
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmptak",
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#ifdef CONFIG_ISA_ARCV2
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[PERF_COUNT_HW_BRANCH_MISSES] = "bpmp",
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#else
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[PERF_COUNT_ARC_BPOK] = "bpok", /* NP-NT, PT-T, PNT-NT */
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[PERF_COUNT_HW_BRANCH_MISSES] = "bpfail", /* NP-T, PT-NT, PNT-T */
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#endif
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[PERF_COUNT_ARC_LDC] = "imemrdc", /* Instr: mem read cached */
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[PERF_COUNT_ARC_STC] = "imemwrc", /* Instr: mem write cached */
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[PERF_COUNT_ARC_DCLM] = "dclm", /* D-cache Load Miss */
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[PERF_COUNT_ARC_DCSM] = "dcsm", /* D-cache Store Miss */
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[PERF_COUNT_ARC_ICM] = "icm", /* I-cache Miss */
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[PERF_COUNT_ARC_EDTLB] = "edtlb", /* D-TLB Miss */
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[PERF_COUNT_ARC_EITLB] = "eitlb", /* I-TLB Miss */
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[PERF_COUNT_HW_CACHE_REFERENCES] = "imemrdc", /* Instr: mem read cached */
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[PERF_COUNT_HW_CACHE_MISSES] = "dclm", /* D-cache Load Miss */
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};
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#define C(_x) PERF_COUNT_HW_CACHE_##_x
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#define CACHE_OP_UNSUPPORTED 0xffff
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static const unsigned int arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
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[C(L1D)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
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[C(RESULT_MISS)] = PERF_COUNT_ARC_DCLM,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = PERF_COUNT_ARC_STC,
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[C(RESULT_MISS)] = PERF_COUNT_ARC_DCSM,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(L1I)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = PERF_COUNT_HW_INSTRUCTIONS,
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[C(RESULT_MISS)] = PERF_COUNT_ARC_ICM,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(LL)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(DTLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
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[C(RESULT_MISS)] = PERF_COUNT_ARC_EDTLB,
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},
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/* DTLB LD/ST Miss not segregated by h/w*/
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(ITLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = PERF_COUNT_ARC_EITLB,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(BPU)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS,
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[C(RESULT_MISS)] = PERF_COUNT_HW_BRANCH_MISSES,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(NODE)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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};
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#endif /* __ASM_PERF_EVENT_H */
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@ -17,6 +17,168 @@
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/* HW holds 8 symbols + one for null terminator */
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#define ARCPMU_EVENT_NAME_LEN 9
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/*
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* Some ARC pct quirks:
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*
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* PERF_COUNT_HW_STALLED_CYCLES_BACKEND
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* PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
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* The ARC 700 can either measure stalls per pipeline stage, or all stalls
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* combined; for now we assign all stalls to STALLED_CYCLES_BACKEND
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* and all pipeline flushes (e.g. caused by mispredicts, etc.) to
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* STALLED_CYCLES_FRONTEND.
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*
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* We could start multiple performance counters and combine everything
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* afterwards, but that makes it complicated.
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*
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* Note that I$ cache misses aren't counted by either of the two!
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*/
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/*
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* ARC PCT has hardware conditions with fixed "names" but variable "indexes"
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* (based on a specific RTL build)
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* Below is the static map between perf generic/arc specific event_id and
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* h/w condition names.
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* At the time of probe, we loop thru each index and find it's name to
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* complete the mapping of perf event_id to h/w index as latter is needed
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* to program the counter really
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*/
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static const char * const arc_pmu_ev_hw_map[] = {
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/* count cycles */
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[PERF_COUNT_HW_CPU_CYCLES] = "crun",
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[PERF_COUNT_HW_REF_CPU_CYCLES] = "crun",
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[PERF_COUNT_HW_BUS_CYCLES] = "crun",
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[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = "bflush",
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[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = "bstall",
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/* counts condition */
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[PERF_COUNT_HW_INSTRUCTIONS] = "iall",
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/* All jump instructions that are taken */
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmptak",
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#ifdef CONFIG_ISA_ARCV2
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[PERF_COUNT_HW_BRANCH_MISSES] = "bpmp",
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#else
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[PERF_COUNT_ARC_BPOK] = "bpok", /* NP-NT, PT-T, PNT-NT */
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[PERF_COUNT_HW_BRANCH_MISSES] = "bpfail", /* NP-T, PT-NT, PNT-T */
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#endif
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[PERF_COUNT_ARC_LDC] = "imemrdc", /* Instr: mem read cached */
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[PERF_COUNT_ARC_STC] = "imemwrc", /* Instr: mem write cached */
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[PERF_COUNT_ARC_DCLM] = "dclm", /* D-cache Load Miss */
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[PERF_COUNT_ARC_DCSM] = "dcsm", /* D-cache Store Miss */
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[PERF_COUNT_ARC_ICM] = "icm", /* I-cache Miss */
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[PERF_COUNT_ARC_EDTLB] = "edtlb", /* D-TLB Miss */
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[PERF_COUNT_ARC_EITLB] = "eitlb", /* I-TLB Miss */
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[PERF_COUNT_HW_CACHE_REFERENCES] = "imemrdc", /* Instr: mem read cached */
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[PERF_COUNT_HW_CACHE_MISSES] = "dclm", /* D-cache Load Miss */
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};
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#define C(_x) PERF_COUNT_HW_CACHE_##_x
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#define CACHE_OP_UNSUPPORTED 0xffff
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static const unsigned int arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
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[C(L1D)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
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[C(RESULT_MISS)] = PERF_COUNT_ARC_DCLM,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = PERF_COUNT_ARC_STC,
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[C(RESULT_MISS)] = PERF_COUNT_ARC_DCSM,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(L1I)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = PERF_COUNT_HW_INSTRUCTIONS,
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[C(RESULT_MISS)] = PERF_COUNT_ARC_ICM,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(LL)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(DTLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
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[C(RESULT_MISS)] = PERF_COUNT_ARC_EDTLB,
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},
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/* DTLB LD/ST Miss not segregated by h/w*/
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(ITLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = PERF_COUNT_ARC_EITLB,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(BPU)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS,
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[C(RESULT_MISS)] = PERF_COUNT_HW_BRANCH_MISSES,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(NODE)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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};
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enum arc_pmu_attr_groups {
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ARCPMU_ATTR_GR_EVENTS,
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ARCPMU_ATTR_GR_FORMATS,
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