system/linux
system/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux synced 2024-07-22 11:10:46 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

net: phy: dp83822: Fix RGMII TX delay configuration

Browse source 
The logic for enabling the TX clock shift is inverse of enabling the RX
clock shift. The TX clock shift is disabled when DP83822_TX_CLK_SHIFT is
set. Correct the current behavior and always write the delay configuration
to ensure consistent delay settings regardless of bootloader configuration.

Reference: https://www.ti.com/lit/ds/symlink/dp83822i.pdf p. 69

Fixes: 8095295292 ("net: phy: DP83822: Add setting the fixed internal delay")
Signed-off-by: Tim Pambor <tp@osasysteme.de>
Link: https://lore.kernel.org/r/20240305110608.104072-1-tp@osasysteme.de
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Tim Pambor 2024-03-05 12:06:08 +01:00 committed by Jakub Kicinski
parent 9831e35efb
commit c8a5c731fd
1 changed files with 20 additions and 17 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

37
drivers/net/phy/dp83822.c
View file

@ -380,7 +380,7 @@ static int dp83822_config_init(struct phy_device *phydev)
{
struct dp83822_private *dp83822 = phydev->priv;
struct device *dev = &phydev->mdio.dev;
int rgmii_delay;
int rgmii_delay = 0;
s32 rx_int_delay;
s32 tx_int_delay;
int err = 0;
@ -390,30 +390,33 @@ static int dp83822_config_init(struct phy_device *phydev)
rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
true);
if (rx_int_delay <= 0)
rgmii_delay = 0;
else
rgmii_delay = DP83822_RX_CLK_SHIFT;
/* Set DP83822_RX_CLK_SHIFT to enable rx clk internal delay */
if (rx_int_delay > 0)
rgmii_delay |= DP83822_RX_CLK_SHIFT;
tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
false);
/* Set DP83822_TX_CLK_SHIFT to disable tx clk internal delay */
if (tx_int_delay <= 0)
rgmii_delay &= ~DP83822_TX_CLK_SHIFT;
else
rgmii_delay |= DP83822_TX_CLK_SHIFT;
if (rgmii_delay) {
err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
MII_DP83822_RCSR, rgmii_delay);
if (err)
return err;
}
err = phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83822_RCSR,
DP83822_RX_CLK_SHIFT | DP83822_TX_CLK_SHIFT, rgmii_delay);
if (err)
return err;
phy_set_bits_mmd(phydev, DP83822_DEVADDR,
MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,
MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
if (err)
return err;
} else {
phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
err = phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
if (err)
return err;
}
if (dp83822->fx_enabled) {