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https://github.com/torvalds/linux
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powerpc/64s/exception: move interrupt entry code above the common handler
This better reflects the order in which the code is executed. No generated code change except BUG line number constants. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20190802105709.27696-34-npiggin@gmail.com
This commit is contained in:
Nicholas Piggin
Michael Ellerman
parent
d1a8471888
commit
c7c5cbb42d
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@ -180,101 +180,6 @@ BEGIN_FTR_SECTION_NESTED(943) \
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std ra,offset(r13); \
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END_FTR_SECTION_NESTED(ftr,ftr,943)
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.macro INT_SAVE_SRR_AND_JUMP label, hsrr, set_ri
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ld r10,PACAKMSR(r13) /* get MSR value for kernel */
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.if ! \set_ri
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xori r10,r10,MSR_RI /* Clear MSR_RI */
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.endif
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.if \hsrr == EXC_HV_OR_STD
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BEGIN_FTR_SECTION
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mfspr r11,SPRN_HSRR0 /* save HSRR0 */
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mfspr r12,SPRN_HSRR1 /* and HSRR1 */
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mtspr SPRN_HSRR1,r10
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FTR_SECTION_ELSE
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mfspr r11,SPRN_SRR0 /* save SRR0 */
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mfspr r12,SPRN_SRR1 /* and SRR1 */
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mtspr SPRN_SRR1,r10
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
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.elseif \hsrr
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mfspr r11,SPRN_HSRR0 /* save HSRR0 */
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mfspr r12,SPRN_HSRR1 /* and HSRR1 */
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mtspr SPRN_HSRR1,r10
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.else
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mfspr r11,SPRN_SRR0 /* save SRR0 */
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mfspr r12,SPRN_SRR1 /* and SRR1 */
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mtspr SPRN_SRR1,r10
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.endif
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LOAD_HANDLER(r10, \label\())
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.if \hsrr == EXC_HV_OR_STD
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BEGIN_FTR_SECTION
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mtspr SPRN_HSRR0,r10
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HRFI_TO_KERNEL
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FTR_SECTION_ELSE
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mtspr SPRN_SRR0,r10
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RFI_TO_KERNEL
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
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.elseif \hsrr
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mtspr SPRN_HSRR0,r10
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HRFI_TO_KERNEL
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.else
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mtspr SPRN_SRR0,r10
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RFI_TO_KERNEL
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.endif
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b . /* prevent speculative execution */
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.endm
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/* INT_SAVE_SRR_AND_JUMP works for real or virt, this is faster but virt only */
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.macro INT_VIRT_SAVE_SRR_AND_JUMP label, hsrr
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#ifdef CONFIG_RELOCATABLE
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.if \hsrr == EXC_HV_OR_STD
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BEGIN_FTR_SECTION
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mfspr r11,SPRN_HSRR0 /* save HSRR0 */
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FTR_SECTION_ELSE
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mfspr r11,SPRN_SRR0 /* save SRR0 */
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
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.elseif \hsrr
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mfspr r11,SPRN_HSRR0 /* save HSRR0 */
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.else
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mfspr r11,SPRN_SRR0 /* save SRR0 */
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.endif
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LOAD_HANDLER(r12, \label\())
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mtctr r12
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.if \hsrr == EXC_HV_OR_STD
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BEGIN_FTR_SECTION
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mfspr r12,SPRN_HSRR1 /* and HSRR1 */
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FTR_SECTION_ELSE
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mfspr r12,SPRN_SRR1 /* and HSRR1 */
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
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.elseif \hsrr
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mfspr r12,SPRN_HSRR1 /* and HSRR1 */
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.else
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mfspr r12,SPRN_SRR1 /* and HSRR1 */
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.endif
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li r10,MSR_RI
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mtmsrd r10,1 /* Set RI (EE=0) */
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bctr
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#else
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.if \hsrr == EXC_HV_OR_STD
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BEGIN_FTR_SECTION
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mfspr r11,SPRN_HSRR0 /* save HSRR0 */
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mfspr r12,SPRN_HSRR1 /* and HSRR1 */
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FTR_SECTION_ELSE
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mfspr r11,SPRN_SRR0 /* save SRR0 */
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mfspr r12,SPRN_SRR1 /* and SRR1 */
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
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.elseif \hsrr
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mfspr r11,SPRN_HSRR0 /* save HSRR0 */
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mfspr r12,SPRN_HSRR1 /* and HSRR1 */
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.else
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mfspr r11,SPRN_SRR0 /* save SRR0 */
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mfspr r12,SPRN_SRR1 /* and SRR1 */
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.endif
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li r10,MSR_RI
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mtmsrd r10,1 /* Set RI (EE=0) */
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b \label
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#endif
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.endm
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/*
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* Branch to label using its 0xC000 address. This results in instruction
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* address suitable for MSR[IR]=0 or 1, which allows relocation to be turned
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@ -288,6 +193,15 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
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mtctr reg; \
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bctr
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.macro INT_KVM_HANDLER vec, hsrr, area, skip
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.if \hsrr
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TRAMP_KVM_BEGIN(do_kvm_H\vec\())
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.else
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TRAMP_KVM_BEGIN(do_kvm_\vec\())
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.endif
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KVM_HANDLER \vec, \hsrr, \area, \skip
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.endm
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#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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/*
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@ -390,6 +304,222 @@ END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948)
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.endm
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#endif
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.macro INT_SAVE_SRR_AND_JUMP label, hsrr, set_ri
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ld r10,PACAKMSR(r13) /* get MSR value for kernel */
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.if ! \set_ri
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xori r10,r10,MSR_RI /* Clear MSR_RI */
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.endif
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.if \hsrr == EXC_HV_OR_STD
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BEGIN_FTR_SECTION
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mfspr r11,SPRN_HSRR0 /* save HSRR0 */
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mfspr r12,SPRN_HSRR1 /* and HSRR1 */
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mtspr SPRN_HSRR1,r10
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FTR_SECTION_ELSE
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mfspr r11,SPRN_SRR0 /* save SRR0 */
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mfspr r12,SPRN_SRR1 /* and SRR1 */
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mtspr SPRN_SRR1,r10
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
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.elseif \hsrr
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mfspr r11,SPRN_HSRR0 /* save HSRR0 */
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mfspr r12,SPRN_HSRR1 /* and HSRR1 */
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mtspr SPRN_HSRR1,r10
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.else
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mfspr r11,SPRN_SRR0 /* save SRR0 */
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mfspr r12,SPRN_SRR1 /* and SRR1 */
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mtspr SPRN_SRR1,r10
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.endif
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LOAD_HANDLER(r10, \label\())
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.if \hsrr == EXC_HV_OR_STD
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BEGIN_FTR_SECTION
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mtspr SPRN_HSRR0,r10
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HRFI_TO_KERNEL
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FTR_SECTION_ELSE
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mtspr SPRN_SRR0,r10
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RFI_TO_KERNEL
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
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.elseif \hsrr
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mtspr SPRN_HSRR0,r10
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HRFI_TO_KERNEL
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.else
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mtspr SPRN_SRR0,r10
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RFI_TO_KERNEL
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.endif
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b . /* prevent speculative execution */
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.endm
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/* INT_SAVE_SRR_AND_JUMP works for real or virt, this is faster but virt only */
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.macro INT_VIRT_SAVE_SRR_AND_JUMP label, hsrr
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#ifdef CONFIG_RELOCATABLE
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.if \hsrr == EXC_HV_OR_STD
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BEGIN_FTR_SECTION
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mfspr r11,SPRN_HSRR0 /* save HSRR0 */
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FTR_SECTION_ELSE
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mfspr r11,SPRN_SRR0 /* save SRR0 */
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
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.elseif \hsrr
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mfspr r11,SPRN_HSRR0 /* save HSRR0 */
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.else
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mfspr r11,SPRN_SRR0 /* save SRR0 */
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.endif
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LOAD_HANDLER(r12, \label\())
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mtctr r12
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.if \hsrr == EXC_HV_OR_STD
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BEGIN_FTR_SECTION
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mfspr r12,SPRN_HSRR1 /* and HSRR1 */
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FTR_SECTION_ELSE
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mfspr r12,SPRN_SRR1 /* and HSRR1 */
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
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.elseif \hsrr
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mfspr r12,SPRN_HSRR1 /* and HSRR1 */
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.else
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mfspr r12,SPRN_SRR1 /* and HSRR1 */
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.endif
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li r10,MSR_RI
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mtmsrd r10,1 /* Set RI (EE=0) */
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bctr
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#else
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.if \hsrr == EXC_HV_OR_STD
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BEGIN_FTR_SECTION
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mfspr r11,SPRN_HSRR0 /* save HSRR0 */
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mfspr r12,SPRN_HSRR1 /* and HSRR1 */
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FTR_SECTION_ELSE
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mfspr r11,SPRN_SRR0 /* save SRR0 */
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mfspr r12,SPRN_SRR1 /* and SRR1 */
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
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.elseif \hsrr
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mfspr r11,SPRN_HSRR0 /* save HSRR0 */
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mfspr r12,SPRN_HSRR1 /* and HSRR1 */
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.else
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mfspr r11,SPRN_SRR0 /* save SRR0 */
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mfspr r12,SPRN_SRR1 /* and SRR1 */
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.endif
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li r10,MSR_RI
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mtmsrd r10,1 /* Set RI (EE=0) */
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b \label
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#endif
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.endm
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/*
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* This is the BOOK3S interrupt entry code macro.
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*
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* This can result in one of several things happening:
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* - Branch to the _common handler, relocated, in virtual mode.
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* These are normal interrupts (synchronous and asynchronous) handled by
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* the kernel.
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* - Branch to KVM, relocated but real mode interrupts remain in real mode.
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* These occur when HSTATE_IN_GUEST is set. The interrupt may be caused by
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* / intended for host or guest kernel, but KVM must always be involved
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* because the machine state is set for guest execution.
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* - Branch to the masked handler, unrelocated.
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* These occur when maskable asynchronous interrupts are taken with the
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* irq_soft_mask set.
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* - Branch to an "early" handler in real mode but relocated.
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* This is done if early=1. MCE and HMI use these to handle errors in real
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* mode.
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* - Fall through and continue executing in real, unrelocated mode.
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* This is done if early=2.
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*/
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.macro INT_HANDLER name, vec, ool=0, early=0, virt=0, hsrr=0, area=PACA_EXGEN, ri=1, dar=0, dsisr=0, bitmask=0, kvm=0
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SET_SCRATCH0(r13) /* save r13 */
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GET_PACA(r13)
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std r9,\area\()+EX_R9(r13) /* save r9 */
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OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR)
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HMT_MEDIUM
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std r10,\area\()+EX_R10(r13) /* save r10 - r12 */
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OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR)
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.if \ool
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.if !\virt
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b tramp_real_\name
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.pushsection .text
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TRAMP_REAL_BEGIN(tramp_real_\name)
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.else
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b tramp_virt_\name
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.pushsection .text
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TRAMP_VIRT_BEGIN(tramp_virt_\name)
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.endif
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.endif
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OPT_SAVE_REG_TO_PACA(\area\()+EX_PPR, r9, CPU_FTR_HAS_PPR)
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OPT_SAVE_REG_TO_PACA(\area\()+EX_CFAR, r10, CPU_FTR_CFAR)
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INTERRUPT_TO_KERNEL
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SAVE_CTR(r10, \area\())
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mfcr r9
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.if \kvm
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KVMTEST \hsrr \vec
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.endif
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.if \bitmask
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lbz r10,PACAIRQSOFTMASK(r13)
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andi. r10,r10,\bitmask
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/* Associate vector numbers with bits in paca->irq_happened */
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.if \vec == 0x500 || \vec == 0xea0
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li r10,PACA_IRQ_EE
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.elseif \vec == 0x900
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li r10,PACA_IRQ_DEC
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.elseif \vec == 0xa00 || \vec == 0xe80
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li r10,PACA_IRQ_DBELL
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.elseif \vec == 0xe60
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li r10,PACA_IRQ_HMI
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.elseif \vec == 0xf00
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li r10,PACA_IRQ_PMI
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.else
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.abort "Bad maskable vector"
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.endif
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.if \hsrr == EXC_HV_OR_STD
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BEGIN_FTR_SECTION
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bne masked_Hinterrupt
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FTR_SECTION_ELSE
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bne masked_interrupt
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
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.elseif \hsrr
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bne masked_Hinterrupt
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.else
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bne masked_interrupt
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.endif
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.endif
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std r11,\area\()+EX_R11(r13)
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std r12,\area\()+EX_R12(r13)
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/*
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* DAR/DSISR, SCRATCH0 must be read before setting MSR[RI],
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* because a d-side MCE will clobber those registers so is
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* not recoverable if they are live.
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*/
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GET_SCRATCH0(r10)
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std r10,\area\()+EX_R13(r13)
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.if \dar
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.if \hsrr
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mfspr r10,SPRN_HDAR
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.else
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mfspr r10,SPRN_DAR
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.endif
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std r10,\area\()+EX_DAR(r13)
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.endif
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.if \dsisr
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.if \hsrr
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mfspr r10,SPRN_HDSISR
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.else
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mfspr r10,SPRN_DSISR
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.endif
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stw r10,\area\()+EX_DSISR(r13)
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.endif
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.if \early == 2
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/* nothing more */
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.elseif \early
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mfctr r10 /* save ctr, even for !RELOCATABLE */
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BRANCH_TO_C000(r11, \name\()_early_common)
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.elseif !\virt
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INT_SAVE_SRR_AND_JUMP \name\()_common, \hsrr, \ri
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.else
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INT_VIRT_SAVE_SRR_AND_JUMP \name\()_common, \hsrr
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.endif
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.if \ool
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.popsection
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.endif
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.endm
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/*
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* On entry r13 points to the paca, r9-r13 are saved in the paca,
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* r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
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@ -555,136 +685,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
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#define FINISH_NAP
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#endif
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/*
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* This is the BOOK3S interrupt entry code macro.
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*
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* This can result in one of several things happening:
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* - Branch to the _common handler, relocated, in virtual mode.
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* These are normal interrupts (synchronous and asynchronous) handled by
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* the kernel.
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* - Branch to KVM, relocated but real mode interrupts remain in real mode.
|
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* These occur when HSTATE_IN_GUEST is set. The interrupt may be caused by
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* / intended for host or guest kernel, but KVM must always be involved
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* because the machine state is set for guest execution.
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* - Branch to the masked handler, unrelocated.
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* These occur when maskable asynchronous interrupts are taken with the
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* irq_soft_mask set.
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* - Branch to an "early" handler in real mode but relocated.
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* This is done if early=1. MCE and HMI use these to handle errors in real
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* mode.
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* - Fall through and continue executing in real, unrelocated mode.
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* This is done if early=2.
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*/
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.macro INT_HANDLER name, vec, ool=0, early=0, virt=0, hsrr=0, area=PACA_EXGEN, ri=1, dar=0, dsisr=0, bitmask=0, kvm=0
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SET_SCRATCH0(r13) /* save r13 */
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GET_PACA(r13)
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std r9,\area\()+EX_R9(r13) /* save r9 */
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OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR)
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HMT_MEDIUM
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std r10,\area\()+EX_R10(r13) /* save r10 - r12 */
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OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR)
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.if \ool
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.if !\virt
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b tramp_real_\name
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.pushsection .text
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TRAMP_REAL_BEGIN(tramp_real_\name)
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.else
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b tramp_virt_\name
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.pushsection .text
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TRAMP_VIRT_BEGIN(tramp_virt_\name)
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.endif
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.endif
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OPT_SAVE_REG_TO_PACA(\area\()+EX_PPR, r9, CPU_FTR_HAS_PPR)
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OPT_SAVE_REG_TO_PACA(\area\()+EX_CFAR, r10, CPU_FTR_CFAR)
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INTERRUPT_TO_KERNEL
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SAVE_CTR(r10, \area\())
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mfcr r9
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.if \kvm
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KVMTEST \hsrr \vec
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.endif
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.if \bitmask
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lbz r10,PACAIRQSOFTMASK(r13)
|
||||
andi. r10,r10,\bitmask
|
||||
/* Associate vector numbers with bits in paca->irq_happened */
|
||||
.if \vec == 0x500 || \vec == 0xea0
|
||||
li r10,PACA_IRQ_EE
|
||||
.elseif \vec == 0x900
|
||||
li r10,PACA_IRQ_DEC
|
||||
.elseif \vec == 0xa00 || \vec == 0xe80
|
||||
li r10,PACA_IRQ_DBELL
|
||||
.elseif \vec == 0xe60
|
||||
li r10,PACA_IRQ_HMI
|
||||
.elseif \vec == 0xf00
|
||||
li r10,PACA_IRQ_PMI
|
||||
.else
|
||||
.abort "Bad maskable vector"
|
||||
.endif
|
||||
|
||||
.if \hsrr == EXC_HV_OR_STD
|
||||
BEGIN_FTR_SECTION
|
||||
bne masked_Hinterrupt
|
||||
FTR_SECTION_ELSE
|
||||
bne masked_interrupt
|
||||
ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
|
||||
.elseif \hsrr
|
||||
bne masked_Hinterrupt
|
||||
.else
|
||||
bne masked_interrupt
|
||||
.endif
|
||||
.endif
|
||||
|
||||
std r11,\area\()+EX_R11(r13)
|
||||
std r12,\area\()+EX_R12(r13)
|
||||
|
||||
/*
|
||||
* DAR/DSISR, SCRATCH0 must be read before setting MSR[RI],
|
||||
* because a d-side MCE will clobber those registers so is
|
||||
* not recoverable if they are live.
|
||||
*/
|
||||
GET_SCRATCH0(r10)
|
||||
std r10,\area\()+EX_R13(r13)
|
||||
.if \dar
|
||||
.if \hsrr
|
||||
mfspr r10,SPRN_HDAR
|
||||
.else
|
||||
mfspr r10,SPRN_DAR
|
||||
.endif
|
||||
std r10,\area\()+EX_DAR(r13)
|
||||
.endif
|
||||
.if \dsisr
|
||||
.if \hsrr
|
||||
mfspr r10,SPRN_HDSISR
|
||||
.else
|
||||
mfspr r10,SPRN_DSISR
|
||||
.endif
|
||||
stw r10,\area\()+EX_DSISR(r13)
|
||||
.endif
|
||||
|
||||
.if \early == 2
|
||||
/* nothing more */
|
||||
.elseif \early
|
||||
mfctr r10 /* save ctr, even for !RELOCATABLE */
|
||||
BRANCH_TO_C000(r11, \name\()_early_common)
|
||||
.elseif !\virt
|
||||
INT_SAVE_SRR_AND_JUMP \name\()_common, \hsrr, \ri
|
||||
.else
|
||||
INT_VIRT_SAVE_SRR_AND_JUMP \name\()_common, \hsrr
|
||||
.endif
|
||||
.if \ool
|
||||
.popsection
|
||||
.endif
|
||||
.endm
|
||||
|
||||
.macro INT_KVM_HANDLER vec, hsrr, area, skip
|
||||
.if \hsrr
|
||||
TRAMP_KVM_BEGIN(do_kvm_H\vec\())
|
||||
.else
|
||||
TRAMP_KVM_BEGIN(do_kvm_\vec\())
|
||||
.endif
|
||||
KVM_HANDLER \vec, \hsrr, \area, \skip
|
||||
.endm
|
||||
|
||||
#define EXC_COMMON(name, realvec, hdlr) \
|
||||
EXC_COMMON_BEGIN(name); \
|
||||
INT_COMMON realvec, PACA_EXGEN, 1, 1, 1, 0, 0 ; \
|
||||
|
|
|
|||
Loading…
Reference in a new issue