From 0c2d652f0bd9fdfe367eca4ebf56ad354bf3b153 Mon Sep 17 00:00:00 2001 From: Simon Guinot Date: Sun, 1 Mar 2015 21:51:40 +0100 Subject: [PATCH 1/5] ARM: Kirkwood: add DT description for nas2big This patch adds the DT description for the LaCie "2Big NAS" (nas2big). This NAS is an hardware upgrade of the 2Big Network v2. Chipset and device list: - CPU Marvell 88F6282 1600Mhz - SDRAM memory, 256MB DDR3 (2x128MB x8) 533Mhz - 1 Ethernet Gigabit port (PHY Marvell 88E1518) - Flash memory, NAND 256MB TSOP48 - I2C EEPROM, 512 bytes (AT24 type) - PCIe SATA controller JMicron JMB360 (eSATA) - I2C fan controller GMT G762 (with a separate alarm GPIO) - 1 USB2 host port - 1 push button - 1 power switch - 2 SATA LEDs (bi-color, blue and red) - 1 power LED (bi-color, blue and red) - CPLD for LEDs and start-up management (Altera Max EMP3064) Signed-off-by: Simon Guinot Acked-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- .../bindings/arm/marvell,kirkwood.txt | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/kirkwood-nas2big.dts | 143 ++++++++++++++++++ 3 files changed, 145 insertions(+) create mode 100644 arch/arm/boot/dts/kirkwood-nas2big.dts diff --git a/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt b/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt index 925ecbf6e7b7..4f40ff3fee4b 100644 --- a/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt +++ b/Documentation/devicetree/bindings/arm/marvell,kirkwood.txt @@ -42,6 +42,7 @@ board. Currently known boards are: "lacie,cloudbox" "lacie,inetspace_v2" "lacie,laplug" +"lacie,nas2big" "lacie,netspace_lite_v2" "lacie,netspace_max_v2" "lacie,netspace_mini_v2" diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b9c3f8c8ca27..b2e51fe3da52 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -165,6 +165,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-lsxhl.dtb \ kirkwood-mplcec4.dtb \ kirkwood-mv88f6281gtw-ge.dtb \ + kirkwood-nas2big.dtb \ kirkwood-net2big.dtb \ kirkwood-net5big.dtb \ kirkwood-netgear_readynas_duo_v2.dtb \ diff --git a/arch/arm/boot/dts/kirkwood-nas2big.dts b/arch/arm/boot/dts/kirkwood-nas2big.dts new file mode 100644 index 000000000000..7427ec50b829 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-nas2big.dts @@ -0,0 +1,143 @@ +/* + * Device Tree file for LaCie 2Big NAS + * + * Copyright (C) 2015 Seagate + * + * Author: Simon Guinot + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. +*/ + +/dts-v1/; + +#include "kirkwood-netxbig.dtsi" + +/ { + model = "LaCie 2Big NAS"; + compatible = "lacie,nas2big", "lacie,netxbig", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + mbus { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; + + ocp@f1000000 { + rtc@10300 { + /* The on-chip RTC is not powered (no supercap). */ + status = "disabled"; + }; + spi@10600 { + /* + * A NAND flash is used instead of an SPI flash for + * the other netxbig-compatible boards. + */ + status = "disabled"; + }; + }; + + fan { + /* + * An I2C fan controller (GMT G762) is used but alarm is + * wired to a separate GPIO. + */ + compatible = "gpio-fan"; + alarm-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + }; + + regulators: regulators { + status = "okay"; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + + regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "hdd1power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; + }; + clocks { + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; + + /* + * An external I2C RTC (Dallas DS1337S+) is used. This allows + * to power-up the board on an RTC alarm. The external RTC can + * be kept powered, even when the SoC is off. + */ + rtc@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + interrupts = <43>; + }; + g762@3e { + compatible = "gmt,g762"; + reg = <0x3e>; + clocks = <&g762_clk>; + }; +}; + +&nand { + chip-delay = <50>; + status = "okay"; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "uImage"; + reg = <0x100000 0x1000000>; + }; + + partition@1100000 { + label = "root"; + reg = <0x1100000 0x8000000>; + }; + + partition@9100000 { + label = "unused"; + reg = <0x9100000 0x6f00000>; + }; +}; From a87cd07b88b4797d50d11fa1089705a284ae087f Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 3 Mar 2015 11:43:17 +0100 Subject: [PATCH 2/5] ARM: mvebu: Enable Performance Monitor Unit on Armada XP/370 SoCs The Armada 370 and XP SoCs have Cortex-A9 compatible CPUs, and with a Performance Monitoring Unit. Enable it so that we can have hardware-assisted perf support. Signed-off-by: Maxime Ripard Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-370-xp.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 7b3393e264f8..ec96f0b36346 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -73,6 +73,11 @@ cpu@0 { }; }; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts-extended = <&mpic 3>; + }; + soc { #address-cells = <2>; #size-cells = <1>; From 7f592c39d4975d9e6d3d0ebcf39695a487a6dc4e Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Tue, 3 Mar 2015 11:43:18 +0100 Subject: [PATCH 3/5] ARM: mvebu: Enable Performance Monitor Unit on Armada 375 SoC The Armada 375 SoC has a Cortex-A9 CPU, and so the PMU is available to be used. This commit enables it in the devicetree. Signed-off-by: Ezequiel Garcia Signed-off-by: Maxime Ripard Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-375.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index c6fedf2bfe3d..c675257f2377 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -96,6 +96,11 @@ cpu@1 { }; }; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts-extended = <&mpic 3>; + }; + soc { compatible = "marvell,armada375-mbus", "simple-bus"; #address-cells = <2>; From 754c4b1b2bddc6881889be9b4aa549d1647ef9ca Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Tue, 3 Mar 2015 11:43:19 +0100 Subject: [PATCH 4/5] ARM: mvebu: Enable Performance Monitor Unit on Armada 380/385 SoC The Armada 380 and 385 SoCs have a Cortex-A9 CPU, so the PMU is available to be used. This commit enables it in the devicetree. Signed-off-by: Ezequiel Garcia Signed-off-by: Maxime Ripard Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-38x.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 1a2dc370792f..ed2dd8ba4080 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -63,6 +63,11 @@ aliases { serial1 = &uart1; }; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts-extended = <&mpic 3>; + }; + soc { compatible = "marvell,armada380-mbus", "simple-bus"; #address-cells = <2>; From 7776ab70d75ff9857343e44e428744d81c30ce1b Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Mon, 19 Jan 2015 14:01:14 +0100 Subject: [PATCH 5/5] ARM: mvebu: armada-385-ap: Enable USB3 port The Armada 385 AP board has a USB3 port exposed that uses a GPIO to drive the VBUS line. Enable the needed drivers to support this. Signed-off-by: Maxime Ripard Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-db-ap.dts | 28 ++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts index d6b0f7db9624..7219ac3a3d90 100644 --- a/arch/arm/boot/dts/armada-385-db-ap.dts +++ b/arch/arm/boot/dts/armada-385-db-ap.dts @@ -125,6 +125,13 @@ uart1: serial@12100 { status = "okay"; }; + pinctrl@18000 { + xhci0_vbus_pins: xhci0-vbus-pins { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + }; + ethernet@30000 { status = "okay"; phy = <&phy2>; @@ -162,6 +169,11 @@ nfc: flash@d0000 { marvell,nand-enable-arbiter; nand-on-flash-bbt; }; + + usb3@f0000 { + status = "okay"; + usb-phy = <&usb3_phy>; + }; }; pcie-controller { @@ -187,4 +199,20 @@ pcie@3,0 { }; }; }; + + usb3_phy: usb3_phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <®_xhci0_vbus>; + }; + + reg_xhci0_vbus: xhci0-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&xhci0_vbus_pins>; + regulator-name = "xhci0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; };