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ARM: S5PV210: Rearrange assignment of clock for fout apll/mpll/epll clocks
The assignment of clock rates for fout apll/mpll/epll is moved further up in the s5pv210_setup_clocks function because the subsequent patches require the clock rate of fout clocks to be setup. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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1 changed files with 4 additions and 4 deletions
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@ -369,6 +369,10 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
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mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
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epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
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clk_fout_apll.rate = apll;
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clk_fout_mpll.rate = mpll;
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clk_fout_epll.rate = epll;
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printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld",
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apll, mpll, epll);
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@ -398,10 +402,6 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
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HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
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armclk, hclk200, hclk166, hclk133, pclk100, pclk83, pclk66);
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clk_fout_apll.rate = apll;
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clk_fout_mpll.rate = mpll;
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clk_fout_epll.rate = epll;
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clk_f.rate = armclk;
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clk_h.rate = hclk133;
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clk_p.rate = pclk66;
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