system/linux
system/linux
1
0
Fork 0
mirror of https://github.com/torvalds/linux synced 2024-09-20 02:57:25 +00:00
Code Issues Packages Projects Releases Wiki Activity

mfd: ti_am335x_tscadc: Reword the comment explaining the dividers

Browse source 
The comment misses the main information which is that we assume that a
sample takes 15 ADC clock cycles to be generated. Let's take the
occasion to rework a little bit this comment.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20211015081506.933180-14-miquel.raynal@bootlin.com
This commit is contained in:
Miquel Raynal 2021-10-15 10:14:31 +02:00 committed by Lee Jones
parent 36e48f07ba
commit c4359f750a
1 changed files with 6 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
drivers/mfd/ti_am335x_tscadc.c
View file

@ -199,12 +199,12 @@ static int ti_tscadc_probe(struct platform_device *pdev)
pm_runtime_get_sync(&pdev->dev); pm_runtime_get_sync(&pdev->dev);
/* /*
* The TSC_ADC_Subsystem has 2 clock domains * The TSC_ADC_Subsystem has 2 clock domains: OCP_CLK and ADC_CLK.
* OCP_CLK and ADC_CLK. * ADCs produce a 12-bit sample every 15 ADC_CLK cycles.
* The ADC clock is expected to run at target of 3MHz, * am33xx ADCs expect to capture 200ksps.
* and expected to capture 12-bit data at a rate of 200 KSPS. * We need the ADC clocks to run at 3MHz.
* The TSC_ADC_SS controller design assumes the OCP clock is * This frequency is valid since TSC_ADC_SS controller design
* at least 6x faster than the ADC clock. * assumes the OCP clock is at least 6x faster than the ADC clock.
*/ */
clk = devm_clk_get(&pdev->dev, "adc_tsc_fck"); clk = devm_clk_get(&pdev->dev, "adc_tsc_fck");
if (IS_ERR(clk)) { if (IS_ERR(clk)) {