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net: dsa: mt7530: setup core clock even in TRGMII mode

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A recent change to MIPS ralink reset logic made it so mt7530 actually
resets the switch on platforms such as mt7621 (where bit 2 is the reset
line for the switch). That exposed an issue where the switch would not
function properly in TRGMII mode after a reset.

Reconfigure core clock in TRGMII mode to fix the issue.

Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled.

Fixes: 3f9ef7785a ("MIPS: ralink: manage low reset lines")
Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Ilya Lipnitskiy 2021-03-12 00:07:03 -08:00 committed by David S. Miller
parent 2e5de7e0c8
commit c3b8e07909
1 changed files with 22 additions and 24 deletions
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46
drivers/net/dsa/mt7530.c
View file

@ -436,34 +436,32 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
TD_DM_DRVP(8) | TD_DM_DRVN(8));
/* Setup core clock for MT7530 */
if (!trgint) {
/* Disable MT7530 core clock */
core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
/* Disable MT7530 core clock */
core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
/* Disable PLL, since phy_device has not yet been created
* provided for phy_[read,write]_mmd_indirect is called, we
* provide our own core_write_mmd_indirect to complete this
* function.
*/
core_write_mmd_indirect(priv,
CORE_GSWPLL_GRP1,
MDIO_MMD_VEND2,
0);
/* Disable PLL, since phy_device has not yet been created
* provided for phy_[read,write]_mmd_indirect is called, we
* provide our own core_write_mmd_indirect to complete this
* function.
*/
core_write_mmd_indirect(priv,
CORE_GSWPLL_GRP1,
MDIO_MMD_VEND2,
0);
/* Set core clock into 500Mhz */
core_write(priv, CORE_GSWPLL_GRP2,
RG_GSWPLL_POSDIV_500M(1) |
RG_GSWPLL_FBKDIV_500M(25));
/* Set core clock into 500Mhz */
core_write(priv, CORE_GSWPLL_GRP2,
RG_GSWPLL_POSDIV_500M(1) |
RG_GSWPLL_FBKDIV_500M(25));
/* Enable PLL */
core_write(priv, CORE_GSWPLL_GRP1,
RG_GSWPLL_EN_PRE |
RG_GSWPLL_POSDIV_200M(2) |
RG_GSWPLL_FBKDIV_200M(32));
/* Enable PLL */
core_write(priv, CORE_GSWPLL_GRP1,
RG_GSWPLL_EN_PRE |
RG_GSWPLL_POSDIV_200M(2) |
RG_GSWPLL_FBKDIV_200M(32));
/* Enable MT7530 core clock */
core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
}
/* Enable MT7530 core clock */
core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
/* Setup the MT7530 TRGMII Tx Clock */
core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);