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https://github.com/torvalds/linux
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pci-v5.19-fixes-1
-----BEGIN PGP SIGNATURE----- iQJIBAABCgAyFiEEgMe7l+5h9hnxdsnuWYigwDrT+vwFAmKZAhoUHGJoZWxnYWFz QGdvb2dsZS5jb20ACgkQWYigwDrT+vwSExAAivmUZMWfGT0DuLVZNLWI4HtcxktW bIhgl+yU+YGF9RaBjSUSjlbg2cC1BjxUkO3NItjpfGUYRwdTsNo5FFmUoMAwQxXB wUmTGH8dpzePzNp+Do0U4usD1ohtIHjxTWGQrKfreXp1U4yD57CB9e6F0b9wUDRj WOZB6N5MnrcWUmbYMpgdUShgWR1wCl634T/seBc5ZAOuT3ierLHQkbDjVtMPt83w ezKag9fu248EwmfLe1M6lRfgxLqBW9B7IkeIqHVr6xi6xjizsddvlD2XHXpuEaMW lxZLNobC3hM+V/nmML2836GbLC1pX9iG+CKezzCWes2tM+Tsf9gvVY4NLlB3wgK4 svpUNQEwflLc/f0mcP2lsPPzM5p3fPN5QsILWx+eTHeIRQDVO2ddzWNFIXCBcFNf sgubApxxhHGzkGbqNVUkZssaO/lNMH2o6xP/8hc6DCT+JxE/OcRZ+l6uA3L84Tmc sCwAqAy3DPpwwIJtklSPrlxUDy1GVKUuf8puOu5mYzrGD0aJ3xk0GtF96fbXoGkX 1mKWdQgA/PjvgUR/th3PBSI3z4ZxDuC/VQXlPRIk3FkrNsnrs0Y9EekFFWvlKeoI 6dZNZc2NvBMkEGF4L9ymzUW+tqODddJLlpdeC8RIwKGtsxFalHf9a8eotPJueUn7 hx1XT4BnCeV8Yco= =4NaF -----END PGP SIGNATURE----- Merge tag 'pci-v5.19-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull pci fixes from Bjorn Helgaas: - Revert brcmstb patches that broke booting on Raspberry Pi Compute Module 4 (Bjorn Helgaas) - Fix bridge_d3_blacklist[] error that overwrote the existing Gigabyte X299 entry instead of adding a new one (Bjorn Helgaas) - Update Lorenzo Pieralisi's email address in MAINTAINERS (Lorenzo Pieralisi) * tag 'pci-v5.19-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: MAINTAINERS: Update Lorenzo Pieralisi's email address PCI/PM: Fix bridge_d3_blacklist[] Elo i2 overwrite of Gigabyte X299 Revert "PCI: brcmstb: Split brcm_pcie_setup() into two funcs" Revert "PCI: brcmstb: Add mechanism to turn on subdev regulators" Revert "PCI: brcmstb: Add control of subdevice voltage regulators" Revert "PCI: brcmstb: Do not turn off WOL regulators on suspend"
This commit is contained in:
Linus Torvalds
commit
c399c85d60
1
.mailmap
1
.mailmap
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@ -236,6 +236,7 @@ Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@web.de>
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|||
<linux-hardening@vger.kernel.org> <kernel-hardening@lists.openwall.com>
|
||||
Li Yang <leoyang.li@nxp.com> <leoli@freescale.com>
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||||
Li Yang <leoyang.li@nxp.com> <leo@zh-kernel.org>
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||||
Lorenzo Pieralisi <lpieralisi@kernel.org> <lorenzo.pieralisi@arm.com>
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||||
Lukasz Luba <lukasz.luba@arm.com> <l.luba@partner.samsung.com>
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||||
Maciej W. Rozycki <macro@mips.com> <macro@imgtec.com>
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Maciej W. Rozycki <macro@orcam.me.uk> <macro@linux-mips.org>
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||||
|
|
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16
MAINTAINERS
16
MAINTAINERS
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|
@ -382,7 +382,7 @@ F: include/acpi/
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F: tools/power/acpi/
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ACPI FOR ARM64 (ACPI/arm64)
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M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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M: Lorenzo Pieralisi <lpieralisi@kernel.org>
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M: Hanjun Guo <guohanjun@huawei.com>
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||||
M: Sudeep Holla <sudeep.holla@arm.com>
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L: linux-acpi@vger.kernel.org
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||||
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@ -2940,7 +2940,7 @@ N: uniphier
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ARM/VERSATILE EXPRESS PLATFORM
|
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M: Liviu Dudau <liviu.dudau@arm.com>
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M: Sudeep Holla <sudeep.holla@arm.com>
|
||||
M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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M: Lorenzo Pieralisi <lpieralisi@kernel.org>
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||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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||||
S: Maintained
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||||
F: */*/*/vexpress*
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||||
|
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@ -5156,7 +5156,7 @@ F: arch/x86/kernel/cpuid.c
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F: arch/x86/kernel/msr.c
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CPUIDLE DRIVER - ARM BIG LITTLE
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M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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||||
M: Lorenzo Pieralisi <lpieralisi@kernel.org>
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||||
M: Daniel Lezcano <daniel.lezcano@linaro.org>
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L: linux-pm@vger.kernel.org
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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||||
|
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@ -5176,7 +5176,7 @@ F: drivers/cpuidle/cpuidle-exynos.c
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F: include/linux/platform_data/cpuidle-exynos.h
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CPUIDLE DRIVER - ARM PSCI
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M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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M: Lorenzo Pieralisi <lpieralisi@kernel.org>
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M: Sudeep Holla <sudeep.holla@arm.com>
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L: linux-pm@vger.kernel.org
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||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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|
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@ -15282,7 +15282,7 @@ F: drivers/pci/controller/pci-v3-semi.c
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PCI ENDPOINT SUBSYSTEM
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M: Kishon Vijay Abraham I <kishon@ti.com>
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M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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M: Lorenzo Pieralisi <lpieralisi@kernel.org>
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R: Krzysztof Wilczyński <kw@linux.com>
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L: linux-pci@vger.kernel.org
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S: Supported
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@ -15345,7 +15345,7 @@ F: Documentation/devicetree/bindings/pci/xgene-pci-msi.txt
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F: drivers/pci/controller/pci-xgene-msi.c
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PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS
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M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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M: Lorenzo Pieralisi <lpieralisi@kernel.org>
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R: Rob Herring <robh@kernel.org>
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R: Krzysztof Wilczyński <kw@linux.com>
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L: linux-pci@vger.kernel.org
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@ -15898,7 +15898,7 @@ F: include/linux/dtpm.h
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POWER STATE COORDINATION INTERFACE (PSCI)
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M: Mark Rutland <mark.rutland@arm.com>
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M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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M: Lorenzo Pieralisi <lpieralisi@kernel.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: drivers/firmware/psci/
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@ -18285,7 +18285,7 @@ F: drivers/net/ethernet/smsc/smc91x.*
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SECURE MONITOR CALL(SMC) CALLING CONVENTION (SMCCC)
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M: Mark Rutland <mark.rutland@arm.com>
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M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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||||
M: Lorenzo Pieralisi <lpieralisi@kernel.org>
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||||
M: Sudeep Holla <sudeep.holla@arm.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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||||
S: Maintained
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|
|
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@ -24,7 +24,6 @@
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#include <linux/pci.h>
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#include <linux/pci-ecam.h>
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#include <linux/printk.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <linux/sizes.h>
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#include <linux/slab.h>
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@ -196,8 +195,6 @@ static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie,
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static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val);
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static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val);
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static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val);
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static int brcm_pcie_linkup(struct brcm_pcie *pcie);
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static int brcm_pcie_add_bus(struct pci_bus *bus);
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enum {
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RGR1_SW_INIT_1,
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@ -286,14 +283,6 @@ static const struct pcie_cfg_data bcm2711_cfg = {
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.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
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};
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struct subdev_regulators {
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unsigned int num_supplies;
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struct regulator_bulk_data supplies[];
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};
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static int pci_subdev_regulators_add_bus(struct pci_bus *bus);
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static void pci_subdev_regulators_remove_bus(struct pci_bus *bus);
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struct brcm_msi {
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struct device *dev;
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void __iomem *base;
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@ -331,9 +320,6 @@ struct brcm_pcie {
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u32 hw_rev;
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void (*perst_set)(struct brcm_pcie *pcie, u32 val);
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void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
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bool refusal_mode;
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struct subdev_regulators *sr;
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bool ep_wakeup_capable;
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};
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static inline bool is_bmips(const struct brcm_pcie *pcie)
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@ -450,99 +436,6 @@ static int brcm_pcie_set_ssc(struct brcm_pcie *pcie)
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return ssc && pll ? 0 : -EIO;
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}
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static void *alloc_subdev_regulators(struct device *dev)
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{
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static const char * const supplies[] = {
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"vpcie3v3",
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"vpcie3v3aux",
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"vpcie12v",
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};
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const size_t size = sizeof(struct subdev_regulators)
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+ sizeof(struct regulator_bulk_data) * ARRAY_SIZE(supplies);
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struct subdev_regulators *sr;
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int i;
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sr = devm_kzalloc(dev, size, GFP_KERNEL);
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if (sr) {
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sr->num_supplies = ARRAY_SIZE(supplies);
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for (i = 0; i < ARRAY_SIZE(supplies); i++)
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sr->supplies[i].supply = supplies[i];
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}
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return sr;
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}
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static int pci_subdev_regulators_add_bus(struct pci_bus *bus)
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{
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struct device *dev = &bus->dev;
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struct subdev_regulators *sr;
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int ret;
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if (!dev->of_node || !bus->parent || !pci_is_root_bus(bus->parent))
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return 0;
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if (dev->driver_data)
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dev_err(dev, "dev.driver_data unexpectedly non-NULL\n");
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sr = alloc_subdev_regulators(dev);
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if (!sr)
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return -ENOMEM;
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dev->driver_data = sr;
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ret = regulator_bulk_get(dev, sr->num_supplies, sr->supplies);
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if (ret)
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return ret;
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ret = regulator_bulk_enable(sr->num_supplies, sr->supplies);
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if (ret) {
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dev_err(dev, "failed to enable regulators for downstream device\n");
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return ret;
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}
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return 0;
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}
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static int brcm_pcie_add_bus(struct pci_bus *bus)
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{
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struct device *dev = &bus->dev;
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struct brcm_pcie *pcie = (struct brcm_pcie *) bus->sysdata;
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int ret;
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if (!dev->of_node || !bus->parent || !pci_is_root_bus(bus->parent))
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return 0;
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ret = pci_subdev_regulators_add_bus(bus);
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if (ret)
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return ret;
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/* Grab the regulators for suspend/resume */
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pcie->sr = bus->dev.driver_data;
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/*
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* If we have failed linkup there is no point to return an error as
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* currently it will cause a WARNING() from pci_alloc_child_bus().
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* We return 0 and turn on the "refusal_mode" so that any further
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* accesses to the pci_dev just get 0xffffffff
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*/
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if (brcm_pcie_linkup(pcie) != 0)
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pcie->refusal_mode = true;
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return 0;
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}
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static void pci_subdev_regulators_remove_bus(struct pci_bus *bus)
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{
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struct device *dev = &bus->dev;
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struct subdev_regulators *sr = dev->driver_data;
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if (!sr || !bus->parent || !pci_is_root_bus(bus->parent))
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return;
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if (regulator_bulk_disable(sr->num_supplies, sr->supplies))
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dev_err(dev, "failed to disable regulators for downstream device\n");
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dev->driver_data = NULL;
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}
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/* Limits operation to a specific generation (1, 2, or 3) */
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static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen)
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{
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@ -858,18 +751,6 @@ static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
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/* Accesses to the RC go right to the RC registers if slot==0 */
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if (pci_is_root_bus(bus))
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return PCI_SLOT(devfn) ? NULL : base + where;
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if (pcie->refusal_mode) {
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/*
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* At this point we do not have link. There will be a CPU
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* abort -- a quirk with this controller --if Linux tries
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* to read any config-space registers besides those
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* targeting the host bridge. To prevent this we hijack
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* the address to point to a safe access that will return
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* 0xffffffff.
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*/
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writel(0xffffffff, base + PCIE_MISC_RC_BAR2_CONFIG_HI);
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return base + PCIE_MISC_RC_BAR2_CONFIG_HI + (where & 0x3);
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}
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/* For devices, write to the config space index register */
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idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0);
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@ -898,8 +779,6 @@ static struct pci_ops brcm_pcie_ops = {
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.map_bus = brcm_pcie_map_conf,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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.add_bus = brcm_pcie_add_bus,
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.remove_bus = pci_subdev_regulators_remove_bus,
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};
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static struct pci_ops brcm_pcie_ops32 = {
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@ -1047,9 +926,16 @@ static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
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static int brcm_pcie_setup(struct brcm_pcie *pcie)
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{
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struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
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u64 rc_bar2_offset, rc_bar2_size;
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void __iomem *base = pcie->base;
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int ret, memc;
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struct device *dev = pcie->dev;
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struct resource_entry *entry;
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bool ssc_good = false;
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struct resource *res;
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int num_out_wins = 0;
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u16 nlw, cls, lnksta;
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int i, ret, memc;
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u32 tmp, burst, aspm_support;
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/* Reset the bridge */
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@ -1139,40 +1025,6 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
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if (pcie->gen)
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brcm_pcie_set_gen(pcie, pcie->gen);
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/* Don't advertise L0s capability if 'aspm-no-l0s' */
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aspm_support = PCIE_LINK_STATE_L1;
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if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
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aspm_support |= PCIE_LINK_STATE_L0S;
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tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
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u32p_replace_bits(&tmp, aspm_support,
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PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
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writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
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/*
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* For config space accesses on the RC, show the right class for
|
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* a PCIe-PCIe bridge (the default setting is to be EP mode).
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*/
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tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3);
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u32p_replace_bits(&tmp, 0x060400,
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PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK);
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writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3);
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return 0;
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}
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static int brcm_pcie_linkup(struct brcm_pcie *pcie)
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{
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struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
|
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struct device *dev = pcie->dev;
|
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void __iomem *base = pcie->base;
|
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struct resource_entry *entry;
|
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struct resource *res;
|
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int num_out_wins = 0;
|
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u16 nlw, cls, lnksta;
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bool ssc_good = false;
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u32 tmp;
|
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int ret, i;
|
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|
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/* Unassert the fundamental reset */
|
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pcie->perst_set(pcie, 0);
|
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|
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|
|
@ -1223,6 +1075,24 @@ static int brcm_pcie_linkup(struct brcm_pcie *pcie)
|
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num_out_wins++;
|
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}
|
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|
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/* Don't advertise L0s capability if 'aspm-no-l0s' */
|
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aspm_support = PCIE_LINK_STATE_L1;
|
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if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
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aspm_support |= PCIE_LINK_STATE_L0S;
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tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
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u32p_replace_bits(&tmp, aspm_support,
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PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
|
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writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
|
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|
||||
/*
|
||||
* For config space accesses on the RC, show the right class for
|
||||
* a PCIe-PCIe bridge (the default setting is to be EP mode).
|
||||
*/
|
||||
tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3);
|
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u32p_replace_bits(&tmp, 0x060400,
|
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PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK);
|
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writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3);
|
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|
||||
if (pcie->ssc) {
|
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ret = brcm_pcie_set_ssc(pcie);
|
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if (ret == 0)
|
||||
|
|
@ -1351,21 +1221,9 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie)
|
|||
pcie->bridge_sw_init_set(pcie, 1);
|
||||
}
|
||||
|
||||
static int pci_dev_may_wakeup(struct pci_dev *dev, void *data)
|
||||
{
|
||||
bool *ret = data;
|
||||
|
||||
if (device_may_wakeup(&dev->dev)) {
|
||||
*ret = true;
|
||||
dev_info(&dev->dev, "disable cancelled for wake-up device\n");
|
||||
}
|
||||
return (int) *ret;
|
||||
}
|
||||
|
||||
static int brcm_pcie_suspend(struct device *dev)
|
||||
{
|
||||
struct brcm_pcie *pcie = dev_get_drvdata(dev);
|
||||
struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
|
||||
int ret;
|
||||
|
||||
brcm_pcie_turn_off(pcie);
|
||||
|
|
@ -1383,25 +1241,6 @@ static int brcm_pcie_suspend(struct device *dev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
if (pcie->sr) {
|
||||
/*
|
||||
* Now turn off the regulators, but if at least one
|
||||
* downstream device is enabled as a wake-up source, do not
|
||||
* turn off regulators.
|
||||
*/
|
||||
pcie->ep_wakeup_capable = false;
|
||||
pci_walk_bus(bridge->bus, pci_dev_may_wakeup,
|
||||
&pcie->ep_wakeup_capable);
|
||||
if (!pcie->ep_wakeup_capable) {
|
||||
ret = regulator_bulk_disable(pcie->sr->num_supplies,
|
||||
pcie->sr->supplies);
|
||||
if (ret) {
|
||||
dev_err(dev, "Could not turn off regulators\n");
|
||||
reset_control_reset(pcie->rescal);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
}
|
||||
clk_disable_unprepare(pcie->clk);
|
||||
|
||||
return 0;
|
||||
|
|
@ -1419,28 +1258,9 @@ static int brcm_pcie_resume(struct device *dev)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (pcie->sr) {
|
||||
if (pcie->ep_wakeup_capable) {
|
||||
/*
|
||||
* We are resuming from a suspend. In the suspend we
|
||||
* did not disable the power supplies, so there is
|
||||
* no need to enable them (and falsely increase their
|
||||
* usage count).
|
||||
*/
|
||||
pcie->ep_wakeup_capable = false;
|
||||
} else {
|
||||
ret = regulator_bulk_enable(pcie->sr->num_supplies,
|
||||
pcie->sr->supplies);
|
||||
if (ret) {
|
||||
dev_err(dev, "Could not turn on regulators\n");
|
||||
goto err_disable_clk;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
ret = reset_control_reset(pcie->rescal);
|
||||
if (ret)
|
||||
goto err_regulator;
|
||||
goto err_disable_clk;
|
||||
|
||||
ret = brcm_phy_start(pcie);
|
||||
if (ret)
|
||||
|
|
@ -1461,10 +1281,6 @@ static int brcm_pcie_resume(struct device *dev)
|
|||
if (ret)
|
||||
goto err_reset;
|
||||
|
||||
ret = brcm_pcie_linkup(pcie);
|
||||
if (ret)
|
||||
goto err_reset;
|
||||
|
||||
if (pcie->msi)
|
||||
brcm_msi_set_regs(pcie->msi);
|
||||
|
||||
|
|
@ -1472,9 +1288,6 @@ static int brcm_pcie_resume(struct device *dev)
|
|||
|
||||
err_reset:
|
||||
reset_control_rearm(pcie->rescal);
|
||||
err_regulator:
|
||||
if (pcie->sr)
|
||||
regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies);
|
||||
err_disable_clk:
|
||||
clk_disable_unprepare(pcie->clk);
|
||||
return ret;
|
||||
|
|
@ -1606,17 +1419,7 @@ static int brcm_pcie_probe(struct platform_device *pdev)
|
|||
|
||||
platform_set_drvdata(pdev, pcie);
|
||||
|
||||
ret = pci_host_probe(bridge);
|
||||
if (!ret && !brcm_pcie_link_up(pcie))
|
||||
ret = -ENODEV;
|
||||
|
||||
if (ret) {
|
||||
brcm_pcie_remove(pdev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
return pci_host_probe(bridge);
|
||||
fail:
|
||||
__brcm_pcie_remove(pcie);
|
||||
return ret;
|
||||
|
|
@ -1625,8 +1428,8 @@ static int brcm_pcie_probe(struct platform_device *pdev)
|
|||
MODULE_DEVICE_TABLE(of, brcm_pcie_match);
|
||||
|
||||
static const struct dev_pm_ops brcm_pcie_pm_ops = {
|
||||
.suspend_noirq = brcm_pcie_suspend,
|
||||
.resume_noirq = brcm_pcie_resume,
|
||||
.suspend = brcm_pcie_suspend,
|
||||
.resume = brcm_pcie_resume,
|
||||
};
|
||||
|
||||
static struct platform_driver brcm_pcie_driver = {
|
||||
|
|
|
|||
|
|
@ -2967,6 +2967,8 @@ static const struct dmi_system_id bridge_d3_blacklist[] = {
|
|||
DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
|
||||
DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
|
||||
},
|
||||
},
|
||||
{
|
||||
/*
|
||||
* Downstream device is not accessible after putting a root port
|
||||
* into D3cold and back into D0 on Elo i2.
|
||||
|
|
|
|||
Loading…
Reference in a new issue