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https://github.com/torvalds/linux
synced 2024-07-22 19:21:07 +00:00
MIPS: Remove unused R8000 CPU support
Our R8000 CPU support can only be included if a system selects CONFIG_SYS_HAS_CPU_R8000. No system does, making all R8000-related CPU support dead code. Remove it. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
This commit is contained in:
Paul Burton
parent
ccd51b9fc3
commit
c2aeaaea17
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@ -1652,16 +1652,6 @@ config CPU_NEVADA
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help
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QED / PMC-Sierra RM52xx-series ("Nevada") processors.
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config CPU_R8000
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bool "R8000"
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depends on SYS_HAS_CPU_R8000
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select CPU_HAS_PREFETCH
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select CPU_HAS_LOAD_STORE_LR
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select CPU_SUPPORTS_64BIT_KERNEL
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help
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MIPS Technologies R8000 processors. Note these processors are
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uncommon and the support for them is incomplete.
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config CPU_R10000
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bool "R10000"
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depends on SYS_HAS_CPU_R10000
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@ -1969,9 +1959,6 @@ config SYS_HAS_CPU_R5500
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config SYS_HAS_CPU_NEVADA
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bool
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config SYS_HAS_CPU_R8000
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bool
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config SYS_HAS_CPU_R10000
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bool
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select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
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@ -2172,13 +2159,13 @@ config PAGE_SIZE_4KB
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config PAGE_SIZE_8KB
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bool "8kB"
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depends on CPU_R8000 || CPU_CAVIUM_OCTEON
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depends on CPU_CAVIUM_OCTEON
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depends on !MIPS_VA_BITS_48
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help
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Using 8kB page size will result in higher performance kernel at
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the price of higher memory consumption. This option is available
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only on R8000 and cnMIPS processors. Note that you will need a
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suitable Linux distribution to support this.
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only on cnMIPS processors. Note that you will need a suitable Linux
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distribution to support this.
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config PAGE_SIZE_16KB
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bool "16kB"
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@ -2269,7 +2256,7 @@ config CPU_HAS_PREFETCH
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config CPU_GENERIC_DUMP_TLB
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bool
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default y if !(CPU_R3000 || CPU_R8000 || CPU_TX39XX)
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default y if !(CPU_R3000 || CPU_TX39XX)
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config MIPS_FP_SUPPORT
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bool "Floating Point support" if EXPERT
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@ -2298,7 +2285,7 @@ config CPU_R4K_FPU
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config CPU_R4K_CACHE_TLB
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bool
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default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
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default y if !(CPU_R3000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
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config MIPS_MT_SMP
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bool "MIPS MT SMP support (1 TC on each available VPE)"
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@ -2555,7 +2542,6 @@ config CPU_R4400_WORKAROUNDS
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config MIPS_ASID_SHIFT
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int
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default 6 if CPU_R3000 || CPU_TX39XX
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default 4 if CPU_R8000
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default 0
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config MIPS_ASID_BITS
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@ -183,7 +183,6 @@ cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=r5000) \
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-Wa,--trap
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cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mdmx)
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cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mips3d)
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cflags-$(CONFIG_CPU_R8000) += -march=r8000 -Wa,--trap
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cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \
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-Wa,--trap
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cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += $(call cc-option,-march=octeon) -Wa,--trap
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@ -135,18 +135,9 @@
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*/
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#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */
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#ifndef CONFIG_CPU_R8000
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/*
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* The R8000 doesn't have the 32-bit compat spaces so we don't define them
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* in order to catch bugs in the source code.
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*/
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#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000)
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#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
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#endif
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#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK)
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#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE)
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@ -146,10 +146,6 @@ static inline int __pure __get_cpu_type(const int cpu_type)
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case CPU_NEVADA:
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#endif
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#ifdef CONFIG_SYS_HAS_CPU_R8000
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case CPU_R8000:
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#endif
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#ifdef CONFIG_SYS_HAS_CPU_R10000
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case CPU_R10000:
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case CPU_R12000:
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@ -300,11 +300,6 @@ enum cpu_type_enum {
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CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
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CPU_SR71000, CPU_TX49XX,
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/*
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* R8000 class processors
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*/
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CPU_R8000,
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/*
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* TX3900 class processors
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*/
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@ -113,8 +113,6 @@ search_module_dbetables(unsigned long addr)
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#define MODULE_PROC_FAMILY "R5500 "
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#elif defined CONFIG_CPU_NEVADA
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#define MODULE_PROC_FAMILY "NEVADA "
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#elif defined CONFIG_CPU_R8000
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#define MODULE_PROC_FAMILY "R8000 "
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#elif defined CONFIG_CPU_R10000
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#define MODULE_PROC_FAMILY "R10000 "
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#elif defined CONFIG_CPU_RM7000
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@ -1491,15 +1491,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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*/
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c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
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break;
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case PRID_IMP_R8000:
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c->cputype = CPU_R8000;
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__cpu_name[cpu] = "RM8000";
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set_isa(c, MIPS_CPU_ISA_IV);
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c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
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MIPS_CPU_FPU | MIPS_CPU_32FPR |
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MIPS_CPU_LLSC;
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c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
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break;
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case PRID_IMP_R10000:
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c->cputype = CPU_R10000;
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__cpu_name[cpu] = "R10000";
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@ -30,7 +30,6 @@ obj-$(CONFIG_DMA_NONCOHERENT) += dma-noncoherent.o
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obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o
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obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o
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obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o tlb-r8k.o
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obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o
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obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o
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obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o
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@ -1,239 +0,0 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
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* Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle ralf@gnu.org
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
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*/
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/mm.h>
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#include <asm/cpu.h>
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#include <asm/bootinfo.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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extern void build_tlb_refill_handler(void);
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#define TFP_TLB_SIZE 384
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#define TFP_TLB_SET_SHIFT 7
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/* CP0 hazard avoidance. */
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#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
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"nop; nop; nop; nop; nop; nop;\n\t" \
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".set reorder\n\t")
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void local_flush_tlb_all(void)
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{
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unsigned long flags;
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unsigned long old_ctx;
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int entry;
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local_irq_save(flags);
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/* Save old context and create impossible VPN2 value */
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old_ctx = read_c0_entryhi();
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write_c0_entrylo(0);
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for (entry = 0; entry < TFP_TLB_SIZE; entry++) {
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write_c0_tlbset(entry >> TFP_TLB_SET_SHIFT);
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write_c0_vaddr(entry << PAGE_SHIFT);
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write_c0_entryhi(CKSEG0 + (entry << (PAGE_SHIFT + 1)));
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mtc0_tlbw_hazard();
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tlb_write();
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}
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tlbw_use_hazard();
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write_c0_entryhi(old_ctx);
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local_irq_restore(flags);
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}
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void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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int cpu = smp_processor_id();
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unsigned long flags;
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int oldpid, newpid, size;
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if (!cpu_context(cpu, mm))
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return;
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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size = (size + 1) >> 1;
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local_irq_save(flags);
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if (size > TFP_TLB_SIZE / 2) {
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drop_mmu_context(mm);
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goto out_restore;
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}
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oldpid = read_c0_entryhi();
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newpid = cpu_asid(cpu, mm);
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write_c0_entrylo(0);
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start &= PAGE_MASK;
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end += (PAGE_SIZE - 1);
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end &= PAGE_MASK;
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while (start < end) {
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signed long idx;
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write_c0_vaddr(start);
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write_c0_entryhi(start);
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start += PAGE_SIZE;
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tlb_probe();
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idx = read_c0_tlbset();
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if (idx < 0)
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continue;
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write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1)));
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tlb_write();
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}
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write_c0_entryhi(oldpid);
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out_restore:
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local_irq_restore(flags);
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}
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/* Usable for KV1 addresses only! */
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void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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unsigned long size, flags;
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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size = (size + 1) >> 1;
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if (size > TFP_TLB_SIZE / 2) {
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local_flush_tlb_all();
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return;
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}
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local_irq_save(flags);
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write_c0_entrylo(0);
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start &= PAGE_MASK;
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end += (PAGE_SIZE - 1);
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end &= PAGE_MASK;
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while (start < end) {
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signed long idx;
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write_c0_vaddr(start);
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write_c0_entryhi(start);
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start += PAGE_SIZE;
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tlb_probe();
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idx = read_c0_tlbset();
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if (idx < 0)
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continue;
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write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1)));
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tlb_write();
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}
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local_irq_restore(flags);
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}
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void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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{
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int cpu = smp_processor_id();
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unsigned long flags;
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int oldpid, newpid;
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signed long idx;
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if (!cpu_context(cpu, vma->vm_mm))
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return;
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newpid = cpu_asid(cpu, vma->vm_mm);
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page &= PAGE_MASK;
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local_irq_save(flags);
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oldpid = read_c0_entryhi();
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write_c0_vaddr(page);
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write_c0_entryhi(newpid);
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tlb_probe();
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idx = read_c0_tlbset();
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if (idx < 0)
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goto finish;
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write_c0_entrylo(0);
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write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT + 1)));
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tlb_write();
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finish:
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write_c0_entryhi(oldpid);
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local_irq_restore(flags);
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}
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/*
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* We will need multiple versions of update_mmu_cache(), one that just
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* updates the TLB with the new pte(s), and another which also checks
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* for the R4k "end of page" hardware bug and does the needy.
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*/
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void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
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{
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unsigned long flags;
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pgd_t *pgdp;
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pmd_t *pmdp;
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pte_t *ptep;
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int pid;
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/*
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* Handle debugger faulting in for debugee.
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*/
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if (current->active_mm != vma->vm_mm)
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return;
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pid = read_c0_entryhi() & cpu_asid_mask(¤t_cpu_data);
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local_irq_save(flags);
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address &= PAGE_MASK;
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write_c0_vaddr(address);
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write_c0_entryhi(pid);
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pgdp = pgd_offset(vma->vm_mm, address);
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pmdp = pmd_offset(pgdp, address);
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ptep = pte_offset_map(pmdp, address);
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tlb_probe();
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write_c0_entrylo(pte_val(*ptep++) >> 6);
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tlb_write();
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write_c0_entryhi(pid);
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local_irq_restore(flags);
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}
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static void probe_tlb(unsigned long config)
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{
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struct cpuinfo_mips *c = ¤t_cpu_data;
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c->tlbsize = 3 * 128; /* 3 sets each 128 entries */
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}
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void tlb_init(void)
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{
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unsigned int config = read_c0_config();
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unsigned long status;
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probe_tlb(config);
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status = read_c0_status();
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status &= ~(ST0_UPS | ST0_KPS);
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#ifdef CONFIG_PAGE_SIZE_4KB
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status |= (TFP_PAGESIZE_4K << 32) | (TFP_PAGESIZE_4K << 36);
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#elif defined(CONFIG_PAGE_SIZE_8KB)
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status |= (TFP_PAGESIZE_8K << 32) | (TFP_PAGESIZE_8K << 36);
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#elif defined(CONFIG_PAGE_SIZE_16KB)
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status |= (TFP_PAGESIZE_16K << 32) | (TFP_PAGESIZE_16K << 36);
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#elif defined(CONFIG_PAGE_SIZE_64KB)
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status |= (TFP_PAGESIZE_64K << 32) | (TFP_PAGESIZE_64K << 36);
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#endif
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write_c0_status(status);
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write_c0_wired(0);
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local_flush_tlb_all();
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build_tlb_refill_handler();
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}
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@ -2633,10 +2633,6 @@ void build_tlb_refill_handler(void)
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#endif
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break;
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case CPU_R8000:
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panic("No R8000 TLB refill handler yet");
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break;
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default:
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if (cpu_has_ldpte)
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setup_pw();
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